University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown. All 5 problems must be completed. Calculators allowed. Closed book = No text or notes allowed. Clearly label all final answers. Name: Grade: Q1 Q2 Q Q4 Q5 Total 1
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Formulas and Data Friday, May th Physical Constants: n i = intrinsic concentration (undoped) silicon = 1.45 10 10 cm @ 00 K k = Boltzman s constant = 1.8 10 2 J/ K q = electronic charge = 1.0 10 19 C 1 angstrom = 10 8 cm ɛ Si = permittivity of Si = 1.0 10 12 F/cm ɛ SiO2 = ɛ ox = permittivity of SiO 2 = 0.4 10 12 F/cm MOS Transistor IV Characteristics: nmos: pmos: V GS V DS Mode I DS ) V GS V T h e nkt /q ( 1 e V DS kt /q ) (1 + λv DS ) V T h Subthreshold ( I W S L > V T h < V GS V T h Resistive k n2 (2(V GS V T h )V DS VDS)(1 2 + λv DS ) V GS V T h Saturation k n2 (V GS V T h ) 2 (1 + λv DS ) k n = µ n C ox W n L n V GS V DS Mode I DS ) V GS V T h e nkt /q ( 1 e V DS kt /q ) (1 + λv DS ) V T h Subthreshold ( I W S L < V T h > V GS V T h Resistive k n2 (2(V GS V T h )V DS VDS)(1 2 + λv DS ) V GS V T h Saturation k n2 (V GS V T h ) 2 (1 + λv DS ) k p = µ p C ox W p L p Threshold Voltage: V T h = V T 0 + γ ( 2φ F + V SB 2φ F ) (p-sub) φ F = kt ln n i q N A γ = 2ɛ Si qn A C ox and (n-sub) φ F = kt q ln N D ni 2
CMOS Capacitors: C ox = ɛox t ox C O = C GSO = C GDO = C ox W L D MOS Gate Capacitance: MOS Diffusion Capacitance: C diff = C db = A D C j0 + P D C j0sw A D = Area of diffusion region P D = Perimeter of diffusion region Static/Dynamic Characteristics of Gates: V 50% = 1 2 (V OL + V OH ) τ P HL = time for output voltage to fall from V OH to V 50% τ P LH = time for output voltage to rise from V OL to V 50% τ P = τ P HL+τ P LH 2 Average Current Delay Model: τ P HL = C load V HL I avg,hl = C load(v OH V 50% ) I avg,hl τ P LH = C load V LH I avg,lh = C load(v 50% V OL ) I avg,lh First-order RC Delay Model: τ P HL = 0.9 C load R P D τ P LH = 0.9 C load R P U Power Equations: P tot = P dyn + P SC + P stat P dyn = dynamic power = a ( ) 1 Cload V 2 f 2 P SC = short circuit power = ac SC V 2 f P stat = static power = V I stat where a=acitivity factor, f=switching frequency
For this question: All transistors W=L=1. The unit resistance of an nmos with W=L=1 is R un. The unit resistance of a pmos with W=L=1 is R up = R un. The gate capacitance and diffusion capacitance of a unit nmos and pmos are C g and C diff respectively. Assume all inputs are driven by R un drive with 2C diff self load. Assume all outputs are loaded by 4C g load. Assume the select inputs are not switching they are set once before the circuit operates and does not change during operation 1. (40 points) A barrel shifter is a digital circuit that can shift the bits in a data word by a specified number of bits. For example the 8-bit data word 10110011 shifted by bits results in the 8-bit data word 10110000. The bits are shifted to the left and shifts in 0s. (a) Below is an implementation of a variable barrel shifter with an 8-bit input and 8-bit output with a -bit shift select specifying the number of bits to be shifted. This implementation is to use a simple 2-input multiplexer (mux): 4
The following 2-input multiplexer implementation using pass transistors and a CMOS inverter shown below is used: Using the first-order RC model, report delay from this R un input driver driving the inputs through to the output of this circuit. Assume all data inputs arrive at the same time, and give answer in terms of R un and C g. Show work for partial credit. 5
(b) Another implementation of the same shift operation is to use an array of pass gates as shown below, where now there are 7 select signals specifying the number of bits to shift where only one select signal is high at a time. Using the first-order RC model, report delay from this R un input driver driving the inputs through to the output of this circuit. Assume all data inputs arrive at the same time, and give answer in terms of R un and C g. Show work for partial credit.
(c) Compare and comment on the difference in the delay of the two implementations. What is the difference between the designs that contributes to the faster implementation being faster? (d) What additional circuit do you need to add to the implementation in (b) for fair comparison of designs such that the inputs and outputs are the same? 7
2. (20 points) Consider the following two circuits. Which work correctly and at what speed? Assume each circuit is driven by R un drive input and is loaded by 10C g output. Assume C diff = 0.5C g, µ n = 2µ p. Assume the CLK signal is driven strongly such that the rise time on the clock is negligible (i.e you don t need to include driving the CLK signal). Use Elmore delay calculations where appropriate. For full credit (and partial credit consideration) show your evaluate delay components (stages, components of Elmore delay calculation). CLK 10 10 out 10 (a) Does it work? Reason it doesn t work? (if it does not) Evaluate Delay (if it works) show delay components Precharge Time 8
CLK 10 4 2 10 4 out 2 10 4 2 (b) Does it work? Reason it doesn t work? (if it does not) Evaluate Delay (if it works) show delay components Precharge Time 9
. (10 points) An embedded hardware accelerator in a system-on-chip is designed in a 90 nm process with a V dd of 1 V. The circuit has 1 million logic transistors with an average width of 12λ. The transistor gate capacitance is Cg = 2fF/µm and the gates have an activity factor of 0.2. (a) What is the maximum clock frequency if the dynamic power should not exceed 20 mw? (b) If the subthreshold leakage is 20nA/µm and half the transistors are off (on average), what is the leakage power? 10
4. (20 points) The figure below shows a 2T-DRAM cell to be used in a low-voltage application. The supply voltage is fixed at 1 V. W BL is the write bit-line, RBL is the read bit-line. Assume initially that node P is driven to GND. (a) Determine the signal levels (V DD or GND) that have to be applied to the control signals (W S, RS) to perform a write operation into and a read operation from the cell? (b) Explain what problem this has in storing data. Hint: Think about when writing a 1. 11
(c) Instead of node P being fixed at GND, we apply a waveform as shown in figure below. Fill in the timing diagrams for the write operation. Denote the voltage levels in terms of V DD and V T, the threshold voltage of an NMOS device. Assume there is enough time to let the transient effects settle out (no need to draw them). Explain why this approach is better. (d) Does the memory cell require refresh? Why or why not? 12
5. (20 pts) Short Answer Questions: Answer the questions briefly. Include diagrams and equations as needed. Be clear in your explanation and handwriting. A Draw the IV relationships between drain current and the drain-to-source voltage and gate-to-source voltage (I d vs. V GS and I d vs. V DS ) Label all relevant features. B What is velocity saturation and under what conditions does it occur in a MOSFET device? C How does reducing the threshold voltage of a device impact delay and energy? 1
D How can you test if your design will meet your speed spec with variations in design parameters? E Describe two undesired effects cause from having long wires in your design. 14