Practice 7: CMOS Capacitance Digital Electronic Circuits Semester A 2012
MOSFET Capacitances
MOSFET Capacitance Components 3
Gate to Channel Capacitance In general, the gate capacitance is similar to a parallel plate capacitor: A Cg Cox W L t ox However, what is the other terminal of the gate capacitance? This is dependent on the existence and characteristics of the channel. But we have to attribute the capacitance to one of the electrical terminals (i.e. G, S, D, B) of the transistor. 4
Gate to Channel Capacitance In cut-off, no channel exists. All capacitance is to the body: CGB Cg Cox W L C GS C GD In linear, the channel extends across the entire length. There is no capacitance to body. 0 We attribute half of the gate capacitance to the source and half to the drain. CGB 0 1 1 CGS CGD Cg CoxWL 2 2 5
Gate to Channel Capacitance In saturation, the channel ends before the drain. There is no capacitance to the drain! There is still no capacitance to the body. The total capacitance is smaller than the full value. C 0 C 0 GD GB 2 2 CGS Cg Cox W L 3 3 Velocity saturation does not affect the channel. Capacitance components should be calculated according to long channel approximations! 6
Overlap Capacitances Overlap capacitances exist independently of the channel. The length of the overlap is deterministic, therefore: C C W L C W GD, overlap ox D, overlap D, overlap We will assume that the source and drain are equivalent. In actuality, this is layout dependent. C C C D, overlap S, overlap ov 7
Diffusion Capacitance Diffusion capacitance is made up of the reverse-bias capacitance of the source and drain diodes. This capacitance is voltage dependent and is proportional to the junction area of the diode. Cbottom C j W Ldiff C C W 2L sidewalls sw diff CDB CSB Cbottom Csidewalls We will usually give you this as a pre-calculated capacitance. 8
MOSFET Capacitances - Summary Component Cut-off Linear Saturation C GB C ox WL 0 0 C GS C ov W 0.5C ox WL + C ov W 2/3C ox WL + C ov W C GD C ov W 0.5C ox WL + C ov W C ov W C DS, C DB C diff C diff C diff 9
CMOS Inverter Capacitances
Delay Capacitance Assumptions We would like to estimate the capacitance of a CMOS stage for propagation delay calculation (t pd =0.69RC) We only care about the relevant capacitance during the 50% transition! To make things easier, we will assume all capacitances are to Ground and lump them together: Driver Load C wire C C C C out out, driver wire in, load C out,1 C in,2 C int C ext C int C ext 11
Input and Output Capacitances Input Capacitances for CMOS gates are the Gate capacitances: C GB C GS C GD Output Capacitances for CMOS gates are the drain capacitances: C DB C GD V in G C GSP C GDP C GDN G C GSN B C GBN S C GBP D D B S C SBP C DBP V out C DBN C SBN 12
Driver Capacitance We will start by looking at the Output Capacitance of the Driver: C DBn is between Vout and ground. Without losing too much accuracy, we will assume that C DBp is to ground. But we have another component of the output capacitance: The feedthrough capacitance from Vin to Vout (C GDp and C GDn ). These are mainly overlap capacitances! But what is their size? V in G C GDP C GSP C GDN G C GSN B C GBN S C GBP D D B S C SBP C DBP V out C DBN C SBN C 13 out, driver Cint DBn C DBp C C C GDp GDn
Driver Capacitance We need to consider the Miller Effect: C GSP S V in G C GDP C GDN B C GBP D D C SBP C DBP V out C DBN So we get 2C GD,overlap G C GSN C GBN B S C SBN C 14 out, driver Cint DBn C DBp C C C 2CovWGDp n 2CGDn ovwp
Load Input Capacitance We look at all the capacitances connected to the gates of the load: C GSn and C GBn are between Vout and ground. Without losing much accuracy, we will assume C GSp and C GBp are to ground. Since we change from 0 to V DD /2, most of the time one transistor is cut-off, while the other is linear. So we can say that C G =C ox WL and not separate C GB, C GS and C GD. V in G C GDP C GSP C GDN G C GSN B C GBN S C GBP D D B S C SBP C DBP V out C DBN C SBN 15 C W L C oxw GSp p LCp GBp Cin, load C GSn ox n Cn GBn
Load Input Capacitance But what about Miller? Remember, this is a non-accurate approximation! There is very little Miller effect on the second stage because it hasn t started to switch. Considering that L=L eff +2L ov, we will usually just use C in =C ox WL. V in G C GDP C GSP C GDN B S C GBP D D C SBP C DBP V out G C GSN C GBN B S C DBN C SBN 16 Cin, load CoxWn Ln CoxWp Lp
CMOS Capacitances - Summary Driver Load C wire C out,1 C in,2 C int C ext C C Cout Cout, driver Cwire Cin, load int ext C C C C C W C W 2, out driver int DBn DBp ov n ov p C C FO C ext wire in, load C C W L C W L in, load ox n n ox p p 17
Examples
Exercise 1 Find the output capacitance of an inverter driving 4 identical inverters with: C C C C 2 0.31fF μm ; 6 ff μm ; 1.5fF; 1.15fF ov ox DBp DBn W L 0.375 0.25 ; W L 1.125 0.25 ; C 0.5 ff n n p p wire 19
Exercise 1 We ll just use the estimations we developed: C, C C 2C W 2C W out driver DBn DBp ov n ov p 1.5 ff 1.15 ff 2 0.31 0.375 ff 2 0.31 1.125 ff 3.58 ff C C W L C W L in,load ox n n ox p p 6 0.375 0.25 6 1.125 0.25 ff 2.25 ff C C C 4 C 3.58 0.5 9 13.08 ff out out, driver wire in, load 20
Exercise 1 Now find the total power consumption of the circuit operating at a frequency of 1GHz with a 2.5V supply. 1 2 C C stage C stage switch out out C 4 C out out, driver 13.08 ff 4 3.58 ff 27.4 ff P f C V 2 dyn switch DD 2 1GHz 27.4 ff 2.5V 171.25 W Pstatic 0 21
Exercise 2: Moed B 2010 22
Exercise 2: Moed B 2010 N1 N2 N1 cut-off N2 - linear 23
Exercise 2: Moed B 2010 V GN1 =V GN2 =V DD /2=0.9V N1, N2 - linear N1 N2 24