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Transcription:

Silicon P-Channel MOS FET November 1996 Application High speed power switching Features Low on-resistance High speed switching Low drive current 4 V gate drive device can be driven from V source Suitable for switching regulator, DC-DC converter Outline DPAK-2 4 4 1 2 3 1 2 3 D G 1. Gate 2. Drain 3. Source 4. Drain S

Absolute Maximum Ratings (Ta = 2 C) Item Symbol Ratings Unit Drain to source voltage V DSS V Gate to source voltage V GSS ±20 V Drain current I D A Drain peak current I D(pulse) * 1 40 A Body to drain diode reverse drain current I DR A Channel dissipation Pch* 2 20 W Channel temperature Tch C Storage temperature Tstg to + C Notes 1. PW µs, duty cycle 1% 2. Value at T C = 2 C 2

Electrical Characteristics (Ta = 2 C) Item Symbol Min Typ Max Unit Test conditions Drain to source breakdown V (BR)DSS V I D = ma, V GS voltage Gate to source breakdown voltage V (BR)GSS ±20 V I G = ±0 µa, V DS Gate to source leak current I GSS ± µa V GS = ±16 V, V DS Zero gate voltage drain current I DSS 0 µa V DS = 16 V, V GS Gate to source cutoff voltage V GS(off) 1.0 2. V I D = 1 ma, V DS = Static drain to source on state R DS(on) 0.0 0.08 Ω I D = A, V GS = * 1 resistance 0.09 0.14 Ω I D = A, V GS = 4 V* 1 Forward transfer admittance y fs 6 9 S I D = A, V DS = * 1 Input capacitance Ciss 730 pf V DS =, V GS, f = 1 MHz Output capacitance Coss 680 pf Reverse transfer capacitance Crss 260 pf Turn-on delay time t d(on) 13 ns I D = A, V GS =, R L = 2 Ω Rise time t r 1 ns Turn-off delay time t d(off) 90 ns Fall time t f 1 ns Body to drain diode forward voltage Body to drain diode reverse recovery time Note 1. Pulse test V DF 1.2 V I F = A, V GS t rr 0 µs I F = A, V GS, di F /dt A/µs 3

20 Power vs. Temperature Derating Channel Dissipation Pch (W) 1 0 30 3 0 1 0 0 200 Case Temperature Tc ( C) Maximum Safe Operation Area Operation in This Area is Limited by R DS(on) µs D.C Operation (Tc = 2 C) 0 µs 1 ms 0.3 PW = ms Ta = 2 C (1shot) 0.1 0.1 0.3 1 3 30 0 Drain to Source Voltage V DS (V) 16 12 8 4 Typical Output Characteristics 6 V 4 V 3. V 3 V V GS = 2. V 0 2 4 6 8 Drain to Source Voltage V (V) DS 4

Typical Tranfer Characteristics 16 12 8 4 V DS = 7 C Tc = 2 C 2 C Drain to Source Voltage V DS(on) (V) Drain to Source On State Resistance R DS(on) ( Ω ) 1.0 0.8 0.6 0.4 0.2 0 1 2 3 4 Gate to Source Voltage V (V) GS Drain to Source Saturation Voltage vs. Gate to Source Voltage I D = A A 2 A 0 2 4 6 8 Gate to Source Voltage V (V) GS 0. 0.2 0.1 0.0 0.02 Static Drain to Source on State Resistance vs. Drain Current 1 V GS = 4 V 0.01 0. 1 2 0

Static Drain to Source on State Resistance R DS(on) ( Ω ) Forward Transfer Admittance y fs (S) Static Drain to Source on State Resistance vs. Temperature 0.20 0.16 0.12 0.08 0.04 V GS = 4 V V GS = I D = A A A 2 A A 2 A 0 40 0 40 80 120 160 Case Temperature Tc ( C) 0 20 2 Forward Transfer Admittance vs. Drain Current Tc = 2 C 2 C 7 C 1 V DS = 0. 0.2 0. 1 2 00 Body Drain Diode Reverse Recovery Time Reverse Recovery Time trr (ns) 200 0 0 20 di / dt = 20 A / µs V GS, 0.1 0.2 0. 1.0 2 Reverse Drain Current I DR (A) 6

000 Typical Capacitance vs. Drain to Source Voltage Capacitance C (pf) 00 0 Ciss Coss Crss Drain to Source Voltage V DS (V) V GS f = 1 MHz 0 4 8 12 16 0 30 Drain to Source Voltage V DS (V) Dynamic Input Characteristics V DS V DD = V V V DD = V V V GS 40 I D = A 0 0 8 16 24 32 40 Gate Charge Qg (nc) 0 4 8 12 16 Gate to Source Voltage V GS (V) Switching Time t (ns) 00 200 0 0 20 t f t d(off) Switching Characteristics V GS =, V DD = PW = 2 µs, duty < 1 % t r t d(on) 0.1 0.2 0. 1 2 7

Reverse Drain Current I DR (A) 16 12 8 4 Reverse Drain Current vs. Source to Drain Voltage V V GS, V 0 0.4 0.8 1.2 1.6 Source to Drain Voltage V SD (V) 3 Normalized Transient Thermal Impedance vs. Pulse Width Normalized Transient Thermal Impedance γ s (t) 1 0.3 0.1 0.03 D = 1 0. 0.2 0.01 0.1 0.0 0.02 1 shot Pulse 0.01 µ 0 µ 1 m m Pulse Width θ ch c(t) = γ s (t) θ ch c θch c = 6.2 C/W, Tc = 2 C PDM PW T Tc = 2 C D = PW T 0 m 1 PW (S) Switching Time Test Circuit Waveforms Vin Monitor D.U.T. R L Vout Monitor Vin % 90% Vin - V 0Ω VDD. =. V 90% 90% Vout % % td(on) tr td(off) t f 8

When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein.. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. 9