ECEN60: Network Theory Broadband Circuit Deign Fall 08 Lecture 6: Loop Filter Circuit Sam Palermo Analog & Mixed-Signal Center Texa A&M Univerity
Announcement HW i due Oct Require tranitor-level deign For 90nm CMOS device model, ee http://www.ece.tamu.edu/~palermo/ecen689/cadence_90nm.pdf Can ue other technology model if they are a 30nm or more advanced CMOS node
Agenda Loop filter circuit Voltage-mode filter Charge-Pump PLL PI filter Filter with capacitive multiplier Split Proportional & Integral Path Filter Pattern Jitter Sample-Reet Loop Filter Some loop filter paper are poted on the webite 3
PLL Block Diagram [Perrott] The lowpa loop filter extract the average of the phae detector error pule in order to produce the VCO control voltage 4
Paive Lag-Lead Filter [Allen] F R C R C Dimenionle voltage-mode filter ued in Type- PLL Called lag-lead becaue the pole i at a lower frequency than the zero Ideally, the paive filter diplay no nonlinearity 5
Active Lag-Lead Filter [Allen] F a R C Dimenionle voltage-mode filter ued in Type- PLL Active filter allow for potential gain in the loop filter Opamp noie and linearity can impact PLL performance R C a C C 6
Active Proportional-Integral (PI) Filter [Allen] F R C R C Dimenionle voltage-mode filter ued in Type- PLL Opamp noie and linearity can impact PLL performance Opamp open loop gain limit the low-frequency gain and ideal tranfer function 7
Cloed-Loop Tranfer Function 8 Negative Feedback) (Auming Overall Filter Active PI Negative Feedback) (Auming Overall Active Lag - Lead Filter Paive Lag - Lead Filter n VCO PD n VCO PD VCO PD VCO PD VCO a PD n VCO a PD n VCO a PD VCO a PD VCO a PD a VCO PD n VCO PD n VCO PD VCO PD VCO PD N N N H F N N N N H F N N N N H F
Charge Pump PLL Paive PI Loop Filter Single-Ended Fully Differential Simple paive filter i mot commonly ued Integrate low-frequency phae error onto C to et average frequency Reitor (proportional gain) iolate phae correction from frequency correction Primary capacitor C affect PLL bandwidth Zero frequency affect PLL tability Reitor add thermal noie which i band-pa filtered by PLL 9
Loop Filter Tranfer Function Neglecting econdary capacitor, C 0
Loop Filter Tranfer Function With econdary capacitor, C
Why have C? Secondary capacitor moothe control voltage ripple Can t make too big or loop will go untable C < C /0 for tability C > C /50 for low jitter Control Voltage Ripple
Loop Filter Reitor Poly, diffuion, and N-well reitor are commonly ued MOSFET reitor can be ued if the reitor i placed below the C cap Thi enure a contant V GS voltage on the tranitor Programmable R value poible with witche Switche hould be CMOS tranmiion gate to minimize paraitic witch reitance variation with control voltage level Good practice i to make Rwitch <0% of the main filter R to minimize the impact of witch reitatnce variation [Fichette] 3
R or C on Top? Ideally, the loop filter ha the ame tranfer function and tranient repone independent of the RC order In reality, the bottom-plate capacitance and witch reitance variation will impact thi ideal tranfer function If the cap i on top, the bottom-plate capacitance will introduce another high frequency pole If the reitor i on top, any witch reitance will have increaed variation with the control voltage level [Fichette] 4
Loop Filter Capacitor To minimize area, we would like to ue highet denity cap Thin oxide MOS cap gate leakage can be an iue Similar to adding a non-linear parallel reitor to the capacitor Leakage i voltage and temperature dependent Will reult in exce phae noie and pur Metal cap or thick oxide cap are a better choice Trade-off i area Metal cap denity can be </0 thin oxide cap Filter cap frequency repone can be relatively low, a PLL loop bandwidth are typically -50MHz 5
Third-Order Loop Filter I CP R3 k V ctrl [Shu JSSC 003] R 0k C 60p C C 3 0p 0p The 60pF capacitance in TSMC 0.35um CMOS take about 0.mm^. To reduce it area, it i implemented via a 0pF capacitor caled up by a factor of 6. 6
Capacitor Multiplier M V BP i in :5 v in C i 0p B :5 A C p C p V BN I bia M Current ratio M=5 Capacitance 6 7
Capacitor Multiplier Tranfer Function M Looking at the impedance, we get pole and a zero c and c3 are pole, c i a zero i in :5 V BP Low freq. pole (ideally at 0) v in C i 0p B :5 A C p V BN High freq. zero (ideally at ) C p I bia M High freq. pole (ideally at ) Current ratio M=5 Capacitance 6 Original Filter 8
Capacitance Multiplier Impedance Magnitude Phae (dominant pole) (high frequency zero) (high frequency pole) 9
Loop Filter Sim. w/ Capacitance Multiplier (a) magnitude (b) phae It how that with capacitance caling the large capacitor in the loop filter can be eaily integrated on chip within mall area Thi approach i imple and the leakage i very mall 0
Loop Filter Tranfer Function Neglecting econdary capacitor, C R C Proportional term Integral term
Split Proportional & Integral Gain Path Proportional and integral gain path can be plit by utilizing independent charge pump driving the integral capacitor and the proportional effective reitor Often, the proportional and integral voltage are ummed with a voltage-to-current converter to control a currentcontrolled ocillator (ICO) Allow for elf-biaed PLL architecture whoe normalized loop bandwidth and damping factor remain contant over different output frequencie We will look at thee PLL architecture in more detail later
Control Voltage Ripple After phae locking, diturbance at a time interval equal to the reference clock period caue time-domain period jitter and frequency-domain reference clock pur Caued by charge pump current imbalance, loop filter leakage, and reference clock jitter 3
Pattern Jitter A dominant form of pattern jitter i due to the proportional gain term, I CP *R Every time the reference clock goe high, charge pump mimatch current dropped on the filter reitor caue control voltage ripple Thi reult in horter (or longer) output cycle that occur at a time interval equal to the reference clock period 4
Pattern Jitter w/ Secondary Capacitor Adding a econdary loop filter capacitor introduce extra filtering, which reduce the control voltage diturbance amplitude, but extend it over many cycle Make an ideal econd-order PLL into a third-order ytem Stability limit the ize of C Can we get thi ame effect without compromiing tability? 5
PLL w/ Sample-Reet Loop Filter Ideal Operation A PLL with a tandard RC filter produce a voltage pike equal to I CP *R for a duration equal to the phae error A ample-reet loop filter replace the reitor with a capacitor that i charged during the phae error and reet every reference cycle Thi pread the correction voltage nearly uniformly over the entire reference period and reduce the correction voltage peak value Thi eliminate the need for additional filtering with a econdary capacitor, providing the opportunity for near 90 phae margin 6
Sample-Reet Loop Filter w/ Single Capacitor A ingle-capacitor implementation till ha a (reduced) ripple component due to the ample, hold, and reet operation Alo, a very hort reet pule need to be generated, which may be difficult to realize with the control logic 7
Sample-Reet Loop Filter w/ Double Capacitor With a double-capacitor implementation, the remaining ripple i dramatically reduced While one capacitor i being reet and then having the phae error ampled, the other capacitor which hold the previou ampled proportional voltage i attached to the gm output tage 8
Sample-Reet PLL PFD & Filter Switch Signal Generation The PFD reet ignal i divided by to produce the even and odd witch control ignal During reet, the charge pump houldn t be conducting and the filter capacitor can be applied to the main loop 9
Sample-Reet PLL Small-Signal Model 30 i ico mi i cp mp update ico p cp mi mp update p i i cp p cp ico i mi i cp p mp update p cp i mi i cp prop lpf p mp update prop i mi MC g I g T I g g T C C I I C g I H C g T I C g I I I I C g T C g : ICO Current Total Path : Proportional Path : Integral _ int int p mp update p cp mi i cp i ico z n mp update mi i p p cp i cp z i ico mi i cp n C g T I g MI C g T g C C I I MC g I _
ICO Control Waveform Standard Charge Pump PLL PLL w/ Sample-Reet Filter PLL w/ ample-reet filter ha dramatically reduced ripple voltage on ocillator control ignal The control ignal diplay an almot ideal tairtep repone 3
Next Time VCO 3