- Spring 2003 Lecture 8 Power Inverter Chain Announcements Homework 3 due today. Homework 4 will be posted later today. Special office hours from :30-3pm at BWRC (in lieu of Tuesday)
Today s lecture Power consumption Inverter chain sizing Power Dissipation 2
Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors Dynamic Power Dissipation Vdd Vin Vout C L Energy/transition = C L *V dd 2 Power = Energy/transition *f=c L *V dd 2 *f Not a function of transistor sizes! Need to reduce C L,V dd,andf to reduce power. 3
Node Transition Activity and Power Consider switching a CMOS gate for N clock cycles E N = C L V 2 dd nn ( ) E N : the energy consumed for N clock cycles n(n):thenumberof0->transitioninn clock cycles P avg = lim N E N ------- f N clk = nn ( ) lim ------------ 2 C V N N dd fclk L α 0 = nn ( ) lim ------------ N N P avg = α 0 C L V 2 dd fclk Short Circuit Currents Vdd Vin Vout C L 0.5 IVDD (ma) 0.0 0.05 0.0.0 2.0 3.0 V in (V) 4.0 5.0 4
How to keep Short-Circuit Currents Down? Short circuit current goes to zero if t fall >> t rise, but can t do this for cascade logic, so... Minimizing Short-Circuit Power 8 7 6 Vdd =3.3 P norm 5 4 Vdd =2.5 3 2 Vdd =.5 0 0 2 3 4 5 t /t sin sout 5
Leakage Vdd Vout Drain Junction Leakage Sub-Threshold Current Sub-threshold current one of most compelling issues in low-energy circuit design! Reverse-Biased Diode Leakage GATE p + p+ N Reverse Leakage Current + - V dd I DL = J S A JS = 0-00 pa/µm2 at 25 deg C for 0.25µmCMOS JS doubles for every 9 deg C! 6
Subthreshold Leakage Component Static Power Consumption Vdd I stat V out V in =5V C L P stat = P (In=).V dd. I stat Wastedenergy Should be avoided in most cases, but could help reducing energy in others (e.g. sense amps) 7
Principles for Power Reduction Prime choice: Reduce voltage!» Recent years have seen an acceleration in supply voltage reduction» Design at very low voltages still open question (0.6 0.9 V by 200!) Reduce switching activity Reduce physical capacitance Sizing of an Inverter Chain 8
Inverter Chain In Out C L If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. Inverter Delay Minimum length devices, L=0.25µm Assume that for W P =2W N =2W same pull-up and pull-down currents approx. equal resistances R N = R P approx. equal rise t plh and fall t phl delays Analyze as an RC network WP WN R P = Runit Runit = RN = RW W unit W unit 2W W Delay (D): t phl =(ln2)r N C L t plh =(ln2)r P C L W Load for the next stage: Cgin = 3 Cunit W unit 9
Inverter with Load Delay R W C L R W Load (C L ) t p = kr W C L k is a constant, equal to 0.69 Assumptions: no load -> zero delay W unit = Inverter with Load C P =2C unit 2W Delay W C int C L C N = C unit Load Delay = kr W (C int + C L )=kr W C int + kr W C L =kr W C int (+ C L /C int ) = Delay (Internal) + Delay (Load) 0
Delay Formula Delay ~ R W ( C + C ) int L t p = kr W C int ( + C / C ) = t ( + f / γ ) L int p 0 C int = γc gin with γ f = C L /C gin - effective fanout R=R unit /W ; C int =WC unit t p0 =0.69R unit C unit Apply to Inverter Chain In Out 2 N C L t p = t p + t p2 + +t pn C gin, j+ t + pj ~ RunitCunit γc gin, j N N C gin j t p = t p j = t p +, +, 0, Cgin N = C j i C, + = = γ gin, j L
Optimal Tapering for Given N Delay equation has N - unknowns, C gin,2 C gin,n Minimize the delay, find N - partial derivatives Result: C gin,j+ /C gin,j = C gin,j /C gin,j- Size of each stage is the geometric mean of two neighbors C gin, j = Cgin, j C gin, j+ - each stage has the same effective fanout (C out /C in ) - each stage has the same delay Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: N f = F = C Effective fanout of each stage: L / Cgin, Minimum path delay p f = N F t = Nt + p0 N ( F /γ ) 2
Example In C f f 2 Out C L =8C C L /C has to be evenly distributed across N = 3 stages: f = 3 8 = 2 Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f t p N ln F CL = F Cin = f Cin with N = ln f t ln F = Nt p0 γ ln f t p t p0 ln F ln f γ f = = 0 2 f γ ln f / N p0 f γ ( F / γ + ) = + For γ =0,f =e,n =lnf f ln f = exp + ( γ f ) 3
Optimum Effective Fanout f Optimum f for given process defined by γ 5 4.5 f = exp + ( γ f ) f opt =3.6 for γ= 4 f opt 3.5 3 2.5 0 0.5.5 2 2.5 3 γ Impact of Loading on tp 7 With Self-Loading γ= 6 5 normalized delay 4 3 2 0.5 2 2.5 3 3.5 4 4.5 5 f 4
Normalized delay function of F t = Nt + p p0 N ( F /γ ) Buffer Design N f t p 64 64 65 8 64 2 8 8 4 6 64 3 4 5 2.8 8 22.6 64 4 2.8 5.3 5
What about power consumption (and area)? Delay versus Area and Power 6