OptiMOS -P2 Power-Transistor Product Summary V DS -4 V R DS(on) (SMD Version) 3.1 mw Features P-channel - Logic Level - Enhancement mode I D -12 A AEC qualified PG-TO263-3-2 PG-TO262-3-1 PG-TO22-3-1 MSL1 up to 26 C peak reflow 175 C operating temperature Green package (RoHS compliant) 1% Avalanche tested Type Package Marking IPB12P4P4L-3 PG-TO263-3-2 4PP4L3 IPI12P4P4L-3 PG-TO262-3-1 4PP4L3 IPP12P4P4L-3 PG-TO22-3-1 4PP4L3 Maximum ratings, at T j =25 C, unless otherwise specified Parameter Symbol Conditions Value Unit Continuous drain current 1) I D T C =25 C, V GS =-1V -12 A T C =1 C, V GS =-1V 2) -114 Pulsed drain current 2) I D,pulse T C =25 C -48 Avalanche energy, single pulse E AS I D =-6A 78 mj Avalanche current, single pulse I AS - -12 A Gate source voltage V GS - ±16 3) V Power dissipation P tot T C =25 C 136 W Operating and storage temperature T j, T stg - -55... +175 C IEC climatic category; DIN IEC 68-1 - - 55/175/56 Rev. 1.1 page 1 215-5-27
Parameter Symbol Conditions Values Unit min. typ. max. Thermal characteristics 2) Thermal resistance, junction - case R thjc - - - 1.1 K/W Thermal resistance, junction - ambient, leaded R thja - - - 62 SMD version, device on PCB R thja minimal footprint - - 62 6 cm 2 cooling area 4) - - 4 Electrical characteristics, at T j =25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS =V, I D = -1mA -4 - - V Gate threshold voltage V GS(th) V DS =V GS, I D =-34µA -1.2-1.7-2.2 Zero gate voltage drain current I DSS V DS =-32V, V GS =V, T j =25 C - -.5-1 µa V DS =-32V, V GS =V, T j =125 C 2) - -2-2 Gate-source leakage current I GSS V GS =-16V, V DS =V - - -1 na Drain-source on-state resistance R DS(on) V GS =-4.5V, I D =-1A - 4. 5.2 mw V GS =-4.5V, I D =-1A, SMD version - 3.7 4.9 V GS =-1V, I D =-1A - 2.9 3.4 V GS =-1V, I D =-1A, SMD version - 2.6 3.1 Rev. 1.1 page 2 215-5-27
Parameter Symbol Conditions Values Unit min. typ. max. Dynamic characteristics 2) Input capacitance C iss - 1138 15 pf Output capacitance C oss V GS =V, V DS =-25V, f =1MHz - 341 5 Reverse transfer capacitance C rss - 135 27 Turn-on delay time t d(on) - 21 - ns Rise time t r V DD =-2V, V GS =-1V, I D =-12A, - 16 - Turn-off delay time t d(off) R G =3.5W - 85 - Fall time t f - 57 - Gate Charge Characteristics 2) Gate to source charge Q gs - 4 52 nc Gate to drain charge Q gd V DD =-32V, I D =-12A, - 32 64 Gate charge total Q g V GS = to -1V - 18 234 Gate plateau voltage V plateau - 3.5 - V Reverse Diode Diode continous forward current 2) I S T C =25 C - - -12 A Diode pulse current 2) I S,pulse - - -48 Diode forward voltage V SD V GS =V, I F =-1A, T j =25 C - -1-1.3 V Reverse recovery time 2) t rr V R =-2V, I F =-5A, - 54 ns Reverse recovery charge 2) Q rr di F /dt =-1A/µs - 6 nc 1) Current is limited by bondwire; with an R thjc = 1.1K/W the chip is able to carry -171A at 25 C. 2) Defined by design. Not subject to production test. 3) V GS =+5V/-16V according AEC; V GS =+16V for max 168h at T J =175 C 4) Device on 4 mm x 4 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 7 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.1 page 3 215-5-27
1 Power dissipation 2 Drain current IPB12P4P4L-3 P tot = f(t C ); V GS -6V I D = f(t C ); V GS -6V; SMD 16 14 14 12 12 1 1 P tot [W] 8 6 8 6 4 4 2 2 5 1 15 2 5 1 15 2 T C [ C] T C [ C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(v DS ); T C = 25 C; D = ; SMD Z thjc = f(t p ) parameter: t p parameter: D =t p /T 1 1 1 1 µs 1 µs 1 1 ms 1 µs 1.5 Z thjc [K/W] 1-1.1.5 1 1-2.1 single pulse 1.1 1 1 1 -V DS [V] 1-3 1-6 1-5 1-4 1-3 1-2 1-1 1 t p [s] Rev. 1.1 page 4 215-5-27
5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(v DS ); T j = 25 C; SMD parameter: V GS R DS(on) = (I D ); T j = 25 C; SMD parameter: V GS 64 56-1 V -5 V 2 18-2.8 V -3 V -3.5 V 48 16 4-4.5 V 14 32 24-4 V R DS(on) [mw] 12 1 8 16-3.5 V 6 8-3 V 1 2 3 4 5 6 4 2-4 V -4.5 V -5 V -1V 4 8 12 -V DS [V] 7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance I D = f(v GS ); V DS = -6V R DS(on) = f(t j ); I D = -1 A; V GS = -1 V; SMD parameter: T j 64 25 C 4.5 56-55 C 48 175 C 4 32 R DS(on) [mw] 3.5 24 2.5 16 8 2 3 4 5 -V GS [V] 1.5-6 -2 2 6 1 14 18 T j [ C] Rev. 1.1 page 5 215-5-27
9 Typ. gate threshold voltage 1 Typ. capacitances IPB12P4P4L-3 V GS(th) = f(t j ); V GS = V DS C = f(v DS ); V GS = V; f = 1 MHz parameter: I D 2.5 1 5 2 1 4 Ciss -34µA Coss -V GS(th) [V] 1.5-34µA C [pf] 1 3 1 1 2 Crss.5-6 -2 2 6 1 14 18 T j [ C] 1 1 5 1 15 2 25 3 -V DS [V] 11 Typical forward diode characteristicis 12 Drain-source breakdown voltage IF = f(v SD ) V BR(DSS) = f(t j ); I D = -1 ma parameter: T j 1 3 45 44 43 1 2 42 -I F [A] 175 C 25 C -V BR(DSS) [V] 41 4 39 1 1 38 37 36 1.2.4.6.8 1 1.2 1.4 -V SD [V] 35-6 -2 2 6 1 14 18 T j [ C] Rev. 1.1 page 6 215-5-27
13 Typ. gate charge 14 Gate charge waveforms V GS = f(q gate ); I D = -12 A pulsed parameter: V DD 12 1 V GS Q g 8-8V -32V -V GS [V] 6 4 2 Q gate 2 4 6 8 1 12 14 16 Q gs Q gd Q gate [nc] Rev. 1.1 page 7 215-5-27
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Revision History Version Date Changes 1. 1.1 211-1-24 Final Data Sheet 215-5-27 Update of marking Rev. 1.1 page 9 215-5-27