BF904A; BF904AR; BF904AWR

Similar documents
Silicon N-channel dual gate MOS-FET IMPORTANT NOTICE. use

DATA SHEET. BF1201; BF1201R; BF1201WR N-channel dual-gate PoLo MOS-FETs DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Dec 01

DATA SHEET. BF1202; BF1202R; BF1202WR N-channel dual-gate PoLo MOS-FETs DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2000 Mar 29

DISCRETE SEMICONDUCTORS DATA SHEET. BF1212; BF1212R; BF1212WR N-channel dual-gate MOS-FETs. Product specification 2003 Nov 14

N-channel enhancement mode Field-Effect Transistor (FET) in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package using

N-channel TrenchMOS standard level FET. High noise immunity due to high gate threshold voltage

PHD/PHP36N03LT. 1. Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 General description. 1.

74AHC1G00; 74AHCT1G00

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

PSMN006-20K. N-channel TrenchMOS SiliconMAX ultra low level FET

60 V, 0.3 A N-channel Trench MOSFET

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

N-channel TrenchMOS logic level FET

DATA SHEET. BF1203 Dual N-channel dual gate MOS-FET DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2000 Dec 04.

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

N-channel TrenchMOS standard level FET. Higher operating power due to low thermal resistance Low conduction losses due to low on-state resistance

N-channel TrenchMOS logic level FET

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

2-input EXCLUSIVE-OR gate

PHB108NQ03LT. N-channel TrenchMOS logic level FET

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

BUK9Y53-100B. N-channel TrenchMOS logic level FET. Table 1. Pinning Pin Description Simplified outline Symbol 1, 2, 3 source (S) 4 gate (G)

N-channel TrenchMOS standard level FET. Higher operating power due to low thermal resistance Low conduction losses due to low on-state resistance

PHP110NQ08T. N-channel TrenchMOS standard level FET

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

N-channel 30 V 1.3 mω logic level MOSFET in LFPAK

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

N-channel TrenchMOS ultra low level FET. Higher operating power due to low thermal resistance Interfaces directly with low voltage gate drivers

BCM857BV; BCM857BS; BCM857DS

PSMN B. N-channel TrenchMOS SiliconMAX standard level FET. High frequency computer motherboard DC-to-DC convertors

Passivated ultra sensitive gate thyristor in a SOT54 plastic package. Earth leakage circuit breakers or Ground Fault Circuit Interrupters (GFCI)

PSMN004-60B. N-channel TrenchMOS SiliconMAX standard level FET. High frequency computer motherboard DC-to-DC convertors

PSMN005-75B. N-channel TrenchMOS SiliconMAX standard level FET. High frequency computer motherboard DC-to-DC convertors

DATA SHEET. BC817DPN NPN/PNP general purpose transistor DISCRETE SEMICONDUCTORS. Product data sheet Supersedes data of 2002 Aug 09.

Dual rugged ultrafast rectifier diode, 20 A, 150 V. Ultrafast dual epitaxial rectifier diode in a SOT78 (TO-220AB) plastic package.

NPN/PNP transistor pair connected as push-pull driver in a SOT457 (SC-74) Surface-Mounted Device (SMD) plastic package.

PSMN4R3-30PL. N-channel 30 V 4.3 mω logic level MOSFET. High efficiency due to low switching and conduction losses

Dual N-channel field-effect transistor. Two N-channel symmetrical junction field-effect transistors in a SOT363 package.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

NPN/PNP low V CEsat Breakthrough in Small Signal (BISS) transistor pair in a SOT457 (SC-74) Surface Mounted Device (SMD) plastic package.

150 V, 2 A NPN high-voltage low V CEsat (BISS) transistor

DATA SHEET. BF908WR N-channel dual-gate MOS-FET. Philips Semiconductors DISCRETE SEMICONDUCTORS Apr 25

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

The 74LV08 provides a quad 2-input AND function.

PSMN4R5-40PS. N-channel 40 V 4.6 mω standard level MOSFET. High efficiency due to low switching and conduction losses

BUK A. N-channel TrenchMOS standard level FET

PSMN013-80YS. N-channel LFPAK 80 V 12.9 mω standard level MOSFET

HEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder

BUK B. N-channel TrenchMOS standard level FET

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

The 74LVC1G11 provides a single 3-input AND gate.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

N-channel TrenchMOS logic level FET

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

PSMN8R3-40YS. N-channel LFPAK 40 V 8.6 mω standard level MOSFET

PSMN2R6-40YS. N-channel LFPAK 40 V 2.8 mω standard level MOSFET

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

The 74LVC1G02 provides the single 2-input NOR function.

65 V, 100 ma NPN/PNP general-purpose transistor. Table 1. Product overview Type number Package NPN/NPN PNP/PNP Nexperia JEITA

The 74LV32 provides a quad 2-input OR function.

N-channel TrenchMOS standard level FET

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74AHC1G14; 74AHCT1G14

BUK B. N-channel TrenchMOS logic level FET

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

2N7002T. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

DATA SHEET. BSS192 P-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 20

BF556A; BF556B; BF556C

PSMN1R3-30YL. N-channel 30 V 1.3 mω logic level MOSFET in LFPAK

IMPORTANT NOTICE. use

BF545A; BF545B; BF545C

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

DISCRETE SEMICONDUCTORS DATA SHEET. ok, halfpage M3D302. PMEM4020ND NPN transistor/schottky-diode module. Product data sheet 2003 Nov 10

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

DATA SHEET. PMEM4010ND NPN transistor/schottky diode module DISCRETE SEMICONDUCTORS. Product data sheet Supersedes data of 2002 Oct 28.

DATA SHEET. BAS40 series Schottky barrier (double) diodes DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr 28.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

2N7002F. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.

DISCRETE SEMICONDUCTORS DATA SHEET. PMMT591A PNP BISS transistor. Product specification Supersedes data of 2001 Jun 11.

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74AHC2G126; 74AHCT2G126

PMV65XP. 1. Product profile. 2. Pinning information. P-channel TrenchMOS extremely low level FET. 1.1 General description. 1.

IMPORTANT NOTICE. use

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

5-stage Johnson decade counter

CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74LV General description. 2. Features. 8-bit addressable latch

DISCRETE SEMICONDUCTORS DATA SHEET M3D071. BAT74 Schottky barrier double diode. Product specification Supersedes data of 1996 Mar 19.

Transcription:

BF9; BF9R; BF9WR Rev. 3 November 27 Product data sheet Dear customer, IMPORTNT NOTICE s from October st, 26 Philips Semiconductors has a new trade name - NXP Semiconductors, which will be used in future data sheets together with new contact details. In data sheets where the previous Philips references remain, please use the new links as shown below. http://www.philips.semiconductors.com use http://www.nxp.com http://www.semiconductors.philips.com use http://www.nxp.com (Internet) sales.addresses@www.semiconductors.philips.com use salesaddresses@nxp.com (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - Koninklijke Philips Electronics N.. (year). ll rights reserved - is replaced with: - NXP B.. (year). ll rights reserved. - If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and understanding, NXP Semiconductors

BF9; BF9R; BF9WR FETURES Specially designed for use at 5 supply voltage Short channel transistor with high transfer admittance to input capacitance ratio Low noise gain controlled amplifier up to GHz Superior cross-modulation performance during GC. PINNING PIN DESCRIPTION source 2 drain 3 gate 2 gate handbook, 2 columns 3 2 Top view MSB BF9 marking code: %M7. PPLICTIONS Fig. Simplified outline (SOT3B). HF and UHF applications with 3 to 7 supply voltage such as television tuners and professional communications equipment. handbook, 2 columns 3 halfpage 3 DESCRIPTION Enhancement type field-effect transistors. The transistors consist of an amplifier MOS-FET with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during GC. The BF9, BF9R and BF9WR are encapsulated in the SOT3B, SOT3R and SOT33R plastic packages respectively. BF9R marking code: %M8. Fig.2 2 Top view MSB35 Simplified outline (SOT3R). BF9WR marking code: MH. Fig.3 2 Top view MSB82 Simplified outline (SOT33R). QUICK REFERENCE DT SYMBOL PRMETER CONDITIONS MIN. TYP. MX. UNIT DS drain-source voltage 7 I D drain current 3 m P tot total power dissipation T s C 2 mw y fs forward transfer admittance 22 25 3 ms C ig-ss input capacitance at gate 2.2 2.6 pf C rss reverse transfer capacitance f = MHz 25 35 ff F noise figure f = 8 MHz 2 db T j operating junction temperature 5 C CUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-68, SNW-FQ-32 and SNW-FQ-32B. Rev. - 3 November 27 2 of 5

BF9; BF9R; BF9WR LIMITING LUES In accordance with the bsolute Maximum Rating System (IEC 3). SYMBOL PRMETER CONDITIONS MIN. MX. UNIT DS drain-source voltage 7 I D drain current 3 m I G gate current ± m I G2 gate 2 current ± m P tot total power dissipation T s C; note ; see Fig. 2 mw T stg storage temperature 65 +5 C T j operating junction temperature 5 C Note. T s is the temperature of the soldering point of the source lead. 25 P tot (mw) 2 MGL65 5 5 5 5 2 T s ( C) Fig. Power derating curve. Rev. - 3 November 27 3 of 5

BF9; BF9R; BF9WR THERML CHRCTERISTICS SYMBOL PRMETER CONDITIONS LUE UNIT R th j-s thermal resistance from junction to soldering point note 2 K/W Note. Soldering point of the source lead. STTIC CHRCTERISTICS T j =25 C unless otherwise specified. SYMBOL PRMETER CONDITIONS MIN. MX. UNIT (BR)G-SS gate -source breakdown voltage G2-S = DS = ; I G-S = m 6 5 (BR)G2-SS gate 2-source breakdown voltage G-S = DS = ; I G2-S = m 6 5 (F)S-G forward source-gate voltage G2-S = DS = ; I S-G = m.5.5 (F)S-G2 forward source-gate 2 voltage G-S = DS = ; I S-G2 = m.5.5 G-S(th) gate -source threshold voltage G2-S =; DS =5; I D =2µ.3 G2-S(th) gate 2-source threshold voltage G-S = DS =5; I D =2µ.3.2 I DSX drain-source current G2-S =; DS =5; R G = 2 kω; note Note. R G connects gate to GG = 5 ; see Fig.2. 8 3 m I G-SS gate cut-off current G2-S = DS = ; G-S =5 5 n I G2-SS gate 2 cut-off current G-S = DS = ; G2-S =5 5 n DYNMIC CHRCTERISTICS Common source; T amb =25 C; DS = 5 ; G2-S = ; I D = m; unless otherwise specified. SYMBOL PRMETER CONDITIONS MIN. TYP. MX. UNIT y fs forward transfer admittance pulsed; T j =25 C 22 25 3 ms C ig-s input capacitance at gate f = MHz 2.2 2.6 pf C ig2-s input capacitance at gate 2 f = MHz.5 2 pf C os drain-source capacitance f = MHz..7 pf C rs reverse transfer capacitance f = MHz 25 35 ff F noise figure f = 2 MHz; G S = 2 ms; B S =B Sopt.5 db f = 8 MHz; G S =G Sopt ; B S =B Sopt 2 2.8 db Rev. - 3 November 27 of 5

BF9; BF9R; BF9WR Y fs (ms) 3 MLD268 handbook, gain halfpage reduction (db) MR769 2 2 3 5 5 5 o T j ( C) 5 2 3 GC () f = 5 MHz. Fig.5 Transfer admittance as a function of the junction temperature; typical values. Fig.6 Typical gain reduction as a function of the GC voltage; see Fig.2. 2 unw (db µ ) MR77 2 I D (m) 5 MLD27 = 3 2.5 G2 S 2.5 9 5 8 2 3 5 gain reduction (db) DS = 5 ; GG = 5 ; f w = 5 MHz. f unw = 6 MHz; T amb =25 C; R G = 2 kω...8.2.6 2. G S () Fig.7 Unwanted voltage for % cross-modulation as a function of gain reduction; typical values; see Fig.2. DS =5. T j =25 C. Fig.8 Transfer characteristics; typical values. Rev. - 3 November 27 5 of 5

BF9; BF9R; BF9WR 2 I D (m) 6 G S =..3 MLD269 5 I G (µ) MLD27 G2 S = 3.5 2.2 3 8...9 5 2.5 2 2 6 8 DS ().5..5 2. 2.5 G S () G2-S =. T j =25 C. Fig.9 Output characteristics; typical values. DS =5. T j =25 C. Fig. Gate current as a function of gate voltage; typical values. y fs (ms) 3 MLD272 G2 S = 3.5 6 I D (m) 2 MLD273 3 2 2.5 8 2 8 2 6 2 I D (m) 2 3 5 I G (µ) DS =5. T j =25 C. DS =5. G2-S =. T j =25 C. Fig. Forward transfer admittance as a function of drain current; typical values. Fig.2 Drain current as a function of gate current; typical values. Rev. - 3 November 27 6 of 5

BF9; BF9R; BF9WR 2 I D (m) 8 MLD275 2 I D (m) 5 R G = 7 kω 68 kω MLD27 82 kω kω 2 kω 5 kω 5 8 kω 22 kω 2 3 5 GG () 2 6 8 GG = DS () DS = 5 ; G2-S = ; T j =25 C. R G = 2 kω (connected to GG ); see Fig.2. Fig.3 Drain current as a function of gate supply voltage (= GG ); typical values. G2-S = ; T j =25 C. R G connected to GG ; see Fig.2. Fig. Drain current as a function of gate (= GG ) and drain supply voltage; typical values. 2 I D (m) 8 MLD276 GG = 5.5 3.5 3 I G (µ) 3 MLB95 GG = 5.5 2 3.5 3 2 6 G2 S () 2 6 G2 S () DS = 5 ; T j =25 C. R G = 2 kω (connected to GG ); see Fig.2. Fig.5 Drain current as a function of gate 2 voltage; typical values. DS = 5 ; T j =25 C. R G = 2 kω (connected to GG ); see Fig.2. Fig.6 Gate current as a function of gate 2 voltage; typical values. Rev. - 3 November 27 7 of 5

BF9; BF9R; BF9WR 2 MLD277 3 MLD278 3 y is (ms) y rs (µs) ϕrs (deg) 2 ϕrs 2 b is y rs g is 2 f (MHz) 3 2 f (MHz) 3 DS = 5 ; G2 =. I D = m; T amb =25 C. DS = 5 ; G2 =. I D = m; T amb =25 C. Fig.7 Input admittance as a function of frequency; typical values. Fig.8 Reverse transfer admittance and phase as a function of frequency; typical values. 2 MLD279 2 MGL6 y fs (ms) y fs ϕ fs (deg) y os (ms) b os ϕ fs g os 2 f (MHz) 3 2 2 f (MHz) 3 DS = 5 ; G2 =. I D = m; T amb =25 C. DS = 5 ; G2 =. I D = m; T amb =25 C. Fig.9 Forward transfer admittance and phase as a function of frequency; typical values. Fig.2 Output admittance as a function of frequency; typical values. Rev. - 3 November 27 8 of 5

BF9; BF9R; BF9WR GC R k Ω C.7 nf C3 2 pf R GEN 5 Ω I R2 5 Ω C2.7 nf R G GG L DUT 5 nh C.7 nf DS R L 5 Ω MLD7 Fig.2 Cross-modulation test set-up. Rev. - 3 November 27 9 of 5

BF9; BF9R; BF9WR Table Scattering parameters: DS = 5 ; G2-S = ; I D = m; T amb =25 C f (MHz) MGNITUDE (ratio) S S 2 S 2 S 22 NGLE (deg) MGNITUDE (ratio) NGLE (deg) MGNITUDE (ratio) NGLE (deg) MGNITUDE (ratio) NGLE (deg).989 3.2 2.52 75.9. 87.9.989.7.987 7.9 2.52 69.. 86..988.3 2.976 5.7 2.7 59.2.3 8..98 8.6 3.972 23.3 2.3 5.5. 8.5.985 2.7.97 3.6 2.36 39.6.5 76.9.975 6.9 5.925 37.6 2.26 3.3.5 75.6.968 2.8 6.95. 2.9 2..5 75.5.96 2.7 7.883 5.9 2. 2.3.6 78..95 28. 8.86 57. 2. 3.6.6 85.3.96 32. 9.8 63..93 95.5.6 9.7.93 35.6.822 68..85 87.8.6 2.6.93 39.3 2.787 78.9.7 72.3.7 27..923 6.7.752 88..59 57.3. 3.7.926 5.2 6.723 97.3.7..9 5..935 62.2 8.685 6.3.36 25..2 9..93 69.3 2.665..3 7.7.26 5.5.93 77.7 22.659 9.8.3..35 58.2.9 89. 2.67 2.2.26 2.2.5 63..9 3.5 26.7 29.3. 78.2.76 62.2.89 9.7 28.729 38.7.82 2.8.6 5.5.62 3.9 3.726 5..52 62.8.28 37..8 3.6 Table 2 Noise data: DS = 5 ; G2-S = ; I D = m; T amb =25 C f (MHz) F min (db) (ratio) Γ opt (deg) 8 2..686 9.6 5. Rn (Ω) Rev. - 3 November 27 of 5

BF9; BF9R; BF9WR PCKGE OUTLINES Plastic surface mounted package; leads SOT3B D B E X y v M H E e b p w M B 3 Q 2 c b Lp e detail X 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm..9 max. b p.8.38 b.88.78 c.5.9 D 3. 2.8 E..2 e.9 e.7 H E 2.5 2. L p.5.5 Q.55.5 v.2 w y.. OUTLINE ERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT3B 97-2-28 Rev. - 3 November 27 of 5

BF9; BF9R; BF9WR Plastic surface mounted package; reverse pinning; leads SOT3R D B E X y v M H E e b p w M B 3 Q 2 c b Lp e detail X 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm..9 max. b p.8.38 b.88.78 c.5.9 D 3. 2.8 E..2 e.9 e.7 H E 2.5 2. L p.55.25 Q.5.25 v.2 w y.. OUTLINE ERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT3R 97-3- Rev. - 3 November 27 2 of 5

BF9; BF9R; BF9WR Plastic surface mounted package; reverse pinning; leads SOT33R D B E X y H E v M e 3 Q 2 c w M B b p b Lp e detail X 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT max mm...8 b p b c D E e e H E Lp Q v w..3.7.5.25. 2.2.8.35.5.3.5 2.2 2..5.5.23.3.2.2 y. OUTLINE ERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT33R 97-5-2 Rev. - 3 November 27 3 of 5

BF9; BF9R; BF9WR Legal information Data sheet status Document status [][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 63) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com Rev. - 3 November 27 of 5

BF9; BF9R; BF9WR Revision history Revision history Document ID Release date Data sheet status Change notice Supersedes BF9_R_WR_N_ 273 Product data sheet - BF9_R_WR_3 Modifications: Fig. and 2 on page 2; Figure note changed BF9_R_WR_3 9995 - BF9_R_WR_N_2 (9397 75 527) BF9_R_WR_N_2 9992 Preliminary specification - BF9_R_WR_N_ (9397 75 523) BF9_R_WR_N_ (9397 75 78) 9983 Preliminary specification - - Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.. 27. ll rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 November 27 Document identifier: BF9_R_WR_N_

Mouser Electronics uthorized Distributor Click to iew Pricing, Inventory, Delivery & Lifecycle Information: NXP: BF9,25 BF9R,25 BF9WR,5

2024 © sciencedocbox.com Privacy Policy | Terms of Service | Feedback