CMOS Logic Gates University of Connecticut 172
Basic CMOS Inverter Operation V IN P O N O p-channel enhancementtype MOSFET; V T < 0 n-channel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and P O is linear. V OH. If V IN, N O is linear but P O is cut off. V OL 0. In either state, the DC power dissipation is negligible. CMOS is therefore very important for battery-powered applications such as watches, calculators, palmtops and laptops. In addition to the extremely low power dissipation, CMOS also exhibits better noise margins than NMOS with nearly as high packing density. University of Connecticut 173
CMOS Load Curve Analysis V IN 2.5V V T -0.6V K 0.5mA/V 2 P O I DD (ma) 1.0 0.8 V IN 0V V IN 2.5V N O V T 0.6V K 0.5mA/V 2 0.6 V IN 0.5V V IN 2V 0.4 The graphical load curve approach may be applied as with NMOS, but now the load curve is a function of V IN. 0.2 0.0 V IN 1V V IN 1.5V 0.0 0.5 1.0 1.5 2.0 2.5 (V) University of Connecticut 174
CMOS Load Curve Analysis V IN P O N O I I DN DP University of Connecticut 175
CMOS Load Curve Analysis V IN 2.5V P O N O V T -0.6V K 0.5mA/V 2 V T 0.6V K 0.5mA/V 2 I DD (ma) 0.25 0.20 0.15 V IN 1.5V e.g. if V IN 1.5V, then V V I V GSN GSP DD OUT 15. V 10. V 0. 04mA 0. 09 V University of Connecticut 176 0.10 0.05 0.00 V IN 1.5V 0.0 0.5 1.0 1.5 2.0 2.5 (V)
CMOS VTC V IN 2.5V P O N O V T -0.6V K 0.5mA/V 2 V T 0.6V K 0.5mA/V 2 (V) 2.5 2.0 For the case of perfectlymatched transistors, i. e. V TP V TN and K P K N, the VTC is symmetric: V V V + V V V M DD IL IH DD NML V / 2 NMH University of Connecticut 177 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 V IN (V)
CMOS VTC: Analytic Determination For V IN < V TN, the n-mosfet is cut off but the p-mosfet is linear, so For V TN < V IN < + V TN and V IN < - V TP, the n-mosfet is saturated but the p-mosfet is linear. Hence V I D OUT University of Connecticut 178
CMOS VTC: Analytic Determination In the vicinity of V IN V M, both MOSFET s are saturated. Thus, versus V IN cannot be determined without the knowledge of the channel length modulation parameters. For + V TN < V IN and + V TP < V IN < - V TP, the n-mosfet is linear but the p-mosfet is saturated. Hence V I D OUT Finally, for V IN > - V TP, the n-mosfet is linear but the p-mosfet is cut off so University of Connecticut 179
DC Current in CMOS 120 V IN 2.5V P O N O V T -0.6V K 0.5mA/V 2 V T 0.6V K 0.5mA/V 2 I DD (µa) 100 80 60 40 20 For V IN < V TN, N O is cut off and I DD 0. For V TN < V IN < /2, N O is saturated. For /2 < V IN < +V TP, P O is saturated. For V IN > + V TP, P O is cut off and I DD 0. 0.0 0.5 1.0 1.5 2.0 2.5 V IN (V) Even though CMOS exhibits negligible DC dissipation in either logic state, appreciable power is dissipated during switching. University of Connecticut 180 0
Design of CMOS Transistors Suppose the minimum feature size is 0.5 µ m, t OX 70 Angstroms, and we want K P K N 0.5 ma/ V 2. k ' P ( W / L) P k ' N ( W / L) N University of Connecticut 181
CMOS Switching Speed Consider a symmetric CMOS inverter with a lumped capacitive load C L. Suppose the input voltage rises abruptly from 0 to. N O is saturated until drops to - V T. During this time, constant current flows in N O : I DN N O becomes linear when - V T at t T D1. T D1 University of Connecticut 182
CMOS Switching Speed Once drops to - V T, N O moves into the linear region of operation. To a first approximation, I DN VOUT 1 I where average value of R R V DN Now if N O is linear, then DN DN OUT I DN I V DN OUT University of Connecticut 183
CMOS Switching Speed If starts at - V T and ends up at zero, then the average value of the partial derivative is approximately 1 R DN Using the ohmic approximation for N O, we have a simple RC circuit: VOUT ( t) Then reaches the 50% point ( /2) at t T D1 + T D2, where T D 2 University of Connecticut 184
CMOS Switching Speed The high-to-low propagation time is t PHL T D1 + T D2. Moreover, if the gate is perfectly symmetric, then t PLH t PHL. Thus t P Therefore the propagation delay is proportional to the load capacitance and inversely proportional to the K values for the (matched) transistors. For a fixed capacitive load, we need to scale up the K values to improve the switching speed. University of Connecticut 185
Loading of CMOS V IN 2.5V P O N O V T -0.6V 2.2µ m/ 0.5µ m V T 0.6V 0.9µ m/ 0.5µ m Suppose that K N K P 0.5 ma / V 2. 2 W KP 05. ma / V ' 2 L k 0113. ma / V P P 4. 4 2 W KN 0. 5mA / V ' 175. 2 L k 0. 286mA / V C OXP C OXN C IN C L University of Connecticut 186
SPICE Transient Response V 2.5V P O V IN N O C L 2. 5V K K 05. ma / V V V 0. 6 V C t DD P P TP L N TN 78 f F ps 150 (SPICE) 120ps (calculated) 2 output voltage input voltage 2.5 2.0 1.5 1.0 0.5 0.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 time (ns) University of Connecticut 187
CMOS Power Dissipation Under static (DC) conditions, the power dissipation is minimal (typically < 10 µw / gate). Under switching conditions, there is significant power dissipation. This is because the load capacitance is charged and discharged through dissipating elements (MOSFETs). During a low-to-high transition, current flows from as the load capacitance is charged from 0V to. The total integrated current is equal to C L, in coulombs. During a high-to-low transition, current flows to ground as the load capacitance is discharged from to 0V. The total integrated current is equal to C L, in coulombs. To avoid double counting, we should consider either current but not both. We will consider the ground current here. University of Connecticut 188
CMOS Power Dissipation V IN 2.5V P O N O C L Consider a symmetric CMOS inverter with a lumped capacitive load C L. Suppose the input voltage rises abruptly from 0 to. During T D1, N O is saturated until drops to - V T, and constant current flows in N O : I DN The total dissipation for 0 < t < T D1 is thus J 1 University of Connecticut 189
CMOS Power Dissipation Once drops to - V T, N O moves into the linear region of operation. J 2 But if the input voltage increases abruptly, the p-channel device switches off at t 0. Then, so that I DN J 2 University of Connecticut 190
CMOS Power Dissipation Therefore, the total energy dissipated for one cycle including a lowto-high transition and a high-to-low transition is J 1 + J 2 : J TOTAL The total dissipation is therefore P In the case of CMOS, the AC term is almost always dominant. For this reason, we can only talk about the PDP for CMOS if we specifiy the switching frequency. Note also that the switching frequency is generally less than the system clock frequency. University of Connecticut 191
CMOS Power Dissipation Consider a CMOS gate with a 2.5V supply, a 1 pf load, and 1 µ W DC dissipation 2.5V 1 mw 100 mw V IN P O 10 mw N O C L 1 mw 1k 10k 100k 1M 10M 100M switching frequency (Hz) Without an external load, the dissipation increases with switching frequency due to internal capacitance. This effect is quantized by the dissipation capacitance. University of Connecticut 192
CMOS Power Delay Product If we neglect the DC dissipation, then V IN P O P V C f 2 DD L The propagation delay is approximately N O C L t P C 2 KV L DD Therefore the PDP is frequency dependent and approximately VDDCL f PDP 2 2 K Thus it is important to decrease but it is extremely important to decrease the load capacitance. University of Connecticut 193
CMOS Power Delay Product In terms of the device design parameters, V IN P O K N O C L If C L comprises N on-chip loads, then C L Therefore the PDP is approximately PDP Now we know how to make better CMOS! University of Connecticut 194
CMOS Fan-out Increasing the fan-out increases t P. If C L comprises N on-chip loads, then V IN P O C L N O C L The K values are both equal to K Therefore t P N MAX University of Connecticut 195
CMOS NAND Gate 4011 NAND (ca 1965 A.D.) V B 25/5 25/5 V 3 to 15V 20/5 DD t 85 to 330ns P aluminum gate @ 50 pf L 5µ m t 1000 Angst roms min OX V A 20/5 Function: If any input goes low, then the associated p-mosfet turns on, the associated n-mosfet turns off, and the output goes high. Form: CMOS requires two MOSFETs per input, so the packing density is slightly less than for NMOS. University of Connecticut 196
CMOS NOR Gate 4001 NOR (ca 1965 A.D.) V A V B 50/5 50/5 V 3 to 15V DD t 85 to 330ns P aluminum gate @ 50 pf L 5µ m t 1000 Angstroms min OX 10/5 10/5 Function: If any input goes high, then the associated p-mosfet turns off, the associated n-mosfet turns on, and the output goes low. Form: There are still two transistors per input. However, the NOR gate requires 1/3 more chip area than the NAND gate. University of Connecticut 197
74HCxx CMOS Family 1/4 74HC00 NAND V A V A V B V B 9/3 9/3 35/3 90/3 7/3 7/3 15/3 35/3 V 4. 5 to 5. 5V t DD L 3µ m t P 600 Angstroms polysilicon gates P min OX DC 2.5µ W 15ns @ 15 pf V T 1V University of Connecticut 198
74HCxx CMOS Family: VTC 5V 9/3 35/3 90/3 V IN 3.5/3 15/3 35/3 1/6 74HC04 HEX INVERTER Double buffering makes the VTC very sharp, thus increasing the external noise margins. Do you see why? 2.3V 2.5V 2.7V 4.33V 0.00V 2.50V 2.50V 0.67V 5.00V 5.00V 2.50V 0.00V University of Connecticut 199
74HCxx CMOS Family: VTC 5 4 3 2 1/6 74HC04 HEX INVERTER The external noise margins are both essentially 2.5 V. The noise margins for the first stage alone are both 1.9 V. 1 0 0 1 2 3 4 5 University of Connecticut V IN 200
74HC CMOS Dynamic Response For all three stages, the process transconductance parameters are k ' N 2 k ' P 2 The oxide capacitance per unit area is C OX A University of Connecticut 201
74HC CMOS Dynamic Response 5V 9/3 35/3 90/3 V IN 3.5/3 15/3 35/3 C L 15 pf For stage A, K PA K C t NA LA PA University of Connecticut 202
74HC CMOS Dynamic Response 5V 9/3 35/3 90/3 V IN 3.5/3 15/3 35/3 C L 15 pf For stage B, K PB K C t NB LB PB University of Connecticut 203
74HC CMOS Dynamic Response 5V 9/3 35/3 90/3 V IN 3.5/3 15/3 35/3 C L 15 pf For stage C, K PC K C t NB LC PB University of Connecticut 204
74HC CMOS Dynamic Response 5V 9/3 35/3 90/3 V IN 3.5/3 15/3 35/3 C L 15 pf For the double-buffered gate, the total propagation delay is the sum of the individual delays: t P 0.8 ns 0.5 ns 13.8 ns University of Connecticut 205
74HC CMOS Dissipation 5V 9/3 35/3 90/3 V IN 3.5/3 15/3 35/3 C L 15 pf For the double-buffered gate, the energy dissipated per switching cycle is J TOT University of Connecticut 206
CMOS IC Fabrication polysilicon gate n+ n+ p+ p+ p well n well phosphosilicate glass (PSG) metal thick field oxide n- substrate or epitaxial layer thin gate oxide The twin well (or twin tub) process is used for state-of-the-art CMOS fabrication. Modern improvements in the process include trench isolation, silicided gates, and the use of n+ buried layers. In BICMOS, NPN bipolar transistors are fabricated alongside p- MOSFETs and n-mosfets. University of Connecticut 207
Latchup in CMOS polysilicon gate thin gate oxide phosphosilicate glass (PSG) n+ n+ p+ p+ p well n well metal thick field oxide n- substrate or epitaxial layer There are parasitic bipolar junction transistors inherent in the CMOS structure. Worse yet, the combination of a PNP and an NPN can form a PNPN device, which is a thyristor (or silicon controlled rectifier, SCR). Once turned on, the thyristor latches, and does not turn off after external bias is removed from the inner P and N regions. Once latched, the parasitic thyristor carries a large, steady, and usually destructive current from to ground. University of Connecticut 208
Latchup in CMOS n+ n+ p+ p+ Q 1 p well Q 2 Q 3 n well Q 4 CMOS inverter circuit with parasitics: P O n- substrate or epitaxial layer Q 2 Q 4 With a low output, Q 2 and Q 4 can latch on. With a high output, Q 1 and Q 3 can latch on. Latchup can be prevented by reducing the parasitic resistances and by reducing the betas of the parasitic bipolar transistors. V IN N O Q 3 Q 1 University of Connecticut 209
CMOS and Static Discharge diode protection circuitry bonding pad to CMOS circuitry Destructive oxide breakdown occurs at 5V for t OX 50 Angstroms. For a 0.25 µm x 1 µm gate, this corresponds to a charge of 1.7 femto coulombs, or about 10,000 electrons! Casual contact with humans or between leads can permanently damage CMOS if proper precautions are not taken. Diode protection circuitry, conductive packaging, and grounding straps have minimized this problem. University of Connecticut 210
Full Scaling of CMOS Full Scaling means that all voltages and dimensions are scaled by a factor of 1/s, where s > 1. C K OX t P ε µ n ε t OX t OX 2C KV 2 DD WL OX OX W L L DD P V C f L Power Density is scaled by is scaled by is scaled by is scaled by is scaled by Full scaling provides a DRAMATIC improvement in performance for CMOS, and even reduces the power density in watts per square centimeter. University of Connecticut 211
CMOS Constant Voltage Scaling Constant Voltage Scaling means that all dimensions are scaled by a factor of 1/s, where s > 1, but the voltages are unchanged. C K OX t P ε µ n ε t OX t OX 2C KV 2 DD WL OX OX W L L DD P V C f L Power Density is scaled by is scaled by is scaled by is scaled by is scaled by Constant voltage scaling is easier for the customer, but increases the power density. University of Connecticut 212
CMOS: Complex Logic Functions 20/2 20/2 20/2 20/2 V C 8/2 V D 8/2 V A 8/2 V B 8/2 The AND-OR-INVERT function can be achieved easily in CMOS using 2N transistors for N inputs. A C B D AC + BD University of Connecticut 213
CMOS: Complex Logic Design CIRCUIT DESIGN ANDing is achieved by series stacks of n-mosfets and parallel connection of p-mosfets. ORing is achieved by paralleling n-mosfets and the series stacking of p-mosfets. MOSFET DESIGN For the inverter, (W P / L P ) 2.5(W N / L N ). (e.g., 10 / 2 and 4 / 2) For the AOI gate, W L N N m W N L AOI N INVERTER where m is the number of series n-mosfets in the longest pull-down path and n is the number of series p-mosfets in the longest pull-up path. (in the example pictured, m 2, and n 2) University of Connecticut 214 W L P P n W P L AOI P INVERTER
Pseudo NMOS Logic Similar to NMOS, w/ p-mosfet pull-up X M PL pull-down network OUT Efficient realization of complex logic functions Improved packing density Disadvantage? University of Connecticut 215
Dynamic CMOS M PPRE CLK precharge evaluate precharge evaluate OUT IN M NO V IN CLK M NEVAL Dynamic CMOS Inverter t University of Connecticut 216
Dynamic CMOS M PPRE M PPRE X pulldown network OUT X pullup network OUT CLK M NEVAL CLK M NEVAL University of Connecticut 217
Dynamic CMOS Can t be Cascaded! CLK M PPREA M PPREB OUT A A M NOA B M NOB B CLK M NEVALA M NEVALB OUT t University of Connecticut 218
Domino Logic M PPRE M PPRE M PPRE A pulldown network B pullup network C pulldown network OUT CLK M NEVAL CLK M NEVAL CLK M NEVAL University of Connecticut 219