Frequency Response Prof. Ali M. Niknejad Prof. Rikky Muller

Similar documents
EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

Lecture 37: Frequency response. Context

I. Frequency Response of Voltage Amplifiers

The Miller Approximation

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Chapter 9 Frequency Response. PART C: High Frequency Response

6.012 Electronic Devices and Circuits Spring 2005

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

EE 330. Lecture 35. Parasitic Capacitances in MOS Devices

Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

ECEN 326 Electronic Circuits

ECE 546 Lecture 11 MOS Amplifiers

Multistage Amplifier Frequency Response

Lecture 23 - Frequency Resp onse of Amplifiers (I) Common-Source Amplifier. May 6, 2003

Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

EECS 105: FALL 06 FINAL

Electronic Circuits Summary

EE 240B Spring Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models. Elad Alon Dept. of EECS

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

Exact Analysis of a Common-Source MOSFET Amplifier

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

Voltage AmpliÞer Frequency Response

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation

University of Toronto. Final Exam

ECE 255, Frequency Response

Sample-and-Holds David Johns and Ken Martin University of Toronto

EE105 Fall 2014 Microelectronic Devices and Circuits

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Refinements to Incremental Transistor Model

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology

Homework Assignment 09

Homework Assignment 08

Berkeley. Matching Networks. Prof. Ali M. Niknejad. U.C. Berkeley Copyright c 2016 by Ali M. Niknejad

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

Homework 6 Solutions and Rubric

MOS Transistor Theory

Lecture 14: Electrical Noise

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

CE/CS Amplifier Response at High Frequencies

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

Design of Analog Integrated Circuits

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers

Lecture 3: CMOS Transistor Theory

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 04: Single Transistor Ampliers

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

Sophomore Physics Laboratory (PH005/105)

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process

Lecture 06: Current Mirrors

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

Two-Port Noise Analysis

Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers

Digital Microelectronic Circuits ( )

Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

Chapter 13 Small-Signal Modeling and Linear Amplification

Electronics II. Final Examination

EE C245 ME C218 Introduction to MEMS Design Fall 2011

Electronics II. Final Examination

MOS Transistor Theory

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Lecture 12 CMOS Delay & Transient Response

EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

Lecture Stage Frequency Response - I (1/10/02) Page ECE Analog Integrated Circuits and Systems II P.E.

6.301 Solid-State Circuits Recitation 14: Op-Amps and Assorted Other Topics Prof. Joel L. Dawson

D is the voltage difference = (V + - V - ).

Practice 7: CMOS Capacitance

Charge-Storage Elements: Base-Charging Capacitance C b

Advanced Current Mirrors and Opamps

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

CMOS Analog Circuits

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

Chapter 2 Switched-Capacitor Circuits

EE 40: Introduction to Microelectronic Circuits Spring 2008: Midterm 2

The Gradual Channel Approximation for the MOSFET:

In this lecture, we will consider how to analyse an electrical circuit by applying KVL and KCL. As a result, we can predict the voltages and currents

EE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances

Chapter 10 Feedback. PART C: Stability and Compensation

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

ECE137B Final Exam. There are 5 problems on this exam and you have 3 hours There are pages 1-19 in the exam: please make sure all are there.

MOS Transistor I-V Characteristics and Parasitics

Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today

55:041 Electronic Circuits The University of Iowa Fall Final Exam

Device Models (PN Diode, MOSFET )

1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)

Designing Information Devices and Systems II Fall 2018 Elad Alon and Miki Lustig Discussion 5A

Figure 1: MOSFET symbols.

Circuit Topologies & Analysis Techniques in HF ICs

EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits

Stability and Frequency Compensation

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130

Transcription:

EECS 105 Spring 2017, Module 4 Frequency Response Prof. Ali M. Niknejad Department of EECS

Announcements l HW9 due on Friday 2

Review: CD with Current Mirror 3

Review: CD with Current Mirror 4

Review: CD with Current Mirror 5

Capacitors in MOS Device C gs = (2 / 3)WLC ox + C ov C gd = C ov C sb = C jsb (area + perimeter) junction C db = C jdb (area + perimeter) junction 6

Common-Source Voltage Amplifier Small-signal model: C sb is connected to gnd on both sides, therefore can be ignored R S Can solve problem directly by nodal analysis or using 2-port models of transistor OK if circuit is small (1-2 nodes) 7 We can find the complete transfer function of the circuit, but in many cases it s good enough to get an estimate of the -3dB bandwidth

CS Voltage Amp Small-Signal Model Two Nodes! Easy For now we will ignore C db to simplify the math 8

Frequency Response KCL at input and output nodes; analysis is made complicated V out = g m r o R L V in 1+ jω /ω p1 [ ]( 1 jω /ω z ) ( )( 1+ jω /ω p2 ) Zero Low-frequency gain: ( ) ( )( 1+ j0) V out = g r R m o L 1 j0 V in 1+ j0 Two Poles g m r o R L ü Zero: ω z = g m C gs + C gd 9

Calculating the Poles ω p1 1 R s C gs + ( 1+ g m R out )C gd { } + R out C gd ω p2 R out / R S R S C gs + ( 1+ g m R out )C gd { } + R out C gd Usually >> 1 Results of complete analysis: not exact and little insight 10 These poles are calculated after doing some algebraic manipulations on the circuit. It s hard to get any intuition from the above expressions. There must be an easier way!

Method: The Miller Effect 11

The Miller Effect 12

Using The Miller Effect Effective input capacitance: C in = 1 jωc Miller = 1 1 A v,cgd 1 jωc gd = 1 jω ( 1 A vcgd )C gd 13

CS Voltage Amp Small-Signal Model Modified Small-Signal Model with Miller Effect: C gs +C Miller We can approximate the first pole by using Miller capacitance This gives us a good approximation of the -3dB bandwidth 14

Comparison with Exact Analysis Miller result (calculate RC time constant of input pole): Exact result: ω p1 1 = R S C gs + ( 1+ g m R out ʹ )C gd ω p1 1 = R S C gs + ( 1+ g m R out ʹ )C gd + R out ʹ C gd As a result of the Miller effect there is a fundamental gain-bandwidth tradeoff 15

Common Drain Amplifier Calculate Bandwidth of the Common Drain (Source- Follower) 16 Procedure: 1. Replace current source with MOSFET-based current mirror 2. Draw small-signal model with capacitors (for simplicity, we will focus on C gd and C gs ) 3. Find the DC small-signal gain 4. Use the Miller effect to calculate the input capacitance 5. Calculate the dominant pole

Two-Port CC Model with Capacitors R S 17 -Find DC Gain -Find Miller capacitor for C gs -- note that the gate-source capacitor is between the input and output!

Voltage Gain Across C gs Write KCL at output node: v out r o r oc = g m v gs = g m (v in v out ) 1 v out + g m r o r = g v m in oc v out v in = r o g m 1 + g r m oc = g m (r o r oc ) 1+ g m (r o r oc ) = A vcgs 18

Compute Miller Effected Capacitance Now use the Miller Effect to compute C in : Remember that C gs is the capacitor from the input to the output R S C in = C gd + C M C in = C gd + (1 A vcgs )C gs Miller Cap C in = C gd + (1 g m (r o r oc ) 1+ g m (r o r oc ) )C gs 1 C in = C gd + ( 1+ g m (r o r oc ) )C gs 19 C in C gd (for large g m (r o //r oc ))

Bandwidth of Source Follower Input low-pass filter s 3 db frequency: C ω 1 p = R S C gd + gs 1+ g m (r o r oc ) Substitute favorable values of R S, r o : R 1/ S g m r o >>1/ g m ω p 1 1/ g m ( ) C gd + C gs C gd / g m 1+ BIG Very high frequency! Model not valid at these high frequencies ω p g m / C gd 20

Some Examples Common source amplifier: A vcgd = Negative, large number (-100) C Miller = (1 A V,Cgd )C gd 100C gd Miller Multiplied Cap has detrimental impact on bandwidth Common drain amplifier: A vcgs = Slightly less than 1 C Miller = (1 A V,Cgs )C gs! 0 Bootstrapped cap has negligible impact on bandwidth! 21