OptiMOS Power-Transistor

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Preliminary data. Maximum Ratings,at T j = 25 C, unless otherwise specified Parameter Symbol Value Unit Continuous drain current I D.

Preliminary data. Maximum Ratings,at T j = 25 C, unless otherwise specified Parameter Symbol Value Unit Continuous drain current I D. I D puls -2.

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Transcription:

OptiMOS Power-Transistor Features N-channel - Enhancement mode Automotive AEC Q11 qualified MSL1 up to 26 C peak reflow 175 C operating temperature Green package (lead free) Product Summary V DS 75 V R DS(on),max 21.5 mω I D 3 A PG-TO252-3-11 Ultra low Rds(on) 1% Avalanche tested Type Package Marking IPD3N8S2-22 PG-TO252-3-11 2N822 Maximum ratings, at T j =25 C, unless otherwise specified Parameter Symbol Conditions Value Unit Continuous drain current I D T C =25 C, V GS =1 V 1) 3 A T C =1 C, V GS =1 V 2) 3 Pulsed drain current2 ) I D,pulse T C =25 C 12 Avalanche energy, single pulse E AS I D =3A 24 mj Gate source voltage V GS ±2 V Power dissipation P tot T C =25 C 136 W Operating and storage temperature T j, T stg -55... +175 C IEC climatic category; DIN IEC 68-1 55/175/56 Rev. 1. page 1 26-7-18

Parameter Symbol Conditions Values Unit min. typ. max. Thermal characteristics 2) Thermal resistance, junction - case R thjc - - 1.1 K/W Thermal resistance, junction - ambient, leaded R thja - - 1 SMD version, device on PCB R thja minimal footprint - - 75 6 cm 2 cooling area 3) - - 5 Electrical characteristics, at T j =25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS = V, I D = 1 ma 75 - - V Gate threshold voltage V GS(th) V DS =V GS, I D =8 µa 2.1 3.1 4. Zero gate voltage drain current I DSS V DS =75 V, V GS = V, T j =25 C -.1 1 µa V DS =75 V, V GS = V, T j =125 C 2) - 1 1 Gate-source leakage current I GSS V GS =2 V, V DS = V - 1 1 na Drain-source on-state resistance R DS(on) V GS =1 V, I D =5 A, - 17.4 21.5 mω Rev. 1. page 2 26-7-18

Parameter Symbol Conditions Values Unit min. typ. max. Dynamic characteristics 2) Input capacitance C iss - 14 - pf Output capacitance C oss V GS = V, V DS =25 V, f =1 MHz - 39 - Reverse transfer capacitance C rss - 18 - Turn-on delay time t d(on) - 13 - ns Rise time t r V DD =4 V, V GS =1 V, - 3 - Turn-off delay time t d(off) I D =3 A, R G =7.5 Ω - 33 - Fall time t f - 2 - Gate Charge Characteristics 2) Gate to source charge Q gs - 8 8.6 nc Gate to drain charge Q gd V DD =6 V, I D =3 A, - 21 36 Gate charge total Q g V GS = to 1 V - 44 57 Gate plateau voltage V plateau - 5.5 - V Reverse Diode Diode continous forward current 2) I S T C =25 C - - 3 A Diode pulse current 2) I S,pulse - - 12 Diode forward voltage V SD V GS = V, I F =3 A, T j =25 C Reverse recovery time 2) t rr V R =4 V, I F =I S, di F /dt =1 A/µs Reverse recovery charge 2) Q rr V R =4 V, I F =I S, di F /dt =1 A/µs -.9 1.3 V - 57 - ns - 13 - nc 1) Current is limited by bondwire; with an R thjc = 1.1K/W the chip is able to carry 52A at 25 C. For detailed information see Application Note ANPS71E at www.infineon.com/optimos 2) Defined by design. Not subject to production test. 3) Device on 4 mm x 4 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 7 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1. page 3 26-7-18

1 Power dissipation 2 Drain current P tot = f(t C ); V GS 6 V I D = f(t C ); V GS 1 V 16 35 14 3 12 25 P tot [W] 1 8 6 2 15 4 1 2 5 5 1 15 2 T C [ C] 5 1 15 2 T C [ C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(v DS ); T C = 25 C; D = Z thjc = f(t p ) parameter: t p parameter: D =t p /T 1 1 µs 1.5 1 1 µs 1 ms 1 µs Z thjc [K/W] 1-1.1.5 1 1-2.1 single pulse 1.1 1 1 1 V DS [V] 1-3 1-7 1-6 1-5 1-4 t p [s] 1-3 1-2 1-1 1 Rev. 1. page 4 26-7-18

5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(v DS ); T j = 25 C R DS(on) = (I D ); T j = 25 C parameter: V GS parameter: V GS 12 1 V 1 7 V 9 5.5 V 6 V 6.5 V 8 7 7 V 6 4 6.5 V 6 V R DS(on) [mw] 5 5.5 V 3 2 5 V 1 V 2 4 6 8 1 V DS [V] 1 2 4 6 8 1 12 7 Typ. transfer characteristics 8 Typ. Forward transconductance I D = f(v GS ); V DS = 6V g fs = f(i D ); T j = 25 C parameter: T j 12 parameter: g fs 5 1 4 8 3 6 g fs [S] 2 4 2 25 C 1 175 C -55 C 2 3 4 5 6 7 V GS [V] 1 2 3 4 5 Rev. 1. page 5 26-7-18

9 Typ. Drain-source on-state resistance 1 Typ. gate threshold voltage R DS(ON) = f(t j ) parameter: I D = 25 A; V GS = 1 V 4 V GS(th) = f(t j ); V GS = V DS parameter: I D 4 35 3.5 3 4 µa R DS(on) [mω] 25 V GS(th) [V] 3 2.5 8 µa 2 15 2 1-6 -2 2 6 1 14 18 T j [ C] 1.5-6 -2 2 6 1 14 18 T j [ C] 11 Typ. capacitances 12 Typical forward diode characteristicis C = f(v DS ); V GS = V; f = 1 MHz IF = f(v SD ) parameter: T j 1 4 1 3 Ciss 1 3 1 2 C [pf] Coss I F [A] 1 2 Crss 1 1 175 C 25 C 5 1 15 2 25 3 V DS [V] 1.2.4.6.8 1 1.2 1.4 1.6 V SD [V] Rev. 1. page 6 26-7-18

13 Typical avalanche energy 14 Typ. gate charge E AS = f(t j ) V GS = f(q gate ); I D = 3 A pulsed parameter: I D 1 7.5 A 12 8 1 15 V 6 V 8 6 E AS [mj] 4 15 A V GS [V] 6 4 2 3 A 2 25 75 125 175 T j [ C] 1 2 3 4 5 Q gate [nc] 15 Typ. drain-source breakdown voltage 16 Gate charge waveforms V BR(DSS) = f(t j ); I D = 1 ma 9 V GS 85 Q g V BR(DSS) [V] 8 75 7 Q gate Q gs Q gd 65-6 -2 2 6 1 14 18 T j [ C] Rev. 1. page 7 26-7-18

Published by Infineon Technologies AG Am Campeon 1-12 D-85579 Neubiberg Infineon Technologies AG 1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices, please contact your nearest Infineon Technologies Office (www.infineon.com) Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact your nearest Infineon Technologies Office. Infineon Technologies' components may only be used in life-support devices or systems with the expressed written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1. page 8 26-7-18