II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III - V group: GaAs GaN GaSb GaP InAs InP InSb...
The Energy Band Structure conduction band E F Fermi Level conductor valence band semiconductor Eg~0.16 aj insulator Eg~1.6 aj Material Electrical conductivity σ Metal σ > 10 5 Ω -1 m -1 Semiconductor 10 5 Ω -1 m -1 > σ > 10-8 Ω -1 m -1 Insulator σ < 10-8 Ω -1 m -1
ontrolling onductivity σ = qnμ
MOS Transistor transfer resistor 1930 J. Lilienfend applied for a patent regarding a fieldeffect device in USA 1935 O. Heil - similar patent in UK 1960 Practical manufacturing of a field-effect transistor
MOS Transistor Metal Oxide Semiconductor Various names: MOSFET, MIS, IGFET Polysilicon gate Dielectric layer Metal electrode Drain and source islands ρ of the substrate: 0.01-0.1 Ωm n+ concentration: 10 24-10 26 m -3 t ox: : 1-100 nm Semiconductor substrate
The MOS apacitor V G Al Oxide P-type silicon Accumulation Depletion Inversion V G <0 V G >0 V G >>0
nmos ross-section Gate Source Drain Metal Polysilicon Silicon dioxide N-type diffusion P-type substrate
lassification of MOS Transistors N-channel P-channel Depletion mode Enhancement mode
nmos Transistor with Biased Gate V G >0 Gate V S =0 Source Drain V D =0 Metal Polysilicon Silicon Dioxide N-type diffusion P-type substrate hannel
Beginning of The Strong Inversion V G =V T E c q φ s = 2 q φ f qφ f E j E F E f
onducting nmos Transistor V G >0 V S =0 Source Gate Drain V G -V T >V D >0
onducting nmos at The Beginning of Saturation V G >0 V S =0 Źródło Bramka Dren V G -V T =V D >0
Saturated nmos Transistor V G >0 V S =0 Źródło Bramka Dren V D >V G -V T A
MOS Symbols N-type enhancement mode G D B S D B S G D S P-type enhancement mode N-type depletion mode P-type depletion mode
nmos as A Switch + 5V + 5V
pmos as A Switch + 5V + 5V
MOS in Linear Range L=L eff +2L d I DS L eff x x+dx L eff -L d 0 L eff +L d x
I DS = W µ L eff eff ox U DS 0 ( U V V ( x) ) GS T 0 dv I DS = µ W L eff eff ox 2 (( U V ) U 1 U ) GS T 0 DS 2 DS I DS = k p W L eff eff (( ) 1 ) 2 U V U U GS T 0 DS 2 DS Linear I DS = k p 2 W L eff eff ( U V ) 2 GS T 0 Saturation β = µε/t ox (W/L) Transistor gain factor
MOS Output haracteristics I D U GS =5 linear U DS =U GS -V T U GS =4 saturation U GS =3 U GS =2 U GS =1 U DS
MOS Transfer haracteristics I D saturation linear U GS V T
hannel Length Modulation V G >V T0 V S >V DSsat L' eff L L eff
Model LEVEL1 I D U DS =U GS -V T U GS =5 linear U GS =4 saturation U GS =3 U GS =2 U GS =1 U DS
SPIE D Parameters for 1µm MOS Parameter nmos pmos Units Description VTO 0.7 0.7 volt Threshold voltage KP 8*10-5 2.5*10-5 A/V 2 Transconductance coefficient GAMMA 0.4 0.5 V 0.5 Bulk threshold parameter PHI 0.37 0.36 volt Surface potential at strong inversion LAMBDA 0.01 0.01 volt -1 hannel length modulation parameter LD 0.1*10-6 0.1*10-6 meter Lateral diffusion TOX 2*10-8 2*10-8 meter Oxide thickness NSUB 2*10 16 4*10 16 1/cm 3 Substrate doping density
What s new in LEVEL3 Modified threshold voltage model, taking into account the drain induced barrier lowering (DIBL) Longitudinal and transversal electric field dependent mobility model Improved channel length modulation and saturation voltage model Weak inversion (subthreshold) range
Trapezoidal harge Approximation x j X D W c
Subthreshold Range ln(i DS ) U GS V T V on
Temperature Influence on MOS haracteristics I DS 20 O 120 O A U GS
MOS apacitances GATE GSov GS GD GDov SOURE DRAIN BS GB BD
MOS apacitancies P S1 Polysilicon gate Dielectric layer P S2 Source Drain A D P S3
MOS apacitances BD j A = U 1 φ j = GDov D BD M GDO + 1 jsw j M jsw W eff U φ BD j P D = = GSO GDO BS j A = U BS 1 φ j = ox GSov L d S M GSO + 1 jsw j M jsw W eff U φ BS j P S Accumulation Depletion = GB ox W eff L eff GB = 1+ ox W U 4 eff GB L eff U 2 γ FB
MOS apacitances Linear range ( GB = 0) for GS 2 3 1 2 ( U ) ( ) GS UT U GS UT + U GD UT = oxweff Leff 2 2 3 1 2 ( U ) ( ) GD UT U GS UT + U GD UT GD = oxweff Leff 2 UGS U GD Saturation range ( GD = 0) 2 GS = oxweff Leff 3 GS GD 1 2 ox W eff L eff
apacitance-voltage haracteristics 1 / i i = ox L eff W eff G GS GD 0 ut-off Saturation Linear GB U GS
What s Missing in LEVEL3 Hot carrier effect Punch-through Non-uniform substrate doping
MOS - Summary Operation range ut-off Linear, non-saturation, triode Saturation, pentode Sub-threshold, weak inversion Pin voltages U GS <U FB U GS V T i U DS <U Dsat U GS V T i U DS U Dsat U FB U GS <V T N-type enhancement mode I DS U GS I DS U DS I DS U GS I DS P-type enhancement mode U DS N-type depletion mode I DS U GS I DS U DS I DS U GS I DS P-type depletion mode U DS