Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 4HC4 is identical in pinout to the LS4. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device coists of two D flip flops with individual Set, Reset, and Clock inputs. Information at a D input is traferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip flop. The Set and Reset inputs are asynchronous. Features Output Drive Capability: 0 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Range: to Low Input Current:.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. A Requirements ESD Performance: HBM 00 ; Machine Model 0 Chip Complexity: 28 FETs or 32 Equivalent Gates Pb Free Packages are Available 4 4 4 SOIC 4 D SUFFIX CASE A TSSOP 4 DT SUFFIX CASE 948G MARKING DIAGRAMS 4 HC4G AWLYWW HC 4 ALYW HC4 = Device Code A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 4 of this data sheet. Semiconductor Components Industries, LLC, 0 February, 0 Rev. 0 Publication Order Number: 4HC4/D
PIN ASSIGNMENT LOGIC DIAGRAM RESET 4 RESET DATA SET Q Q 2 3 4 5 6 2 FUNCTION TABLE Inputs Outputs Set Reset Clock Data Q Q L H X X H L H L X X L H L L X X H* H* H H H H L H H L L H H H L X No Change H H H X No Change H H X No Change 3 0 9 8 RESET 2 DATA 2 2 SET 2 DATA SET RESET 2 DATA 2 2 SET 2 2 3 4 3 2 0 5 6 9 8 PIN 4 = PIN = Q Q *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. MAXIMUM RATINGS Symbol Parameter alue Unit DC Supply (Referenced to ) 0.5 to +.0 in DC Input (Referenced to ) 0.5 to + 0.5 out DC Output (Referenced to ) 0.5 to + 0.5 I in DC Input Current, per Pin ± ma I out DC Output Current, per Pin ±25 ma I CC DC Supply Current, and Pi ±50 ma P D Power Dissipation in Still Air, SOIC Package mw TSSOP Package 450 T stg Storage Temperature 65 to + 50 C T L Lead Temperature, mm from Case for 0 Seconds C (SOIC or TSSOP Package) 260 0 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability. Derating SOIC Package: mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C For high frequency or heavy load coideratio, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit DC Supply (Referenced to ) in, out DC Input, Output (Referenced to ) 0 T A Operating Temperature, All Package Types 55 + 25 C t r, t f Input Rise and Fall Time = 0 000 (Figures, 2, 3) = = = 0 0 0 600 This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. 2
DC ELECTRICAL CHARACTERISTICS (s Referenced to ) Guaranteed Limit Symbol Parameter Test Conditio () 55 to 25 C 85 C 25 C Unit IH Minimum High Level Input out = 0. or 0..5 2. 3.5 4.2.5 2. 3.5 4.2.5 2. 3.5 4.2 IL Maximum Low Level Input out = 0. or 0. 0.5 0.9.35.8 0.5 0.9.35.8 0.5 0.9.35.8 OH OL Minimum High Level Output Maximum Low Level Output I out 2.4 ma I out 4.0 ma I out 5.2 ma I out 2.4 ma I out 4.0 ma I out 5.2 ma I in Maximum Input Leakage Current in = or ±0. ±.0 ±.0 A I CC Maximum Quiescent Supply Current (per Package) in = or I out = 0 A 80 A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = ) Symbol f max t PLH, t PLH, t TLH, t THL Parameter Maximum Clock Frequency ( Duty Cycle) (Figures and 4) Maximum Propagation Delay, Clock to Q or Q (Figures and 4) Maximum Propagation Delay, Set or Reset to Q or Q (Figures 2 and 4) Maximum Output Traition Time, Any Output (Figures and 4) ().9 4.4 5.9 2.48 3.98 5.48 0. 0. 0. 0.26 0.26 0.26.9 4.4 5.9 2.34 3.84 5.34 0. 0. 0. 0.33 0.33 0.33.9 4.4 5.9 2.2 3. 5.2 0. 0. 0. 0.4 0.4 0.4 Guaranteed Limit 55 to 25 C 85 C 25 C C in Maximum Input Capacitance 0 0 0 pf NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). Typical @ 25 C, = 5.0 C PD Power Dissipation Capacitance (Per Flip Flop)* 32 pf * Used to determine the no load dynamic power coumption: P D = C PD 2 CC f + I CC. For load coideratio, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). 5 35 00 05 80 2 8 5 3 4.8 0 24 28 25 90 25 2 95 26 22 95 40 9 6 4.0 24 50 26 60 32 2 0 55 22 9 Unit MHz 3
TIMING REQUIREMENTS (Input t r = t f = ) Guaranteed Limit Symbol Parameter () 55 to 25 C 85 C 25 C Unit t su Minimum Setup Time, Data to Clock (Figure 3) 80 35 6 4 00 45 55 24 t h Minimum Hold Time, Clock to Data (Figure 3) t rec Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Clock (Figure ) 60 25 2 0 5 3 90 40 8 5 Minimum Pulse Width, Set or Reset (Figure 2) 60 25 2 0 5 3 90 40 8 5 t r, t f Maximum Input Rise and Fall Times (Figures, 2, 3) 000 800 000 800 000 800 ORDERING INFORMATION Device Package Shipping 4HC4D 4HC4DG 4HC4DR2 4HC4DR2G 4HC4DTR2 4HC4DTR2G SOIC 4 SOIC 4 (Pb Free) SOIC 4 SOIC 4 (Pb Free) TSSOP 4* TSSOP 4* 55 Units / Rail 2 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *This package is inherently Pb Free. 4
SWITCHING WAEFORMS 90% 0% t f t r /f max SET OR RESET Q OR Q Q or Q 90% 0% t PLH t TLH t THL Q OR Q t PLH t rec Figure. Figure 2. DATA t su ALID t h DEICE UNDER TEST OUTPUT TEST POINT C L * *Includes all probe and jig capacitance Figure 3. Figure 4. 4, 0 SET DATA 2, 2 5, 9 Q 3, 6, 8 Q, 3 RESET Figure 5. EXPANDED LOGIC DIAGRAM 5
PACKAGE DIMENSIONS SOIC 4 CASE A 03 ISSUE H T SEATING PLANE A 4 8 G B P PL 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, 982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.2 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES C R X 45 F DIM MIN MAX MIN MAX A 8.55 8. 0.33 0.344 B 3.80 4.00 0.50 0.5 C.35. 0.054 0.068 D 0.35 0.49 0.04 0.09 D 4 PL K M J F 0.40.25 0.06 0.049 G.2 BSC 0.050 BSC 0.25 (0.00) M T B S A S J 0.9 0.25 0.008 0.009 K 0.0 0.25 0.004 0.009 M 0 0 P 5.80 6. 0.228 0.244 R 0.25 0.50 0.00 0.09 SOLDERING FOOTPRINT* 4X 0.58 X.04 4X.52.2 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6
PACKAGE DIMENSIONS TSSOP 4 CASE 948G 0 ISSUE B 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C 4 4X K REF 0.0 (0.004) M T U S S N 8 0.25 (0.00) M B U A G H N J J F DETAIL E K K ÇÇÇ ÇÇÇ ÉÉÉ SECTION N N DETAIL E W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, 982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.0 0.93 0.0 B 4. 0 0.69 0. C. 0.04 D 0.05 0.5 0.002 0.006 F 0.50 0. 0.0 0.0 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.0 0.024 J 0.09 0. 0.004 0.008 J 0.09 0.6 0.004 0.006 K 0.9 0. 0.00 0.02 K 0.9 0.25 0.00 0.00 L 6.40 BSC 0.252 BSC M 0 8 0 8 SOLDERING FOOTPRINT*.06 0.65 PITCH 4X 0.36 4X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.