> ccepted fr publicatin in IEEE TCS - II < The Study f a Dual-Mde ing Oscillatr Zuw-Zun Chen and Tai-Cheng Lee Member IEEE bstract n analytical investigatin f a dual-mde ring scillatr is presented. The ring scillatr is cnstructed in a CMOS.8-μm technlgy with differential 8-stage delay cells emplying auxiliary input devices. With prper startup cntrl the scillatr perates in tw different mdes cvering tw different frequency bands. nnlinear mdel alng with linearizatin methd is used t btain the transient and steady-state behavirs f the dual-mde ring scillatr. The analytical derivatins are verified thrugh HSPICE simulatin. The scillatr perates at the frequency bands frm ~ 5 GHz and frm. ~ GHz respectively. Index Terms Fractinal-N frequency synthesizer multiphase signals ring scillatrs vltage-cntrl scillatrs (COs. I. INTODUCTION ing scillatrs are fund in varius f cmmunicatin systems and clck generatrs. Cmpared with their LC-CO cunterparts ring scillatrs have the advantage f small size highly integratin multiphase utputs and wide scillatin range. Multiphase signals are required by cmmunicatin systems such as phase-array transceivers clck data recvery circuits (CD and fractinal-n frequency synthesizers (FNFS. In delta-sigma FNFS multiphase ring scillatrs are used t reduce quantizatin nise [] thus allwing a wide lp bandwidth t achieve faster settling time and better immunity t CO induced phase nise. In view f the demand fr a large number f distinct phases the number f delay stages must be large which leads t lwer scillatin frequency and prer phase spacing reslutin. Delay cells with auxiliary input devices are ften emplyed t achieve high scillatin frequencies in lng-chain ring scillatrs []-[7]. Wide range scillatrs are als demanded by cmmunicatin systems that are intended t cver different standards at varius frequency bands. In ring scillatrs wide scillatin range is achieved by tuning the tail current and lading resistance f each delay cell r by dividing and mixing the utput signal. Multiple scillatin mdes are ften fund in ring scillatrs which emply delay cells with auxiliary input devices [][6]. Cnstraint fr stable scillatin at the desired mde is This wrk was supprted by Natinal Science Cuncil (NSC under Cntract 99--E---. The authrs are with the Department f Electrical Engineering and the Graduate Institute f Electrnics Engineering Natinal Taiwan University Taipei 6 Taiwan. Cpyright (c IEEE. Persnal use f this material is permitted. Hwever permissin t use this material fr any ther purpses must be btained frm the IEEE by sending an email t pubs-permissins@ieee.rg. explained in [6]. Hwever the characteristics f multi-mde ring scillatrs remain unidentified. Mtivated by these ambiguus multi-mde phenmena in this brief we prvide a thrugh analysis f multi-mde ring scillatrs. dual-mde 8-stage ring scillatr with delay cells utilizing auxiliary input devices is presented as an example. startup circuit is prpsed t cntrl the dual-mde ring scillatr t perate in either the tw mdes. nnlinear mdel f the ring scillatr is als intrduced. The vltage-t-current transfer functin f nnlinear devices is mdeled with plynmial equatins. Further by applying linearizatin methds as addressed in [8][9] behavirs including the utput phase relatin amplitude scillatin frequency and criterin f scillatin at either the tw mdes are given. nalytical expressins f the criterin f scillatin explain the cnditins which prvke the ring scillatr t shift t different mdes and the situatins fr it t remain in ne f the multiple mdes. The analytical equatins presented permit an accurate predictin f the ring scillatr and the results are verified by simulatins. In sectin II the generic cncept f the dual-mde ring scillatr is presented. The startup circuit and its peratin are als prvided. In sectin III a nnlinear mdel is used t describe the behavir as well as the stability f the tw scillatin mdes. In sectin I simulatin results are presented t illustrate the validity f the derived analytical equatins. cnclusin is then given in sectin. 6 b b 5b 8b 7b 8 5 Fig. Dual-mde ring scillatr. 8b b 8 b 6 b b b 5b 5 b b II. DELY CELL WITH UXILIY INPUT DEICES Figure shws the diagram f the presented dual-mde ring scillatr. The tplgy is chsen because it achieves tw scillatin mdes ne f high scillatin frequency and the ther f lw scillatin frequency. Mrever as will be explained later bth mdes retain 6 distinct utput phases. Differential delay cells are used fr greater cmmn-mde nise rejectin. The schematic f each delay cell is depicted in Fig.. Each delay cell is cnstructed with a pair f main input devices M and a pair f auxiliary input devices M that
> ccepted fr publicatin in IEEE TCS - II < frms a secndary delay path. Furthermre transistrs M 56 perate in the tride regin and wrk as utput resistive lads. The equivalent resistance can be adjusted thrugh cntrl signal v ctl. The sum f the tw differential pair tail current I I and I is designed t be cnstant I ttal = I I + I. In this brief t ensure the dual-mde scillatin a startup circuit is emplyed t cntrl the tail current f main input devices and auxiliary input devices via v ctl Fig.. The peratin f the startup circuit is explained belw. ctl in M 5 M 6 M M DD ut M M aux additinal delay path. Hwever in cntrast t mde nw the auxiliary input devices frm the main delay path and the main input devices cnstruct the additinal delay path. Therefre with aid f Fig. the blck diagram f Fig. can be redrawn as Fig. fr mde scillatin. The phase relatin f the tw mdes is shwn in Fig. 5. lthugh the rder f the utput phases is different the number f distinct phases is the same bth cntain 6 distinct phases. Nevertheless different circuit tplgies such as number f stages delay cell architecture and intercnnectins affect the pssible scillatin mdes and utput phase relatins [6]. These characteristics can be determined thrugh slving fr the general slutins f the ring scillatr using small-signal linear apprximatin. bin bin M 7 M 8 I I DD I + I I M c ctl M c baux baux M 9 I M I + I I M c bias M c 6 b b b b b b b 8 6 5 5b b 5 b 8 8b bin bin M c6 M c7 M c5 M c8 baux baux Fig. Schematic f delay cell. Schematic f startup circuit. in g min ut g min aux aux in g maux g maux ut g maux g maux g min g min Fig. Dual-delay-path ring scillatr. Mde. Mde. Mde : T ensure mde v ctl is at first set lw. The bias current will mainly flw thrugh main input devices M. fter the scillatr reaches steady-state scillatin at mde v ctl can then be brught t a higher value t activate the auxiliary pair and shift up the scillatin frequency. The half-circuit equivalent f the ring scillatr is shwn in Fig.. The ring scillatr can be regarded as a main delay path frmed with main input devices plus an additinal delay path cnstructed by auxiliary input devices. g min and g maux represent the equivalent transcnductance f the main input devices and auxiliary input devices respectively. The equivalent utput resistance and capacitance are als depicted in Fig.. Miller effect capacitances are ignred here fr simplicity. Mde : T ensure mde v ctl is set high at first. The bias current will then flw mainly thrugh auxiliary input devices M. fter the scillatr reaches stable scillatin at mde v ctl can be brught t a lwer value t decrease the scillatin frequency. s shwn in Fig. the ring scillatr perating at mde can als be regarded as a main delay path plus an 8b Fig. The rearranged diagram f Fig.. 5b 5b 8 6 b 5b 7b b 8 b b 8b b b b 7 5 6 b 5 b 8b Fig. 5 Phase relatin f each utput nde. Mde. Mde. b Mrever small-signal linear apprximatin prvides an alternative way t bserve the tw scillatin mdes f the ring scillatr. With the aid f Fig. the nrmalized rt lcus f the ring scillatr at mde and mde are drawn in Fig. 6 and respectively. Parameters were extracted frm HSPICE simulatins at the bias pint. Fig. 6 shws the rt lcus f mde where v ctl is initially set lw (black dts. s predicted the pair f ples f mde lies at the right-half plane. Thus the signal f mde will build up and reach steady-state scillatin. Further by increasing v ctl the lcatin f the ples f mde changes (gray dts. This indicates a change in bth the amplitude and scillatin frequency f mde signal. questin then ccurs. While further rising v ctl the pair f ples f mde enters the right-half plane. It is evident that there is a perid in which tw pairs f ples lie at the right-half plane. The prblem f whether mde signal will build up and dminate the ring scillatr r the ring scillatr remains perating at mde becmes ambiguus. On the ther hand Fig. 6 depicts the rt lcus f mde where v ctl is initially set high (black dts. In this case the pair f ples f mde lies at the right-half plane. s previusly mentined the same questin arises when bringing v ctl t a lwer value. The pair f ples f mde will enter the
> ccepted fr publicatin in IEEE TCS - II < right-half plane (gray dts. T determine whether the ring scillatr will remain at the same mde r shift t the ther mde requires nnlinear analysis because linear mdel pssess superpsitin feature which allws bth mdes t sustain and scillate simultaneusly. Hwever simultaneus scillatin has nt been bserved within the presented ring scillatr. Simulatin results indicate that nly ne f the tw mdes remains while the ther dies away. In the fllwing sectin a nnlinear mdel is intrduced. nalytical derivatins explain the circumstances which cause ne mde t shift t the ther as well as the cnditins in which the scillatr remains at its initial mde. Im. - -. M M Im - - - e Fig. 6 t lcus. Mde. Mde.. - -. III. NONLINE NLYSIS M M - - - e. Derivatin f Mde Equatins In rder t investigate the transient and steady-state behavirs f the tw scillatin mdes we cnsider ne f the delay stages in half-circuit representatin as shwn in Fig. 7. v in and v aux are the differential input signals f main input device and auxiliary input device. v ut is the utput signal. v in and v aux are the utput signals f the successive main input device and auxiliary input device. C L C Maux and C Min represent the utput lading capacitance and Miller effect capacitances respectively. It is assumed that the differential signals can be expressed as sinusidal signals [][] and because tw scillatin mdes are predicted the vltage signal f each nde is given as v = v + v x x m x m = cs ( ω t + + cs ( ω t + ( m m x m m m x m where m m ω m and ω m are the amplitude and scillatin frequency f mde and mde respectively. xm and xm are cnstant phases f the tw mdes at nde x and the values can be fund with aid f Fig. 5. Subscript x = in aux in aux and ut. The differential equatin f the delay stage can be frmed as dv ( aux vut dv ( in vut i + i + C + C in aux Maux Min dt dt dv ( ut dv ( ut vaux dv ( ut vin vut = C + C + C + L Maux Min dt dt dt ( i in and i aux are the differential utput currents f the main input device and auxiliary input device. Frm [] fr CMOS differential pairs the differential utput current i d can be btained as ISS id = kvid vid ( k where v id is the differential input signal k = (/μ n C x (W/L and I SS represents the tail current f the differential pair. The Taylr expansin f ( is i = α v + α v +... ( d id id in which k α = ki and α = α. (5 I SS SS in I I Main C Min aux C Maux ux I C L C Min C Maux ut in aux Fig. 7 Half-circuit representatin f ne delay stage. Nte because f the differential structure there are n even pwer terms in (. T prvide intuitive analysis nly pwer series up t the rd pwer term is cnsidered. The simplificatin retains the essence and ffers mre insight f the effect f nnlinear vltage-t-current functins and the behavir f the scillatr. Substitute ( int ( the utput current f main input device and auxiliary input device can be derived as i = y α +α + v + α +α + v y y m m ym y y m m ym In the abve equatin subscript y is equal t in and aux. The influences f higher-rder harmnic terms are assumed t be small and can be neglected [8][9]. By applying ( and (6 int ( and let utm = utm = with sme mathematical manipulatins we arrive at differential equatins fr the amplitudes f the tw mdes ( ( ( in cs aux cs d( m α +α m = dt Km + m m ( in cs( aux cs( + α +α ( ( ( in cs aux cs d( m α +α m =. dt Km. ( ( ( + m + m cs +αaux cs (6 (7 nd the scillatin frequencies f the tw mdes can be expressed as ( aux sin in m ( aux m m m ( ( inm ( aux m sin +α ω = m K m + + sin +αaux sin
> ccepted fr publicatin in IEEE TCS - II < ( aux sin( sin +α in m aux m ω =. m K m + m + m ( sin inm +αaux sinaux m (8 K i is defined as ( in ( ( ( C C L Min cs cs + i in i Ki =. C + Maux cs cs aux i aux i Fr i = m and m. The square f the steady-state amplitude at mde alne ( m = and the square f the steady-state amplitude at mde alne ( m = can be btained as ( frm (7 by setting d( m / dt = and d( m / dt = respectively. cs +αaux cs = m α cs +α cs m ( aux ( in cs +αaux cs =. α cs +α ( aux cs ( in (9 ( B. Stability analysis The stability f the ring scillatr can be determined by intrducing a small perturbatin f amplitude arund the statinary pint and evaluating the prperties f (7 in respnse t this disturbance. T this end the Jacbean matrix f the amplitude equatins (7 is frmed and the eigenvalues are evaluated fr each f the fur equilibrium states: State : Zer state where m = and m =. It can be shwn that if cs +αaux cs > r cs +αaux cs > ( the zer state will be unstable. These are als the criteria fr each scillatin mde t build up. State : Oscillatin at mde where m and m =. Fr steady-state scillatin at mde the cnditins t be satisfied are cs +αaux cs > α cs +αaux cs in > = m m cs +αaux cs. ( State : Oscillatin at mde where m = and m. Similarly the cnditins required fr steady-state scillatin at mde are cs +αaux cs > α cs +αaux cs in > = m m cs +αaux cs.( State : Simultaneus scillatin at mde and mde where m and m. Expressins f amplitudes f the tw mdes fr this equilibrium state can als be derived frm (7. Hwever the eigenvalues f the Jacbean matrix evaluated frm this state have psitive signs and this indicates the ring scillatr des nt generate simultaneus scillatin. Figure 8 depicts the phase prtrait frmed frm (7 the unit f the axis is in amplitude instead f the square f amplitude fr clarity. Figure 8 shws the case when bth ( and m < m < m are satisfied. mng the fur equilibrium states the zer state and simultaneus scillatin state are unstable. s fr the ther tw equilibrium states the ring scillatr can retain steady-state scillatin. Fig. 8 depicts the case when bth cnditins ( and m > m are meet. s predicted in ( when m > m mde becmes unstable and the nly stable state is scillatin at mde. The black and gray dts crrespnd t the maximum and minimum amplitudes f each mde. Therefre by using the derived equatins the frequency range f the tw mdes can be calculated. Fr mde applying (5 and ( t the secnd cnstraint given in ( a maximum I required fr scillatin in mde can be derived. Since larger I attains higher frequency the maximum frequency can be fund with the aid f (8. On the ther hand because smaller I des nt break the cnstraints in ( the lwest frequency can be btained by (8 and the minimum available I which is arund. m in ur design. The frequency range f mde can als be calculated in a similar way. m (.5..........5 m ( m (.5..........5 m ( Fig. 8 Phase prtrait. m < m < m. m > m. I. SIMULTION ESULTS T determine the validity f the equatins derived in sectin III the scillatin frequency amplitude and criteria f scillatin are calculated using (8 ( ( and ( and are cmpared with thse btained frm the behavir simulatins and circuit level simulatins respectively. The behaviral mdel was created in erilg- using delay stages as shwn in Fig. 7. Nnlinear current functins are frmed frm ( and pwer series up t the rd pwer term are cnsidered. Parameters I SS k C L C Min C Maux and are extracted frm transistr-level simulatins in HSPICE based n a CMOS.8-μm technlgy with DD =.8. In rder t test the criterin f scillatin tw simulatin methdlgies are designed. The first ne is designed t cntrl the scillatr t initially start scillating at mde. This is dne by setting v ctl t which makes I I I ttal and I m. fter the scillatr reaches steady-state scillatin at mde then v ctl is adjust t v final. The prcess f tail current adjustment via v ctl is shwn in Fig. 9. v final is swept frm
> ccepted fr publicatin in IEEE TCS - II < 5 t DD. cmparisn f the calculatin results with erilg- and HSPICE simulatin results is shwn in Fig.. The black and gray dts represent scillatin at mde and mde respectively. In Fig. the scillatr initially scillates at mde. By rising v ctl t v final I increases and I I decreases. This tuning is equivalent t increasing ( m / m. s v final is swept t the vltage level where ( m / m > scillatin at mde n lnger sustains and the scillatr shifts t mde. Similarly the secnd simulatin methdlgy is t cntrl the scillatr t initially start scillating at mde. This is dne by setting v ctl t DD which makes I I m and I I ttal. fter the scillatr reaches steady-state scillatin at mde then v ctl is adjust t v final. The prcess f tail current adjustment fr this case is shwn in Fig. 9. The final value v final is nw swept frm DD t. The results are pltted in Fig.. In Fig. the scillatr initially scillates at mde. By bringing v ctl lwer I I increases and I decreases s that ( m / m increases. s the perating pint ( m / m > is reached scillatin at mde n lnger sustains and the scillatr shifts t mde. Nte the full range f I I is frm. m t.8 m. We demnstrated the regin. m t.5 m here t emphasize n the transitins frm mde t mde and mde t mde respectively. The simulated frequency bands are frm ~ 5 GHz and frm. ~ GHz fr mde and mde respectively. s shwn the calculated values using (8 ( ( and ( clsely match with the results f the behavir simulatins as well as the circuit level simulatins. This assures the validity f the assumptin f representing nde vltage as sinusidal signals and neglect f higher harmnics in the current functins. The simplificatin f pwer series up t the rd pwer term is als feasible.. I ttal = I I + I. I ttal = I I + I.6 I I.6 I...8.8. I. I I Mde Time (Sec Mde Time (Sec Fig. 9 Mde startup cntrl. Mde startup cntrl. I (m mplitude ( Frequency (GHz.5... 6 I (m Calculatin erilg- Sim. HSPICE Sim.....5.6.7.8.9. I I (m....5.6.7.8.9. I I (m m > m (Cal. m < m (Cal. mplitude ( Frequency (GHz.5... 6 Calculatin erilg- Sim. HSPICE Sim.....5.6.7.8.9. I I (m....5.6.7.8.9. I I (m m < m (Cal. m > m (Cal. Fig. Oscillatin mde simulatin. Startup frm Mde. Startup frm Mde. (Black dts are scillatin at mde. Gray dts are scillatin at mde.. CONCLUSIONS The study f a dual-mde ring scillatr in a CMOS.8-μm technlgy is presented. startup circuit is designed t cntrl the scillatr t prperly perate in either f the tw mdes. nalytical derivatins which include the expressins f scillatin frequency amplitude and criterin f scillatin prvide full insight int the behavir f the dual-mde ring scillatr. transistr-level ring scillatr circuit is built and simulated in HSPICE. Simulatin results shw cnsistency with the analytical derivatins. EFEENCES [] T. iley and J. Kstamvaara " Hybrid ΔΣ Fractinal-N Frequency Synthesizer" IEEE Trans. Circuits Syst. II vl. 5 pp. 76 8 pr.. [] D. Y. Jeng et al. CMOS Current-Cntrlled Oscillatrs Using Multiple-Feedback Lp ing rchitectures in IEEE ISSCC Dig. Tech. Papers Feb. 997 pp. 86 87. [] S. J. Lee B. Kim and K. Lee Nvel High-Speed ing Oscillatr fr Multi-phase Clck Generatin Using Negative Skewed-Delay Scheme IEEE J. Slid-State Circuits vl. pp. 89 9 Feb. 997. [] L. Sun and T.. Kwasniewski.5-GHz.5-μm Mnlithic CMOS PLL Based n a Multiphase ing Oscillatr IEEE J. Slid-State Circuits vl. 6 pp. 9 96 Jun.. [5] Y.. Eken and J. P. Uyemura 5.9-GHz ltage-cntrlled ing Oscillatr in.8-μm CMOS IEEE J. Slid-State Circuits vl. 9 pp. Jan.. [6] S. S. Mhan et al. Differential ing Oscillatrs with Multipath Delay Stages in Prc. IEEE Custm Integrated Circuits Cnf. (CICC Sep. 5 pp. 5 56. [7] C.-Y. Yang C.-H. Chang and W.-G. Wng Δ-Σ PLL-Based Spread-Spectrum Clck Generatr with a Ditherless Fractinal Tplgy IEEE Trans. Circuits Syst. I vl. 56 pp. 5 59 Jan. 9. [8] B. van der Pl On Oscillatin Hysteresis in a Tride Generatr with Tw Degrees f Freedm Philsph. Mag. vl. pp. 7 79 pr. 9. [9]. Gel and H. Hashemi Frequency Switching in Dual-esnance Oscillatrs IEEE J. Slid-State Circuits vl. pp. 57 58 March 7. [] S. Dcking and M. Sachdev Methd t Derive an Equatin fr the Oscillatin Frequency f a ing Oscillatr IEEE Trans. Circuits Syst. I vl. 5 pp. 59 6 Feb.. [] P. M. Farahabadi et al. Clsed-Frm nalytical Equatins fr mplitude and Frequency f High-Frequency CMOS ing Oscillatrs IEEE Trans. Circuits Syst. I vl. 56 pp. 669 677 Dec. 9. [] B. azavi Design f nalg CMOS Integrated Circuits. New Yrk: McGraw-Hill ch..