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Built-In Self-Test Outline Motivation for BIST Testing SoC with BIST Test per Scan and Test per Clock HW and SW based BIST Exhaustive and pseudoexhaustive test generation Pseudorandom test generation with LFSR Hybrid BIST Response compaction methods Signature analyzers

Testing Challenges: SoC Test Cores have to be tested on chip Source: Elcoteq Source: Intel

Self-Test in Complex Digital Systems Source SoC Test Access Mechanism SRAM CPU MPEG Peripheral Component Interconnect Wrapper Core Under Test UDL SRAM ROM DRAM Test Access Mechanism Sink Test architecture components: Test pattern source & sink Test Access Mechanism Core test wrapper Solutions: Off-chip solution need for external ATE Combined solution mostly on-chip, ATE needed for control On-chip solution BIST

Self-Test in Complex Digital Systems SoC SRAM CPUSource MPEG Peripheral Component Interconnect Wrapper Core Under Test UDL Sink SRAM ROM DRAM Test architecture components: Test pattern source & sink Test Access Mechanism Core test wrapper Solutions: Off-chip solution need for external ATE Combined solution mostly on-chip, ATE needed for control On-chip solution BIST

What is BIST On circuit Test pattern generation Response verification Random pattern generation, very long tests Response compression IC BIST Control Unit Test Pattern Generation (TPG) Circuitry Under Test CUT Test Response Analysis (TRA)

SoC BIST Optimization: Embedded Tester Test Controller Core BIST Test access mechanism - testing time Core 2 - memory cost - power consumption BIST - hardware cost - test quality Tester Memory BIST BIST BIST Core 3 Core 4 Core 5 System on Chip

Built-In Self-Test Motivations for BIST: Need for a cost-efficient testing (general motivation) Doubts about the stuck-at fault model Increasing difficulties with TPG (Test Pattern Generation) Growing volume of test pattern data Cost of ATE (Automatic Test Equipment) Test application time Gap between tester and UUT (Unit Under Test) speeds Drawbacks of BIST: Additional pins and silicon area needed Decreased reliability due to increased silicon area Performance impact due to additional circuitry Additional design time and cost

BIST in Maintenance and Repair Useful for field test and diagnosis (less expensive than a local automatic test equipment) To overcome the disadvantages of software tests for field test and diagnosis (nonbist): Low hardware fault coverage Low diagnostic resolution Slow to operate Hardware BIST benefits: Lower system test effort Improved system maintenance and repair Improved component repair Better diagnosis Possibility to use the functionality of microprocessors

BIST techniques are classified: BIST Techniques on-line BIST - includes concurrent and nonconcurrent techniques off-line BIST - includes functional and structural approaches On-line BIST - testing occurs during normal functional operation Concurrent on-line BIST - testing occurs simultaneously with normal operation mode, usually coding techniques or duplication and comparison are used Nonconcurrent on-line BIST - testing is carried out while a system is in an idle state, often by executing diagnostic software or firmware routines Off-line BIST - system is not in its normal working mode, usually on-chip test generators and output response analyzers or microdiagnostic routines Functional off-line BIST is based on a functional description of the Component Under Test (CUT) and uses functional high-level fault models Structural off-line BIST is based on the structure of the CUT and uses structural fault models (e.g. SAF)

General Architecture of BIST BIST Control Unit Test Pattern Generation (TPG) Circuitry Under Test CUT Test Response Analysis (TRA) BIST components: Test pattern generator (TPG) Test response analyzer (TRA) TPG & TRA are usually implemented as linear feedback shift registers (LFSR) Two widespread schemes: test-per-scan test-per-clock

Detailed BIST Architecture Source: VLSI Test: Bushnell-Agrawal

BIST: Test Generation Methods Universal test sets. Exhaustive test (trivial test) 2. Pseudo-exhaustive test Properties of exhaustive tests. Advantages (concerning the stuck at fault model): - test pattern generation is not needed - fault simulation is not needed - no need for a fault model - redundancy problem is eliminated - single and multiple stuck-at fault coverage is 00% - easily generated on-line by hardware 2. Shortcomings: - long test length (2 n patterns are needed, n - is the number of inputs) - CMOS stuck-open fault problem

Exhaustive and Pseudo-Exhaustive Testing Exhaustive combinational fault model: - exhaustive test patterns - pseudoexhaustive test patterns - exhaustive output line oriented test patterns - exhaustive module oriented test patterns

BIST: Pseudoexhaustive Testing Pseudo-exhaustive test sets: Output function verification maximal parallel testability partial parallel testability Module function verification Module Under Test Primitive polynomials Output function verification 4 4 F 4 4 00 00 F & 2 6 = 65536 Exhaustive test >> 4x6 = 64 Pseudoexhaustive sequential > 6 Pseudoexhaustive parallel Subcircuits for internal signal propagation

Testing ripple-carry adder Output function verification (maximum parallelity) Exhaustive test generation for n-bit adder: Good news: Bit number n - arbitrary Test length - always 8 (!) Bad news: The method is correct only for ripple-carry adder c 0 a 0 b 0 c a b c 2 a 2 b 2 c 3 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 4 0 0 0 0 5 0 0 0 0 0 0 6 0 0 0 7 0 0 0 8 0-bit testing -bit testing 2-bit testing 3-bit testing etc

Pseudo-Exhaustive Test for Multiplier Multiplier array a 3 a 2 a a 0 + & + & + & b 0 = 0 + & + & + & b = c 4 + & c 3 + & c 2 + & b 2 = Multiplication with traditional paper and pencil method + s 5 & + s 4 & + s 3 & s 2 s = a 0 s 0 = 0 b 3 = 0

Pseudo-Exhaustive Test for Multiplier Replication of columns with pseudo-exhaustive patterns for Multiplier Adder No carry multiplier array 4-bit 3-bit 2-bit -bit 0-bit a 4 b 4 c 4 a 3 b 3 c 3 a 2 b 2 c 2 a b c a 0 b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 6 0 0 0 0 7 0 0 0 0 8 N 6-bit 5-bit 4-bit 3-bit 2-bit -bit 0-bit c 6 a 7 a 6 c 5 a 6 a 5 c 4 a 5 a 4 c 3 a 4 a 3 c 2 a 3 a 2 c a 2 a a a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 6 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Exhaustively Self-Testing Multiplier BIST Built-in Self-Test Multiplicand operands: Shifted 000000 000000 000000 Multiplier operands: Generated with FSM and replicated 5-bit patterns Test length: (n-)

Pseudoexhaustive Test Optimization Simple iterative algorithm: Output function verification (partial parallelism) F 00-0 000 F 3 F 2 000 F 4 000 F 5 x x 2 x 3 x 4 F (x, x 2 ) F 2 (x, x 3 ) F 3 (x 2, x 3 ) F 4 (x 2, x 4 ) F 5 (x, x 4 ) F 6 (x 3, x 4 ) Exhaustive testing - 6 Pseudo-exhaustive, full parallel 4 (not possible) Pseudo-exhaustive, partially parallel - 6

Combined Pseudo-Exhaustive-Random Testing Pseudo- Random Test PE4 PE2 PE3 K K2 K3 K4 Segmented LFSR Combined PE-PR Test Circuit with 4 cones A set of Partial Pseudo-Exhaustive tests can be combined with () Pseudorandom BIST or (2) Stored Deterministic test set

Problems with Exhaustive Testing Problem: Sequential fault class - Transistor Level Stuck-off Faults NOR gate test: x V DD Stuck-off (open) x V DD x x 2 y y d 0 0 0 0 0 0 0 Y x 2 x 2 Y Y x x 2 x x 2 V SS V SS No conducting path from V DD to V SS for 0 0 0 Test sequence is needed: 00,0

Problems with Exhaustive Testing Problem: Sequential fault class - Bridging Fault Sequentiality A short will change the circuit into sequential one, and you will need because of that 2 4 = 6 input patterns Instead of 2 3 = 8 Y = F(x, x 2, x 3 ) Bridging fault State q y 0 x x 2 x 3 & & Y = F(x, x 2, x 3,q)

Built-In Self-Test Test pattern generator BIST Control Test response analysator Test per Scan: Scan Path Scan Path... Scan Path CUT Initial test set: T: 00 T2: 00 T3: 00 T4: 00 Assumes existing scan architecture Drawback: Long test application time Test application: 00 T 00 T 00T 00 T Number of clocks = (4 x 4) + 4 = 20

Built-In Self-Test Test per Clock: Combinational Circuit Under Test Initial test set: T: 00 T2: 00 T3: 00 T4: 00 Assume, this is the full test sequence needed Test application: Scan-Path Register 0 0 0 0 0 0 00 T T 4 T 3 T 2 Number of clocks = 8 < 20

Pattern Generation Store in ROM too expensive Exhaustive too long Pseudo-exhaustive preferred Pseudo-random (LFSR) preferred Binary counters use more hardware than LFSR Modified counters Test pattern augmentation ( Hybrid BIST) LFSR combined with a few patterns in ROM LFSR with bit flipping LFSR with bit fixing

LFSR Based Testing: Some Definitions Exhaustive testing Apply all possible 2 n patterns to a circuit with n inputs Pseudo-exhaustive testing Break circuit into small, overlapping blocks and test each exhaustively Pseudo-random testing Algorithmic pattern generator that produces a subset of all possible tests with most of the properties of randomly-generated patterns LFSR Linear feedback shift register, hardware that generates pseudo-random pattern sequence BILBO Built-in logic block observer, extra hardware added to flip-flops so they can be reconfigured as an LFSR pattern generator or response compacter, a scan chain, or as flip-flops

Pattern Generation Pseudorandom test generation by LFSR: Xo X... ho h hn... LFSR CUT LFSR Xn Using special LFSR registers Test pattern generator Signature analyzer Several proposals: BILBO CSTP Main characteristics of LFSR: polynomial initial state test length

Pseudorandom Test Generation LFSR Linear Feedback Shift Register: Standard LFSR x x 2 x 3 x 4 Modular LFSR x x 2 x 3 x 4 Polynomial: P(x) = x 4 + x 3 +

Pseudorandom Test Generation LFSR Linear Feedback Shift Register: Why modular LFSR is useful for BIST? x x 2 x 3 x 4 UUT Test responses Test patterns Polynomial: P(x) = x 4 + x 3 +

Problems with BIST: Hard to Test Faults The main motivations of using random patterns are: - low generation cost - high initial efeciency Problem: Low fault coverage Pseudorandom Patterns from LFSR: test window: 2 n - Fault Coverage Hard to test faults Start (seed) Finish Dream solution: Find LFSR such that: 2 n - Time Hard to test faults

Pseudorandom Test Generation Scan-based BIST Bit-flipping BIST H.-J. Wunderlich, G. Kiefer. Bit flipping BIST. Proc. ICCAD, Nov. 996, pp.337-343.

Pseudorandom Test Generation Bit-fixing BIST N.A. Touba, E.J. McCluskey. Bit-fixing in pseudorandom sequences for scan BIST. IEEE Trans. on CAD of IC and Systems, Vol.20, No.4, Apr.200.

Pseudorandom Test Generation LFSR Linear Feedback Shift Register: Why modular LFSR is useful for BIST? x x 2 x 3 x 4 UUT Test responses Test patterns Polynomial: P(x) = x 4 + x 3 +

BILBO BIST Architecture Working modes: B B2 0 0 Normal mode 0 Reset 0 Test mode Scan mode Testing modes: CC: LFSR - TPG LFSR 2 - SA CC2: LFSR 2 - TPG LFSR - SA B B2 B B2 LFSR CC LFSR 2 CC2

BILBO BIST Architecture Working modes: B B2 0 0 Normal mode 0 Reset 0 Test mode Scan mode Testing modes: CC, CC2 Tested in parallel: B B2 B B2 LFSR CC LFSR 2 LFSR LFSR 2 TPG, SA CC2

Reconfiguration of the LFSR Unit Under Test LFSR FEEDBACK MUX Normal & Reset From & & T i- T i Test & OR T i+ Scan & To T i+2 Signature analyzer mode B B2 0 2 3 MUX 4 working modes

Pseudorandom Test Generation - LFSR Shift x x 2 x 3 x 4 Two approaches to LFSR simulation: Polynomial: P(x) = x 4 + x 3 + t x x 2 x 3 x 4 t x x 2 x 3 x 4 Matrix calculation: 0 0 0 9 0 0 X 4 (t + ) X 3 (t + ) X 2 (t + ) X (t + ) = 0 0 0 0 0 h 3 0 0 h 2 0 0 h 0 0 X 4 (t) X 3 (t) X 2 (t) X (t) = Feedback X 3 X 2 X X 4 X 3 2 0 0 0 0 0 0 3 0 0 0 0 4 0 0 0 2 0 5 0 0 3 6 0 0 4 0 7 0 0 5 0 0 8 0 6 0 0 0

Matrix Equation for Standard LFSR X n (t + ) X n- (t + ). X 3 (t + ) X 2 (t + ) X (t + ) = 0 0... 0 0 0... 0 0 h n- 0... 0 0 h n-2 0 0... 0 h 2 0 0... 0 h X n (t) X n- (t). X 3 (t) X 2 (t) X (t) X (t + ) = T s X (t) (T s is companion matrix) x x 2 x n- x n

Theory of LFSR: Primitive Polynomials Properties of Polynomials: Irreducible polynomial cannot be factored, is divisible only by itself Any polynomial with all even exponents can be factored and hence is reducible Irreducible polynomial of degree n is characterized by: An odd number of terms including term Divisibility into x k +, where k = 2 n An irreducible polynomial of degree n is primitive if it divides the polynomial x k + for k = 2 n, but not for any smaller positive integer k x 3 x x 7 + 2

Theory of LFSR: Examples Polynomials of degree n=3 (examples): k = 2 n = 2 3 =7 Primitive polynomials: x x 3 3 x 2 x The polynomials will divide evenly the polynomial x 7 + but not any one of k<7, hence, they are primitive They are also reciprocal: coefficients are 0 and 0 Reducible polynomials (non-primitive): Primitive polynomial x x 3 3 x 2 ( x )( x x 2 x ) ( x )( x 2 )

Theory of LFSR: Examples Is x 4 x 2 a primitive polynomial? Irreducible polynomial of degree n is characterized by: x 4 - An odd number of terms including term? Yes, it includes 3 terms - Divisibility into + x k, where k = 2 n x No, there is remainder 2 is non-primitive? x 4 Divisibility check: x 2 x x x x x x x x x x 5 5 3 3 9 9 7 7 3 x 9 x x x x x x 7 5 5 3 x x x x x 5 5 3 9 x 3

Theory of LFSR: Examples Simulation of the behaviour of LFSR by polynomial: Primitive polynomials x 3 x 00 0 0 0 00 00 00 x x 2 x 3

Theory of LFSR: Examples Comparison of test sequences generated: Primitive polynomials Non-primitive polynomials 3 3 2 3 3 2 x x x x x x x x 00 0 0 0 00 00 00 00 00 0 0 0 00 00 00 00 00 00 00 00 00 00 00 0 0 00 00 0 0 00

Theory of LFSR: Examples Non-primitive polynomial x 4 + x 2 + Primitive polynomial x 4 + x + x x 2 x 3 x 4 x x 2 x 3 x 4 000 000 000 00 00 000 000 00 00 0 0 00 00 00 0 0 00 000 000 00 0 0 0 00 00 0 00 00 00 000 000 000

Theory of LFSR: Examples Primitive polynomial x 4 + x + x x 2 x 3 x 4 Zero generation: x x 2 x 3 x 4 000 000 00 0 0 0 00 00 0 00 00 00 000 000 000 The code 0000 is missing 0000 000 00 0 0 0 00 00 0 00 00 00 000 000 000 0000

Pseudorandom Testing with LFSR Primitive polynomial x 4 + x + For testing the fault x 2 the test patterns 000, 00 and 00 can be used x x 2 x 3 x 4 000 000 00 0 0 0 00 00 0 00 00 00 000 000 000 0 (-) - (0) 0 x x 2 x 3 x 4 x 2 x 22 0 & & a b y

Pseudorandom Testing with LFSR Non-primitive polynomial x 4 + x 2 + For testing the fault x 2 the test patterns 000, 00 and 00 can be used x x 2 x 3 x 4 000 000 000 00 00 000 000 00 00 0 0 00 00 00 0 0 00 x x 2 x 3 x 4 0-0 (-) (0) Be careful: no proper patterns can be generated using the seed 00 x x 2 x 3 x 4 x 2 x 22 0 0 0 & & a b y

Theory of LFSR: Primitive Polynomials Number of primitive polynomials of degree N N No 2 4 2 8 6 6 2048 32 6708864 Table of primitive polynomials up to degree 3 N Primitive Polynomials,2,3,4,6,7,5,22 + X + X n 5,, 2, 29 + X 2 + X n 0,7,20,25,28,3 + X 3 + X n 9 + X 4 + X n 23 + X 5 + X n 8 + X 7 + X n 8 + X 2 + X 3 + X 4 + X n 2 + X + X 3 + X 4 + X n 3 + X + X 4 + X 6 + X n 4, 6 + X + X 3 + X 4 + X n

Theory of LFSR: Primitive Polynomials Examples of PP (exponents of terms): n other n other 0 9 4 0 2 0 0 3 0 3 0 2 0 4 0 2 7 4 3 0 5 2 0 3 4 3 0 6 0 4 2 0 7 0 5 0 8 6 5 0 6 5 3 2 0 x 3 + x + x 3 + x 4 + x 3 + x +

BIST: Fault Coverage Pseudorandom Test generation by LFSR: Motivation of using LFSR: - low generation cost - high initial efeciency BIST Control Unit Test Pattern Generation (TPG) Circuitry Under Test CUT Fault Coverage Test Response Analysis (TRA) Drawback: 00% fault coverage is difficult to achieve Time

BIST: Fault Coverage Pseudorandom Test generation by LFSR: Motivation of using LFSR: Fault Coverage - low generation cost - high initial efeciency Reasons of the high initial efficiency: A circuit may implement n 2 2 functions A test vector partitions the functions into 2 equal sized equivalence classes (correct circuit in one of them) The second vector partitions into 4 classes etc. After m patterns the fraction of functions distinguished from the correct function is 2 m n 2 i 2 2 n i, n m 2 Time

... Raimund Ubar Fault Coverage: Functional View Why we need 2 64 patterns 2 64 Fault coverage 00% Number of patterns 2 m n 2 i 2 2 n n m 2 i Test quality:, First pattern 00% 0% 93,75% 4. 3. Second pattern 87,5% 75% 50%

BIST: Fault Coverage # all functions Explanation of the formula of fault coverage: ) General case: 2 m n 2 i 2 2 n i 2) Example: n = 2, m =, i = : 2 i, n m 2 3 2 5 2 2 2 2 2 n number of inputs, m number of test patterns, i share of each pattern # tested functions 8 5 00% will be reached only after 2 n test patterns Faulty functions covered by. pattern 00% 0% 50% 4. pat. 87,5% 3. pattern Faulty functions covered by 2. pattern 93,75% 75%

BIST: Structural Approach to Test Deterministic test approach: Testing of structural faults: 2 n Combinational circuit under test Not tested faults 3. patttern 4. pat. 2. pattern Faults covered by. pattern 00% Fault coverage Number of patterns 4

BIST: Two Approaches to Test Testing of functions: 00% 0% 93,75% 4. pat. 87,5% Deterministic test approach: Testing of faults: Not tested faults 3. patttern 4. pat. 2. pattern 00% will be reached only after 2 n test patterns Faulty functions covered by. pattern 50% 3. pattern Faulty functions covered by 2. pattern 75% Testing of faults 00% Testing of functions Faults covered by. pattern 00% will be reached when all faults from the fault list are covered

Problems with BIST: Hard to Test Faults The main motivations of using random patterns are: - low generation cost - high initial efeciency Problem: Low fault coverage Pseudorandom Patterns from LFSR: test window: 2 n - Hard to test faults Fault Coverage Dream solution: Find LFSR such that: 2 n - Time Hard to test faults

Deterministic Scan-Path Test Test per Clock: Combinational Circuit Under Test Initial test set: T: 00 T2: 00 T3: 00 T4: 00 Test application: Scan-Path Register 0 0 0 0 0 0 00 T T 4 T 3 T 2 Number of clocks = 8 < 20

Deterministic Synthesis of LFSR Generation of the polynomial and seed for the given test sequence ) Given test sequence: () 00x0 (2) x00 (3) 00 (4) 0 2) Creation of the shortest bit-stream: 000 0 0 Seed States of the LFSR This deterministic test set is generated by ATPG However, only patterns which detects the hard-totest faults can be chosen 3) Expected shortest LFSR sequence: 0 (4) 0 0 0 00 (3) 0 00 (2) 0 00 000 () Shift LFSR

Deterministic Synthesis of LFSR Generation of the polynomial and seed for the given test sequence System of linear equations: a k x b k x 2 c k x 3 d k x 4 e k x 5 =f k Expected shortest LFSR sequence: 0 (4) 0 0 0 00 (3) 0 00 (2) 0 00 000 () Currrent state of the LFSR k=,2 6 j=,2,,,5 f k a k b k c k d k e k 0 0 00 00 000 000 k x x x 2 x 3 x 4 x 5 : x x 2 x 3 x 4 x5 x x 2 x 3 x 4 x 5 = 0 0 0 We are looking for the values of x i x j j f k k Next input signal into LFSR

Deterministic Synthesis of LFSR 2 3 4 5 6 Generation of the polynomial and seed for the given test sequence System of linear equations: 0 0 00 00 000 000 x x x 2 x 3 x 4 x 5 = 0 0 0 Solving the equation by Gaussian elimination with swapping of rows Rows:,2,4,6 4,6,3 2,4,3,6 a k x b k x 2 c k x 3 d k x 4 e k x 5 = f k, k=,2,..,6 Results: 0000 0000 0000 0000 0000 0000 x x x 2 x 3 x 4 x 5 = f k 0 0 0 f 2 f 3 k=2 (4) 00 0 (6) 000 (4 6) 0000 k=3 () 0 (3) 00 ( 3) 0000 0 4) Solution: x x 2 x 3 x 4 x 5 0 0 0

Deterministic Synthesis of LFSR Embedding deterministic test patterns into LFSR sequence: 4) Solution: x x 2 x 3 x 4 x 5 0 0 0 LFSR sequence: 5) Polynomial: x 5 + x + Seed: 0 x x x 2 x 3 x 4 x 5 Given deterministic test sequence: () 00x0 (2) x00 (3) 00 (4) 0 x5 () 0 (4) (2) 0 (3) 00 (4) 00 (3) (5) 000 (2) (6) 000 (7) 000 ()

Which Test Patterns to Select for as HTF? Frequences of fault detection For deterministic LFSR based BIST, only the patterns which detects HTFs can be chosen for the synthesis process Fault detection frequences for the given random test sequence Different faults Easily detectable faults Hard-to-test faults (HTF)

Other Problems with Pseudorandom Test The main motivations of using random patterns are: - low generation cost - high initial efeciency Problem: low fault coverage & LFSR Decoder S 0 A = S S 5 Counter A = 0 Fault Coverage Reset If Reset = signal has probability 0,5 then counter will not work and for AND gate may never be produced S 2 B = 0 B = S 3 S 4 Time

Sequential BIST A DFT technique of BIST for sequential circuits is proposed The approach proposed is based on all-branches coverage metrics which is known to be more powerful than all-statement coverage S 0 S 0 S 0 A = S S 5 A = S S 5 A = S S 5 A = 0 S 2 B = 0 B = A = 0 S 2 B = 0 B = A = 0 S 2 B = 0 B = S 3 S 4 S 3 S 4 S 3 S 4

Sequential BIST reset clock test/normal mode (TM) primary inputs masked status bits Digital System primary outputs FSM control signals Datapath observation points status signals MUX Status signals entering the control part are made controllable In the test mode we can force the UUT to traverse all the branches in the FSM state transition graph The proposed idea of architecture requires small device area overhead since a simple controller can be implemented to manipulate the control signals

Example for Sequential BIST Control Part y y 2 y 3 y 4 R IN M M 2 b a + * c d M 3 e R 2 Data Part

BIST: Different Techniques Pseudorandom Test generation by LFSR: Full identification is achieved only after 2 n input combinations have been tried out (exhaustive test) 2 m n 2 n 2 i n m 2 2 A better fault model (stuck-at-0/) may limit the number of partitions necessary, Pseudorandom testing of sequential circuits: The following rules suggested: clock-signals should not be random control signals such as reset, should be activated with low probability data signals are chosen randomly Microprocessor testing A test generator picks randomly an instruction and generates random data patterns By repeating this sequence a specified number of times it will produce a test program which will test the microprocessor by randomly exercising its logic

BIST: Weighted pseudorandom test Calculation of signal probabilities: LFSR PI PI 2 PI 3 PI 4 PI 5 PI 6 2 3 & For PI : P = 0.5 For PI 2 and PI 3 : P = 0.6 For PI 4 - PI 6 : P = 0.4 G Probability of detecting the fault at the input 3 of the gate G: ) equal probabilities (p = 0.5): P = 0.5 (0.25 + 0.25 + 0.25) 0.5 3 = = 0.5 0.75 0.25 = = 0.046 2) weighted probabilities: P = 0.85 (0.6 0.4 + 0.4 0.6 + 0.6 2 ) 0.6 3 = = 0.85 0.84 0.22 = = 0.6

BIST: Weighted pseudorandom test Hardware implementation of weight generator LFSR & & & /6 /8 /4 /2 Weight select MUX Desired weighted value Scan-IN

BIST: Weighted pseudorandom test Faults to be tested Problem: random-pattern-resistant faults Solution: weighted pseudorandom testing The probabilities of pseudorandom signals are weighted, the weights are determined by circuit analysis NCV NCV non-controlling value The more faults that must be tested through a gate input, the more the other inputs should be weighted to NCV & Propagated faults NDI G NDI I NDI - number of primary inputs for each gate determined by the back-trace cone NDI - relative measure of the number of faults to be detected through the gate I & G

BIST: Weighted pseudorandom test Faults to be tested NCV & Propagated faults R I = NDI G / NDI I R I - the desired ratio of the NCV () to the controlling value (0) for each gate input NCV - noncontrolling value The more faults that must be tested through a gate input, the more the other inputs should be weighted to NCV NDI G NDI I I & G

BIST: Weighted pseudorandom test Example: PI PI PI PI PI PI 2 3 & G R = NDI G / NDI I = 6/ = 6 R 2 = NDI G / NDI I = 6/2 = 3 R 3 = NDI G / NDI I = 6/3 = 2 More faults must be detected through the third input than through others This results in the other inputs being weighted more heavily towards NCV

BIST: Weighted pseudorandom test Calculation of signal weights: R 2 = 3 W0 2 = W 2 = 3 PI PI PI PI PI PI 2 3 R 3 = 2 W0 3 = W 3 = 2 & R = 6 W0 = W = 6 G W0 G = W G = W0, W - weights of the signals are calculated by backtracking Calculation of W0, W for inputs Function W0 IN W IN AND W0G RI WG NAND WG RI W0G OR RI W0G WG NOR RI WG W0G

BIST: Weighted pseudorandom test Calculation of signal weights: R = W0 = 6 W = R = 2 W0 = 2 W = 3 R = 3 W0 = 3 W = 2 PI PI 2 PI 3 PI 4 PI 5 PI 6 2 3 & W0 = W = 6 G W0 2 = W 2 = 3 Backtracing from all the outputs to all the inputs of the given cone Weights are calculated for all gates and inputs Function W0 I W I OR RI W0G WG NOR RI WG W0G W0 3 = W 3 = 2

BIST: Weighted pseudorandom test Calculation of signal probabilities: R = W0 = 6 W = PI R = 2 W0 = 2 W = 3 R = 3 W0 = 3 W = 2 PI 2 PI 3 PI 4 PI 5 PI 6 2 3 & G PI : W0 = 6 W = P = /7 = 0.5 PI 2 and PI 3 : W0 = 2 W = 3 P = 3/5 = 0.6 PI 4 - PI 6 : W0 = 3 W = 2 P = 2/5 = 0.4

BIST: Weighted pseudorandom test Calculation of signal probabilities: PI PI PI PI PI PI 2 3 & For PI : P = 0.5 For PI 2 and PI 3 : P = 0.6 For PI 4 - PI 6 : P = 0.4 G Probability of detecting the fault at the input 3 of the gate G: ) equal probabilities (p = 0.5): P = 0.5 (0.25 + 0.25 + 0.25) 0.5 3 = = 0.5 0.75 0.25 = = 0.046 2) weighted probabilities: P = 0.85 (0.6 0.4 + 0.4 0.6 + 0.6 2 ) 0.6 3 = = 0.85 0.84 0.22 = = 0.6

The Main BIST Problems On circuit Test pattern generation Test Pattern Generation (TPG) Response verification Random pattern generation, Very long tests Hard-to-test faults Response compression Aliasing of results IC BIST Control Unit Circuitry Under Test CUT Test Response Analysis (TRA)

Pseudorandom Test Generation LFSR Linear Feedback Shift Register: Standard LFSR x x 2 x 3 x 4 Modular LFSR x x 2 x 3 x 4 Polynomial: P(x) = x 4 + x 3 +

BIST: Signature Analysis Signature analyzer: Standard LFSR UUT x x 2 x 3 x 4 Modular LFSR Response string x x 4 x 2 Response in compacted by LFSR The content of LFSR after test is called signature x 3 Polynomial: P(x) = x 4 + x 3 +

BIST: Signature Analysis Parallel Signature Analyzer: Single Input Signature Analyser UUT x 4 x 2 x x 3 x 4 x 2 x x 3 UUT Multiple Input Signature Analyser (MISR)

Special Cases of Response Compression. Parity checking P( R) ( m i r i ) mod 2 2. One counting P( R) m i r i 3. Zero counting P( R) m i r i Test UUT r i P i- Test r i UUT Counter T

Special Cases of Response Compression 4. Transition counting r i a) Transition 0 P( R) m i 2 ( r i r i ) Test UUT T & r i- b) Transition 0 r i P( R) m i 2 ( r i r i ) Test UUT T r i- & 5. Signature analysis

Theory of LFSR The principles of CRC (Cyclic Redundancy Coding) are used in LFSR based test response compaction Coding theory treats binary strings as polynomials: Example: R = r m- r m-2 r r 0 - m-bit binary sequence (binary string) R(x) = r m- x m- + r m-2 x m-2 + + r x + r 0 - polynomial in x 00 R(x) = x 4 + x 3 + Only the coefficients are of interest, not the actual value of x However, for x = 2, R(x) is the decimal value of the bit string

Arithmetic of coefficients: Theory of LFSR - linear algebra over the field of 0 and : all integers mapped into either 0 or - mapping: representation of any integer n by remainder r resulting from the division of n by 2: n = 2m + r, r { 0, } or r = n (modulo 2) Linear - refers to the arithmetic unit (modulo-2 adder), used in CRC generator (linear, since each bit has equal weight upon the output) Examples (addition, multiplication): x 4 + x 3 + x + + x 4 + x 2 + x x 3 + x 2 + x 4 + x 3 + x + x + x 5 + x 4 + x 2 + x x 4 + x 3 + x + x 5 + x 3 + x 2 +

Theory of LFSR Characteristic Polynomials: 0 2 2 0...... ) ( m m m m m x c x c x c x c c x G Division of polynomials x x x x x x x x x x x x x x x 2 2 3 2 3 2 4 3 4 2 2 Quotient Remainder Dividend Divider

BIST: Signature Analysis Division of one polynomial P(x) by another G(x) produces a quotient polynomial Q(x), and if the division is not exact, a remainder polynomial R(x) ) ( ) ( ) ( ) ( ) ( x G x R x Q x G x P Example: ) ( ) ( 3 5 2 2 3 3 5 3 7 x x x x x x x x x x x x x G x P Remainder R(x) is used as a check word in data transmission The transmitted code consists of the message P(x) followed by the check word R(x) Upon receipt, the reverse process occurs: the message P(x) is divided by known G(x), and a mismatch between R(x) and the remainder from the division indicates an error

BIST: Signature Analysis In signature testing we mean the use of CRC encoding as the data compressor G(x) and the use of the remainder R(x) as the signature of the test response string P(x) from the UUT P( x) G( x) Q( x) R( x) G( x Signature is the CRC code word ) Example: P( x) G( x) G(x) 7 3 x x x 5 3 x x x Signature 0 = Q(x) = x 2 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P(x) 0 0 0 = R(x) = x 3 + x 2 +

BIST: Signature Analysis G(x) 0 IN: 0 0000 P(x) P( x) G( x) 0 0 0 0 0 x x 2 x 3 x 4 x 5 G(x) 0 7 3 x x x 5 3 x x x 0 Shifted into LFSR Compressor x 5 0 0 0 0 0 0 0 0 Signature 0 x 5 x 4 x 3 x 2 x 0 0 0 0 0 0 0 0 0 Dvision process can be mechanized using LFSR Divisor polynomial G(x) is defined by the feedback connections Last shift creates x 5 which is replaced by x 5 = x 3 + x + Response P(x) 0 0 0 = R(x) = x 3 + x 2 +

BIST: Signature Analysis Aliasing: UUT Response L SA N L - test length N - number of stages in Signature Analyzer All possible responses All possible signatures L k 2 Faulty response Correct response N << L N k 2

BIST: Signature Analysis Aliasing: UUT Response L SA N L - test length N - number of stages in Signature Analyzer L k 2 - number of different possible responses No aliasing is possible for those strings with L - N leading zeros since they are represented by polynomials of degree N - that are not divisible by characteristic polynomial of LFSR 2 L N Probability of aliasing: ---- No aliasing is possible P L 2 2 N L 000000000000000... 00000 XXXXX L L P 2 N N

BIST: Signature Analysis Parallel Signature Analyzer: Single Input Signature Analyser UUT x 4 x 2 x x 3 x 4 x 2 x x 3 UUT Multiple Input Signature Analyser (MISR)

BIST: Signature Analysis Signature calculating for multiple outputs: LFSR - Test Pattern Generator LFSR - Test Pattern Generator Combinational circuit Combinational circuit Multiplexer Multiplexer LFSR - Signature analyzer LFSR - SA

BIST Architectures General Architecture of BIST BIST Control Unit Test Pattern Generation (TPG) Circuitry Under Test CUT Test Response Analysis (TRA) BIST components: Test pattern generator (TPG) Test response analyzer (TRA) BIST controller A part of a system (hardcore) must be operational to execute a self-test At minimum the hardcore usually includes power, ground, and clock circuitry Hardcore should be tested by external test equipment or it should be designed selftestable by using various forms of redundancy

BIST Architectures Test per Clock: Disjoint TPG and SA: BILBO Joint TPG and SA: CSTP - Circular Self-Test Path: LFSR - Test Pattern Generator LFSR - Test Pattern Generator & Signature analyser Combinational circuit Combinational circuit LFSR - Signature analyzer

BIST: Joining TPG and SA LFSR UUT x x 2 x 3 x 4 FF FF FF FF Response string for Signature Analysis Test Pattern (when generating tests) Signature (when analyzing test responses)

Pseudorandom Test Generation LFSR Linear Feedback Shift Register: Why modular LFSR is useful for BIST? x x 2 x 3 x 4 UUT Test responses Test patterns Polynomial: P(x) = x 4 + x 3 + Instead of BILBO we have now CSTP architecture

BIST: Circular Self-Test Architecture Circuit Under Test FF FF FF

BIST: Circular Self-Test Path CC CSTP CC CSTP CSTP CC R R CC CC CSTP CSTP

BIST Embedding Example LFSR LFSR2 M M2 CSTP M4 MUX M5 M3 BILBO Concurrent testing: MISR LFSR, CSTP M2 MISR M2 M5 MISR2 (Functional BIST) CSTP M3 CSTP LFSR2 M4 BILBO MUX MISR2 M6

Scan chain Scan chain BIST Architectures STUMPS: Self-Testing Unit Using MISR and Parallel Shift Register Sequence Generator Test Pattern Generator LOCST: LSSD On-Chip Self-Test Scan Path BS BS CUT CUT... CUT TPG SA MISR SI IC Test Controller SO Error

Scan-Based BIST Architecture PS Phase shifter Scan-Forest Scan-Trees Scan-Segments (SC) Weighted scanenables for SS Compactor - EXORs Copyright: D.Xiang 2003

Problems with BIST The main motivations of using random patterns are: - low generation cost - high initial efeciency Problems: Very long test application time Low fault coverage Area overhead Additional delay Fault Coverage Time Possible solutions Weighted pseudorandom test Combining pseudorandom test with deterministic data Multiple seed Bit flipping Hybrid BIST Fault Coverage Time

Problems with BIST: Hard to Test Faults The main motivations of using random patterns are: - low generation cost - high initial efeciency Problem: Low fault coverage Pseudorandom Patterns from LFSR: test window: 2 n - Hard to test faults Fault Coverage Dream solution: Find LFSR such that: 2 n - Time Hard to test faults

Deterministic patterns Hybrid Built-In Self-Test ROM...... BIST Controller Pseudorandom patterns PRPG... CORE UNDER TEST MISR...... SoC Core Hybrid test set contains pseudorandom and deterministic vectors Pseudorandom test is improved by a stored test set which is specially generated to target the random resistant faults Optimization problem: Where should be this breakpoint? Pseudorandom Test Determ. Test

Optimization of Hybrid BIST Cost of BIST: FAST estimation Number of remaining faults after applying k pseudorandom test patterns rnot(k) # faults Brake point min C TOTAL Total Cost C TOTAL Cost of pseudorandom test patterns C GEN Cost of stored test C MEM Number of pseudorandom test patterns applied, k Figure 2: Cost calculation for hybrid BIST Pseudorandom Test C TOTAL = k + t(k) k SLOW analysis # tests Det. Test t(k) PR test length k PR test length # faults not detected (fast analysis) # tests needed (slow analysis) k r DET (k) r NOT (k) FC(k) t(k) 55 839 5.6% 04 2 76 763 23.2% 04 3 65 698 29.8% 00 4 90 608 38.8% 0 5 44 564 43.3% 99 0 04 42 57.6% 95 20 44 3 68.7% 87 50 5 28 78.% 74 00 6 45 85.4% 52 200 8 4 88.5% 4 4 3 70 93.0% 26 954 8 28 97.2% 2 560 8 6 98.4% 7 253 5 99.5% 3 3449 2 3 99.7% 2 459 2 99.9% 4520 0 00.0% 0 How to convert #faults to #tests

Deterministic Test Length Estimation Fault coverage 00% F* F F D k ( i ) F P E k ( i ) j i Deterministic test (DT) Pseudorandom test (PT) i * Brake point search T D F k i Fast estimation for the length of deterministic test: For each PT length i* we determine - PT fault coverage F*, and - the imaginable part of DT FD k (i) to be needed for the same fault coverage Then the remaining part of DT TD E k(i) will be the estimation of the DT length T D E k ( i ) Pseudorandom test length Deterministic test length estimation

Deterministic Test Length Estimation Cost of BIST: FAST estimation Number of remaining faults after applying k pseudorandom test patterns rnot(k) # faults Brake point min C TOTAL Total Cost C TOTAL Cost of pseudorandom test patterns C GEN Cost of stored test C MEM Number of pseudorandom test patterns applied, k Figure 2: Cost calculation for hybrid BIST Pseudorandom Test C TOTAL = k + t(k) k SLOW analysis # tests Det. Test t(k) PR test length k PR test length # faults not detected (fast analysis) # tests needed (slow analysis) k r DET (k) r NOT (k) FC(k) t(k) 55 839 5.6% 04 2 76 763 23.2% 04 3 65 698 29.8% 00 4 90 608 38.8% 0 5 44 564 43.3% 99 0 04 42 57.6% 95 20 44 3 68.7% 87 50 5 28 78.% 74 00 6 45 85.4% 52 200 8 4 88.5% 4 4 3 70 93.0% 26 954 8 28 97.2% 2 560 8 6 98.4% 7 253 5 99.5% 3 3449 2 3 99.7% 2 459 2 99.9% 4520 0 00.0% 0 How to convert #faults to #tests

Calculation of the Deterministic Test Cost Two possibilities to find the length of deterministic data for each possible breakpoint in the pseudorandom test sequence: ATPG based approach For each breakpoint of P- sequence, ATPG is used Fault table based approach A deterministic test set with fault table is calculated For each breakpoint of P-sequence, the fault table is updated for not yet detected faults FAST estimation Only fault coverage is calculated ATPG based: ATPG Detected Faults All PR patterns? No Next PR pattern End Yes Fault table based: ATPG Fault table update All PR patterns? No Next PR pattern Yes End

Calculation of the Deterministic Test Cost ATPG based approach For each breakpoint of P-sequence, ATPG is used ATPG based: ATPG R R 2 R k R k+ R k+2 R n Detected Faults All PR patterns? Task for fault simulator Brake point T T 2.... T n Faults detected by pseudorandom patterns Faults to be detected by deterministic patterns No Next PR pattern End Yes Task for ATPG T n+ T p New detected faults

Calculation of the Deterministic Test Cost Fault table based approach A deterministic test set with fault table is calculated For each breakpoint of P-sequence, the fault table is updated and remaining det. patterns are determined Fault table based: R R 2 R k R k+ R k+2 R n ATPG Fault table update Task for fault simulator T T 2.... T n Faults detected By pseudorandom patterns Fault table for full deterministic test All PR patterns? No Next PR pattern Yes End Updated fault tabel T n+ T p To be detected faults

Experimental Data: HybBIST Optimization Finding optimal brakepoint in the pseudorandom sequence: Pseudorandom Test Det. Test L OPT L MAX S OPT S MAX Optimized hybrid test process: Pseudorandom Test Det. Test Circuit LMAX LOPT SMAX SOPT Bk CTOTAL C432 780 9 80 2 4 75 C499 2036 78 32 60 6 438 C880 5589 2 77 48 8 505 C355 522 2 26 52 6 433 C908 5803 05 43 23 5 720 C2670 658 444 55 77 30 2754 C3540 8734 297 2 0 7 067 C535 238 7 7 2 23 987 C6288 20 20 45 20 4 00 C7552 8704 583 267 6 5 3694

Hybrid BIST with Reseeding The motivation of using random patterns is: - low generation cost - high initial efeciency Problem: low fault coverage long PR test Pseudorandom test: 2 n - Fault Coverage Hard to test faults Solution: many seeds: Pseudorandom test: 2 n - Time

Hybrid BIST with Reseeding Using many seeds: Pseudorandom test: 2 n - Problems: Which deterministic patterns should be the seeds for the blocks?

Store-and-Generate Test Architecture # seeds ROM TPG UUT ADR Seeds RD Window Counter 2 Counter Pseudorandom test windows Seeds ROM contains deterministic data for BIST control to target hard-to-test-faults Each pattern P k in ROM serves as an initial state of the LFSR for test pattern generation (TPG) - seeds Counter counts the number of pseudorandom patterns generated starting from P k - width of the windows After finishing the cycle for Counter 2 is incremented for reading the next pattern P k+ for starting the new window CL

Store-and-Generate vs. Hybrid BIST Store and generate method (Reseeding) LFSR ROM Seed UUT Deterministic test pattern Hybrid BIST method

HBIST Optimization Problem Using many seeds: Pseudorandom test: 2 n - Seed Pseudorandom sequences: Problems: How to calculate the number and size of blocks? Which deterministic patterns should be the seeds for the blocks? Deterministic test (seeds): Seed Seed 2 Seed n L Seed 2 Seed n Block size: 00% FC Memory Constraints Minimize L at given M and 00% FC

Hybrid BIST Optimization Algorithm D-patterns are ranked ATPG patterns Pattern selection Pseudorandom sequence PR i Algorithm is based on D-patterns ranking Deterministic test patterns with 00% quality are generated by ATPG Modified ATPG pattern table FC(PR i ) Detected faults subtraction, optimization of ATPG patterns The best pattern is selected as a seed A pseudorandom block is produced and the fault table of ATPG patterns is updated The procedure ends when 00% fault coverage is achieved

Hybrid BIST Optimization Algorithm 2 P-blocks are ranked PT min Deterministic test vector (seed) DT i Pseudorandom test sequence PR i Pseudorandom sequence removed with the block length optimization PT * Algorithm is based on P-blocks ranking Deterministic test patterns with 00% quality are generated by ATPG All P-blocks are generated for all D-patterns and ranked The best P-block is selected included into sequence and updated The procedure ends when 00% fault coverage is achieved

Cost Curves for Hybrid BIST with Reseeding Two possibilities for reseeding: Constant block length (less HW overhead) Dynamic block length (more HW overhead) Test length L 0000 9000 8000 7000 6000 5000 4000 3000 2000 000 0 L(b) C908 L2(b) M(b) Memory cost M 40 0 500 000 500 2000 2500 3000 20 00 80 60 40 20 0 Block size b

Functional Self-Test Traditional BIST solutions use special hardware for pattern generation on chip, this may introduce area overhead and performance degradation New methods have been proposed which exploit specific functional units like arithmetic blocks or processor cores for on-chip test generation It has been shown that adders can be used as test generators for pseudorandom and deterministic patterns Today, there is no general method how to use arbitrary functional units for built-in test generation

Hybrid Functional BIST To improve the quality of FBIST we introduce the method of Hybrid FBIST The idea of Hybrid FBIST consists in using the mixture of functional patterns produced by the microprogram (no additional HW is needed), and additional stored deterministic test patterns to improve the total fault coverage (HW overhead: MUX-es, Memory) Tradeoffs should be found between the testing time and the HW/SW overhead cost

Example: Functional BIST for Divider Functional BIST quality analysis for Samples from N=20 cycles DB=64 Register block Control K Data SB=05 ALU Signature analyser K*N Functional test Data compression: K pairs of operands B, B2 N*SB / DB = 97 Fault simulator Fault coverage Test patterns (samples) are produced on-line during the working mode

Example: Functional BIST Quality for Divider Fault coverage of FBIST compared to Functional test Data Functional testing Functional BIST B B2 Total B B2 Total 4/2 3.2 5.09 4.5 35.4 40.57 29.72 7/2 2.23 6.98 9.0 38.44 47.64 29.25 6/3 9.34 3.6 25.47 4.04 39.62 42.45 8/2 25.47 0.38 7.92 32.07 40.57 25.00 9/4 8.96 5.66 7.3 36.56 47.64 25.47 9/3 32.55 26.89 29.72 43.63 46.07 40.57 2/6 3.44 8.02 8.87 36.08 39.62 32.55 4/2 8.6 25.00.32 37.50 49.06 25.94 5/3 29.48 3.3 27.83 47.88 50.00 45.75 2/4 7.8 7.55 8.02 29.0 20.75 33.02 Aver. 8.96 7.83 7.97 37.74 42.5 32.97 Gain.0.0.0 2.0 2.4.8 Traditional Functional test UUT Result Reference Go/NoGo FBIST UUT Result HW overhead Signature Reference Go/NoGo FBIST: collection and analysis of samples during the working mode Fault coverage is better, however, still very low (ranging from 42% to 70%)

Hybrid Functional BIST for Divider Hybrid Functional BIST implementation MUX M Automatic Test Pattern Generator Register block ALU Deterministic test set Random resistant faults K Data Signature analyser Test patterns are stored in the memory

Cost Functions for Hybrid Functional BIST Total cost: Cost C Total = C FB_Total +C D_Total C Total = C FB_Total +C D_Total The cost of functional test part: C FB_Total = C FB_Const + C FB_T + C FB_M Opt. cost The cost of deterministic test part: C FB_T + C FB_M C D_T + C D_M C D_Total = C D_Const + C D_T + C D_M C D_Const C FB_Const Length of FBIST C FB_Const, C D_Const - HW/SW overhead C FB_T, C D_T - testing time cost, - weights of time and memory expenses Opt. length Problem: minimize C Total

Hybrid Functional BIST Quality Hyb FBIST with multiple seeds (data operands) Functional test part k N j N FC % Total cost Determ. test part D Total cost Total cost k number of operands used in the FBIST 0 0 0 00 0 58 648 648 08 08 66,8 40 24 2544 2684 2 05 23 76,7 277 8 908 285 3 3 326 83,3 58 7 802 2320 The fault coverage increases if k increases 4 08 434 85,5 690 6 696 2386 5 0 544 88,4 864 5 590 2454

Functional Self-Test with DFT Example: N-bit multiplier N cycles Improving controllability T MUX Register block ALU F EXOR Improving observability K Signature analyser Data

Hybrid BIST for Multiple Cores Embedded tester for testing multiple cores Embedded Tester C2670 C3540 Deterministic test patterns: C880 C355 C908 C2670 C3540 Test Controller Tester Memory BIST BIST Test access mechanism BIST BIST BIST Pseudorandom or functional test patterns generated on-line C908 C880 C355 SoC

Hybrid BIST for Multiple Cores Deterministic test (DT) How to pack knapsack? How to compress the test sequence? Pseudorandom test (PT)

Multi-Core Hybrid BIST Optimization Cost of BIST: C TOTAL = k + t(k) FAST estimation Number of remaining faults after applying k pseudorandom test patterns r NOT (k) # faults min C TOTAL Total Cost C TOTAL k SLOW analysis # tests Cost of pseudorandom test patterns C GEN Cost of stored test C MEM t(k) Number of pseudorandom test patterns applied, k Figure 2: Cost calculation for hybrid BIST Pseudorandom Test Det. Test PR test length k Two problems: ) Calculation of DT cost is difficult 2) We have to optimize n (!) processes How to avoid the calculation of the very expensive full DT cost curve?

Deterministic Test Length Estimation Deterministic test (DT) Fault coverage Pseudorandom test (PT) 00% F* F F D k ( i ) F P E k ( i ) j i i * T D F k i Solution of the first problem: For each PT length i* we determine - PT fault coverage F*, and - the imaginable part of DT FD k (i) to be used for the same fault coverage Then the remaining part of DT TD E k(i) will be the estimation of the DT length T D E k ( i ) Pseudorandom test length Deterministic test length estimation for a single core

Deterministic Test Cost Estimation Total cost calculation of core costs: 8000 DT cost Memory Constraint 6000 5500 Constraint Core name: c499 c880 c355 c908 c535 c6288 c432 Memory usage: 5357 bits Memory usage: 353 480 025 363 236 0 0 Deterministic time: 33 8 25 2 0 0 Memory (bits) 4000 Core costs Cost Estimates for Individual Cores Real Cost Real cost Estimated Cost 2000 0 500 542 Solution Estimated cost 000 Total Test Lenght (clocks) 500 Total test length

Total Test Cost Estimation COST Using total cost solution we find the PT length: DT cost PT cost E COST D,k COST E* T COST T,k Total cost Total cost solution COST P,k j* k j min PT length solution E Solution Pseudorandom test (PT) length j Using PT length, we calculate the test processes for all cores: c432 c6288 4 4 2 c880 6 3 c908 c535 c355 c499 9 40 2 86 46 205 36 203 90 69 50 Total Test 23 Deterministic Pseudorandom 0 50 00 50 200 48 73 25

Multi-Core Hybrid BIST Optimization Iterative optimization process: - First estimation * - Real cost calculation 2 - Correction of the estimation 2* - Real cost calculation 3 - Correction of the estimation 3* - Final real cost G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Test Time Minimization for Hybrid BIST of Core-Based Systems. Asian Test Symposium 2003, Xi an, China, November 7-9, 2003,

Optimized Multi-Core Hybrid BIST Pseudorandom test is carried out in parallel, deterministic test - sequentially

LFSR LFSR LFSR LFSR Test-per-Scan Hybrid BIST Every core s BIST logic is capable to produce a set of independent pseudorandom test The pseudorandom test sets for all the cores can be carried out simultaneously Embedded Tester Test Controller LFSR s327 Scan Path Scan Path Scan Path Scan Path LFSR s298 Scan Path Scan Path Scan Path Scan Path TAM Deterministic tests can only be carried out for one core at a time Tester Memory Only one test access bus at the system level LFSR Scan Path Scan Path Scan Path LFSR Scan Path Scan Path Scan Path is needed. Scan Path Scan Path SoC s423 s838

Bus-Based BIST Architecture Self-test control broadcasts patterns to each CUT over bus parallel pattern generation Awaits bus transactions showing CUT s responses to the patterns: serialized compaction Source: VLSI Test: Bushnell-Agrawal

Broadcasting Test Patterns in BIST Concept of test pattern sharing via novel scan structure to reduce the test application time:...... CUT CUT 2...... CUT CUT 2 Traditional single scan design Broadcast test architecture While one module is tested by its test patterns, the same test patterns can be applied simultaneously to other modules in the manner of pseudorandom testing

Broadcasting Test Patterns in BIST Examples of connection possibilities in Broadcasting BIST: CUT CUT 2 CUT CUT 2 j-to-j connections Random connections

Broadcasting Test Patterns in BIST Scan configurations in Broadcasting BIST: Scan-In Scan-In...... CUT... CUT n...... MISR Scan-Out Common MISR...... CUT CUT n...... MISR MISR n Scan-Out Individual and multiple MISRs

Software BIST SoC Software based test generation: CPU Core load (LFSRj); for (i=0; i<nj; i++)... end; Core j Core j+ ROM LFSR: 0000000000 N: 275 LFSR2: 0000000 N2: 900... Core j+... To reduce the hardware overhead cost in the BIST applications the hardware LFSR can be replaced by software Software BIST is especially attractive to test SoCs, because of the availability of computing resources directly in the system (a typical SoC usually contains at least one processor core) The TPG software is the same for all cores and is stored as a single copy All characteristics of the LFSR are specific to each core and stored in the ROM They will be loaded upon request. For each additional core, only the BIST characteristics for this core have to be stored

Embedded Built-in Self-Diagnosis (BISD) Introduction to Fault Diagnosis Combinational diagnosis (effect-cause approach) Sequential (adaptive) diagnosis (cause-effect approach) General conception of embedded BISD Diagnostic resolution Intersection based on test subsequences Intersection based on using signature analyzers Fault model free diagnosis Fault evidence based diagnosis

Raimund Ubar Research in ATI Why Fault Masking is Important Issue? Diagnosis method Devil s advocate approach Single fault assumption Multiple faults allowed Angel s advocate Fault table Tested faults Tested faults Tested faults Fault candidates? Fault candidates Proved OK Fault candidates Test result Passed Failed Failed Diagnosis 44/24

Fault Diagnosis Fault modeling How many rows and columns should be in the Fault Table? Fault table F F 2 F 3 F 4 F 5 F 6 F 7 T 0 0 0 0 0 T 2 0 0 0 0 0 T 3 0 0 0 T 4 0 0 0 0 0 T 5 0 0 0 0 T 6 0 0 0 0 Fault simulation Fault F 5 located Fault diagnosis Test experiment E E 2 E 3 0 0 0 0 0 0 0 0 0 0 0 Testing Test generation

Combinational Fault diagnosis Fault localization by fault tables (cause-effect concept) F F 2 F 3 F 4 F 5 F 6 F 7 T 0 0 0 0 0 T 2 0 0 0 0 0 T 3 0 0 0 T 4 0 0 0 0 0 T 5 0 0 0 0 T 6 0 0 0 0 E E 2 E 3 0 0 0 0 0 0 0 0 0 0 0 Fault F 5 located Faults F and F 4 are not distinguishable No match, diagnosis not possible

Combinational Fault Diagnosis Fault localization by fault dictionaries (cause-effect concept) Fault dictionaries contain the sama data as the fault tables with the difference that the data is reorganised The column bit vectors can be represented by ordered decimal codes or by some kind of compressed signature No Bit vectors Decimal numbers Faults 00000 0 F 7 2 0000 06 F 5 3 000 F 6 4 0000 24 F, F 4 5 000 35 F 3 6 000 44 F 2 Test results: E = 06, E = 24, E = 38 No match

Sequential Fault Diagnosis Sequential fault diagnosis by Edge-Pin Testing (cause-effect) F F 2 F 3 F 4 F 5 F 6 F 7 T 0 0 0 0 0 T 2 0 0 0 0 0 T 3 0 0 0 T 4 0 0 0 0 0 T 5 0 0 0 0 T 6 0 0 0 0 F,F 2 F 3,F 4 F 5,F 6 F 7 P T F,F 4,F 5,F 6,F 7 F F 2, F 3 T 3 P F F 3 T 2 F P F,F 4 F 5,F 6,F 7 T 3 P Diagnostic tree Two faults F,F 4 remain indistinguishable Not all test patterns used in the fault table are needed F Different faults need for identifying test sequences with different lengths The shortest test contains two patterns, the longest four patterns F 5,F 7 T 4 F P F 7 F 2 F 6 F 5

Raimund Ubar CREDES Summer School Sequential Fault Diagnosis Guided-probe testing at the gate level (effect-cause) x 8 Searh tree: P F No faults x 6 P x 4 F F x 5,2 P F Line x 2 is faulty OR- x 8 is faulty x 2 P F x 3, Faulty circuit: P F NOR- x 5 is faulty x 3 Line x 2 is faulty P F x 2 x 3 x 4 x 3, x 3,2 Line x 3, is faulty Line x 3 is faulty x 5 x 6 x 5, x 5,2 x 7 x 8 P x 3,2 P AND- x 6 is faulty F x 3 P F Line x 3,2 is faulty Line x 3 is faulty 49

Embedded BIST Based Fault Diagnosis BISD scheme: Pseudorandom test sequence: Test Pattern Generator (TPG)...... BISD Control Unit Circuit Under Diagnosis (CUD)...... Output Response Analyser (ORA) Test patterns Pattern Signature Faults........................................................................... Diagnostic Points (DPs) patterns that detect new faults Further minimization of DPs as a tradeoff with diagnostic resolution May -4, 2008 26th International Conference on Microelectronics, Niš, Serbia 4/20

Built-In Fault Diagnosis Diagnosis procedure: Test Pattern Generator (TPG)...... BIST Control Unit. test 2. test 3. test Faulty signature Circuit Under Test (CUT)...... Output Response Analyser (ORA) Test patterns Number Signature Faults........................................................................ Correct signature 3. test Faulty signature Pseudorandom test sequence

Introduction to Information Theory Entropy H X of a discrete random variable X is a measure of the amount of uncertainty associated with the value of X H = p i log 2 ( p i ) i where p i is the probability of occurrence of the i-th possible value of the source symbol; (the entropy is given in the units of "bits" (per symbol) because it uses log of base 2) H X = - p log 2 p (-p) log 2 (-p) I = - p log 2 p (-p) log 2 (-p) p probability of detecting a fault