EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3
NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS > DSAT ) ( DS < DSAT ) 4
The other classification of models can be done on the basis of magnitude and frequency of applied voltages MOS MODEL Large Signal Small Signal dc or Low frequency Dynamic Low frequency High frequency 5
Threshold oltage G SiO B S D Poly P + N + N + P-Silicon THN ( THN 0 F SB F ) qn s A body parameter Units : : C o x C ox t ox ox, F kt N ln( q n i A ) 6
Body effect is important for NMOS SiO SiO Poly Poly Poly Poly P + N + N + N + P + P + P + N + N + N + P + P + N-well N-well P-Silicon P-Silicon P-Silicon P-Silicon All NMOS transistors t have acommonbd body contact(which t( h is attached to the most negative point in the circuit), while body for PMOS transistors can be tied to their respective source terminals. 7
Body effect can be very significant DD = 3.3 Bias4 M 3 Bias3 Pmos: source and body can be shorted together SB =.1 0 -.1 SS =-33 3.3 M M 1-1. TN 1 0. 7 TN 0.7 ( 1.7 F SB F ) 0.696; F 0.35 8
Dc Model: Triode (or Linear) I DS vs. DS GS TN Triode saturation DS Dsat GS TN I DS N DSAT DS GS THN DS N kp. N W eff A kp C :( TransConduct ance parameter ) N n ox L eff L eff L Drawn L D W W W eff Drawn D 9
A 3.3 A 3.3 1. 0.9/0.6 1. 1.8/0.6 M1 M Why is drain current of M not double that of M1? L eff L Drawn L D W W W eff Drawn D 30
Effective Channel Length L drawn Poly P + N + N + L eff P-Silicon L D L D L eff L L Drawn L D 31
Effective Channel Width M 1 M 3
W eff W W W WD ForHP 0.5m technology, ogy, WD =0.8m.. eff So a W = 0.9 m is effectively equal to W 0.44 m eff 33
Effective Gate Width M 1 09 0.9m M 1.8m I ( M1) 6.06 A DS I ( ) 18.344 3 I DS DS M A IDS1 W eff 1.8 0.8 0.9 0.8 W eff 1 3 34
DC Model: Saturation Region I DS vs. DS GS THN Triode saturation DS GS THN DSAT I DS N ( GS THN ) [1 n DS ] λ N is the channel length modulation parameter 35
The basic I model requires 7 parameters I DS N ( ) [1 ] GS THN n DS,, KPN, LD, WD F TNO N It is important to note that as a designer, one can control drain-tosource current using gate, drain and body voltages as expected but also using the dimensions of the MOS transistor (W/L ratio). Most of MOS design is done by suitably sizing the different transistors in the circuit 36
Temperature dependence I DS KP N W ( L GS THN ) [1 n Temperature affects the current through its impact on transconductance parameter KP N and threshold voltage THN DS ] kp N C At room temperature, mobility decreases with further increase in temperature so that KP N also decreases. A simple model for its temperaturet dependenced is: T 1.5 KPN ( T ) KPN ( TO ) ( ) T The threshold voltage also decreases with increase in temperature THN ( T) THN ( TO ) (1 TCTHN ( T TO )) T O TC THN n ox 1 THN d dt THN TC THN is the temperature coefficient of the threshold voltage. A 37 typical value might be ~ -3000 PPM/ o C 1PPM = 10-6
Although both K PN and THN and decrease with temperature, the former causes a decrease in current while the latter causes an increase in current I DS KPN W L ( GS THN ) [1 Parameter NMOS 3.3 TO() 0.69 (for L = 1μm) 0.015 1. /1 1. /1 0.696 LD ~0 WD(μm) 0.8 KP (μa/ ) 100 T=5 o C T=50 o C n 0.8A DS ] 3.65A 3.3 A 33 3.3 5.6A 33 3.3 0.41mA 33 3.3 0.39mA 33 3.3 0.9 /1 0.9 /1 3 /1 3 /1 T=5 o C T=50 o C T=5 o C T=50 o C 38
The dc model of the transistor in triode and saturation region can be represented in the form of an equivalent circuit: G G D I Poly DS N + N + S D B S P-Silicon B Although there is a small leakage I DS is a voltage controlled current source current between gate and ad (CCS) with an expression described source/drain through the thin gateoxide, earlier. Two PN junction diodes, one it has been ignored in the model. Similarly, with each terminal between source and body and another between drain and body have also been there is a small parasitic resistance in series which is also not shown. With continued reduction in gate added. Normally these diodes are reverse biased and contribute little to current. Application i of avery large drain or bd body oxide thickness, gate leakage is bias can cause breakdown of these diodes becoming of increasing concern and result in large leakage currents. 39
Capacitance Model Saturation AA large signal dynamic model can be built by adding capacitances to the dc model. There are five distinct components of capacitance as illustrated below Cgs Cox. Weff. Leff Cgso. Weff 3 C GS SiO C GD gd GDO eff Poly C C. W N + N + L C SB C C GB DB P-Silicon W S G D L S L D 40
Capacitances: Area and Perimeter Components L W C WLCp (L W) d 41
SiO P-Silicon PSilicon C GS C GD Poly N + N + W S G D C SB C C GB DB L L S L D C sb Csb, bottom Csb, sidewall A C s j C sb, sidewall Area of Source, Zero bias Capacit ance C C jsw. PS, P S L M jsw SB 1 PBSW C. A j s sb, bottom, A M s j SB 1 P B S W eff P built in potential, M grading Coefficient B j W eff 4. L S
C db Cdb, bottom Cdb, sidewall C db, sidewall C jsw. PD, PD L M jsw DB 1 PBSW D W eff C C. L gb GBO eff W L S G D L S L D A factor of is included in C GBO itself 43
Triode/Linear Region 1 C gs Cox. Weff. Leff CGSO. W eff Cutoff Region C C. W gs GSO eff 1 C gd Cox. Weff. Leff CGDO. W eff C gd CGDO. W eff C sb sameasbefore C db sameasbefore C b sameasbefore C gb Assuming DS ~0 DS C sb sameasbefore C db sameasbefore bf C C. L C. W. L gb GBO eff ox eff Assuming Tr. is in accumulation eff 44
The capacitance model presented herein requires 10 parameters: CGSO, CGDO, CGBO, COX, CJ, PB, M J, CJSW, PBSW, M JSW Complete Large Signal Model C gd G C gs I DS Cdb I ds D C gb C sb S B 45
To analyze circuits we need parameters of model Hence, we need to select a MOS technology first. of a MOSFET. Parameter NMOS PMOS TO() 0.69-0.869 (for L = 1μm) 0.015 0.065 0.696 0.456 LD ~0 ~0 WD(μm) 0.8 0.5 KP (μa/ ) 100 40 CGSO (pf/m) 81 5 CGDO(pF/m) 81 5 CGBO(pF/m) 100 100 CJ (μf/m ) 467.7 93 PB 0.5 0.9 MJ 0.5 0.466 CJSW(μF/m) 616.95 181 MJSW 0.35 0.5 Model Parameters for HP 0.5m Technology 46
Typical alues of Capacitances 1m D C GD C DB m S G D G B C GS C SB m m S area C gs 4.1 ff ; C gd 0. 43 C sb 1.3 3.174.47 ff ff C db 0.58.17. 75 ff DB = perimeter 47
ariation of Capacitance with Gate-Source oltage 1.5 GS 48
Small Signal Model 49
Incremental Circuit Analysis R D = 100K DD = 3.3 G = 1. /1 O +v o Given v =1m, find v due to v in o in Parameter NMOS TO() 0.69 (for L = 1μm) 0.015 0.696 LD ~0 WD(μm) 0.8 KP B. Mazhari, (μa/iitk ) 100 v in N I DS GS THN n DS ( ) [1 ] I R O DS DD DS D N O DD ( GS THN) [1 no] RD 1.54 for GS 1.00 1.018 1.46 for 1.01 v 8m GS o 50
Incremental Circuit Analysis R 1.54 for 1.00 N O DD ( GS THN) [1 n O] D GS 1.46 for 1.01 v 8 m GS o 1.018 Can we neglect this factor? R 1.9 for 1.00 error is 38m N ( ) O DD GS THN YES! D GS R 1.84 for 1.01 N O DD ( GS THN ) D GS vo 8m 51
Incremental Circuit Analysis R 1 I 1 0 s1 R I s s =10m volts; =? s1 0 5
0 =5m 53
One Method: Superposition Theorem R 1 I 1 R 1 0 S1 R I s R R vs1 0 v s1 s v o s1 R R R 1 5m But this requires the circuit to be linear! 54
Alternative Method s1 R 1 I 1 0 (1) S 1 I1R1 0 R I s I = I +( - )/R () s 1 S 0 S R 1 v i 0 1 v s1 R Incremental Equivalent Circuit Let I S 1 1 +i Δ +v 1 s1 s 1 = I = v s1 = (I +i S 1 +( 0 1 ) R + +v o 1 - s1 1 1 S 0 )/R (3)-(1): v =i R +v (4)-():() i =v o /R v =i R +i R 1 s1 1 1 1 o +v o (3) (4) Increment equivalent circuit can be obtained by building incremental device model for each circuit element. 55
Terminology X : Nominal or base alue X Normally is a dc vx : incremental alue Often ac but could be dc as well x X vx :Netle alue 56
Incremental Models: Resistor R v( I i) R IR vir Incremental model of a resistor is a resistor of the Same magnitude Capacitor d I = C dt d( + v) I + i = C Incremental model of a capacitor is a capacitor of the same magnitude. The same holds for an inductor as well. i = C dv dt dt 57
Incremental Models = constant v = 0 I = constant i = 0 Incremental model of a constant oltage Source is a short circuit Incremental model of a constant current Source is an open circuit 58
Solution using incremental equivalent device models S1 R 1 I 1 R 1 R 0 I s v s1 i 1 v 0 R v s1 s Incremental Equivalent Circuit v v o s1 R R R 1 59
Nonlinear element I 1 R 0 i R v S cc X I s v s? I X =K X I x k x I i k( v ) X x X x X v x X i x = k {1 ( + / ) - 1} 60
Non-linearity makes the model difficult to use so approximations are used to make it linear i x X v x X =k {1 ( + / ) -1} Small signal approximation: v x / X << 1 i x v k {(1 x X ) 1} k X X v x i = v / r ; r = x x x x 1 k X 61
Nonlinear element I 1 R 0 cc X I s i R v o r x v S v s I X =K X v o v s rx R r x r x = 1 k o 6
How small is small? Depends on how much error we can tolerate! X x X i x =k {1 ( + v / ) -1} ix k X v x X = 1 4 I k v x () Error (%) 0.0 1 0. 10 0.5 0 x x X = 1 v x () Error (%) 0.007 1 1.0 33.3 0.071 10 0.5 50.77 1.0 73.3 Stronger nonlinearity implies smaller voltage for same error 63
One of the strongest non-linearity is exponential I x x X vx kexp( ) IX ix kexp( ).06.06 i x X v x X vx kexp( ) {exp( ) 1} ix kexp( ) ( ).06.06.06.06 X = 0.7 v x (m) Error (%) 0.53 1 5.4 10 10 18 6 41.8 64
General approach for obtaining small signal model for a -terminal device (not containing capacitor/inductors) I = f( ) x x I +i = f( +v ) X x X x df = f( )+v ( ) +... X x d X x i x =vx/rx r x = 1 df ( ) d X x 65
General approach for obtaining small signal model for a 3-terminal device I i I 0 + i i i i 0 + - - δf i=ν δ i i i δi I ν r i i I=f() I +i = f(+ν ) I i i I i Assumption: unilateral (Output does not affect the input) 1 r= i δfi δ i I From the input port, the device appears as a resistance 66
I i I 0 + + i 0 - - I I O O = +i o Output port: f O = (, f O i ( O i ) ν i, O +ν o ) δf δf I i f (, ) ν ν... 0 0 O o o i o i o O I δi δ0 δf δf i ν ν 0 0 o i o O I δi δ0 i =g ν o g m m i δff δ ν r o o 0 1 r0 O i δf0 I δ0 g m v i v o r 0 67
Complete small signal model (dc) for a 3-terminal device. unilateral I i I 0 + + i 0 - - i O v o i i r i g m v i r O 68
Small Signal Model (dc/low frequency) G D S I DS I ds N (1 ) gs THN () n ds B gs GSQ v gs ds DSQ v ds sb SBQ v sb I ds I DSQ i ds 69 Q: quiescent or dc bias point
I i v v v N DSQ ds GSQ gs THN BSQ bs 1 n DSQ n ds i ds gs thn n ds v v v I DSQ 1 1 1 1 GSQ THN n DSQ vthn THN BSQ vbs ( ) THN v v thn F BSQ bs F BSQ i ds 1 vgs vthn 1 nv I ds DSQ 1 1 GSQ THN n DSQ Assumption: v ( ) gs GSQ THN vgs vthn nv Ignoring cross terms: ds i ds IDSQ 1 1 1 GSQ THN ndsq 70
vgs vthn i I v GSQ THN ds DSQ n ds v ( v ) thn F BSQ bs F BSQ v v 1 bs v 1 bs thn F BSQ F BSQ F BSQ Assumption: v ( ) bs F SBQ v gs v i bs ds I DSQ nv ds ( ) GSQ THN GSQ THN F BSQ 71
v gs v i bs ds IDSQ nvds ( ) GSQ THN GSQ THN F BSQ v i g v g v r ds ds m gs mbbs b o r o 1 I n DSQ g m I GSQ DSQ THN I DSQ g mb g m. F SBQ 7
Small Signal low frequency model i ds g m v gs g mb v bs v r ds o g g mb v bs i ds d g mv gs r o s b 73
i ds v v 1 gs thn DSQ 1 I GSQ THN g m I DSQ GSQ THN I DSQ i ds g v m gs (1 vgs ) GSQ THN Thus the small signal approximation i g v is accurate when v ( ) gs GS THN ds m gs v gs / GS - THN +0.1-0.1 +0. -0. +0.5-0.5 1-1 Error (%) -4.7 5.6-9.1 11.11-0 33.33-33.3 100 For positive values of v gs, the small signal approximation results in underestimation of current while for negative values, the current is 74 B. overestimated. Mazhari, IITK
High Frequency Small Signal Model C gd G C gs g i ds mb v bs g m v gs r o i d D C gb C S sb C db B 75