22 2 2018 2 Electri c Machines and Control Vol. 22 No. 2 Feb. 2018 300072 SMC FPGA PID SMC SMC SMC FPGA DOI10. 15938 /j. emc. 2018. 02. 009 TP 23 A 1007-449X201802-0064- 07 Modeling and sliding mode control of electric vehicle charger control system LI BinGUAN Tian-yi Key Laboratory of Smart Grid of Ministry of EducationTianjin UniversityTianjin 300072China AbstractBased on the analysis of the various links of the control system for the electric vehicle charger the mathematical models of the voltage and current of the control system were established. Furtherthe voltage and current-based sliding mode control SMCalgorithms were presented to control the charging processrespectivelyin order to enhance the robustness of the charging process. On this basisthe structure and the operation process of a new charging control system was designed with field-programmable gate arrayfpgachip as the core controller. The PID-based conventional three-stage charging mode and SMC-based intelligence charging mode were employed to correspond different types of power battery for increasing versatility. The performance of the SMC and the different charging modes were simulated and analyzed. The simulation results show that the SMC method has excellent control and robust performance in the control of the charger system. Keywordselectric carchargersliding mode controlcontrol system modelingfpga chip 0 2-3 2017-06 - 12 51422703 1976 1994 1
2 65 G 1 s= 4-5 1 sn 2 L tl + L th + n 2 R L + n 2 R tl + R th 1 4 RLC u bi u bo R th L th pulsewidth modulation PWM R L n R tl L tl RLC 4 G 4 s= N 5 N 0. 9 Fig. 1 1 Each section in control system K pwm Ts + 1 Z 1. 1 1 Z = C pr p R 0 s + R 0 + R p = b 0s + b 1 C p R p s + 1 a 0 s + 1 7 b 0 = C p R p R 0 b 1 = R p + R 0 a 0 = C p R p a 1 = b 0 L 2 1 K pwm T K pwm K pwm = U lmt E 2 E U lmt 6-7 2RLC RLC sliding mode control 1 SMC G 2 s= L 1 C 1 s 2 + R 1 C 1 s + 1 1 R 1 C 1 s + 1 3 R 1 C 1 L 1 field-programmable gate array FPGA s 2 L 1 C 1 PID 3 SMC G 3 s= u bos u bi s = n 2 R L 5 Thevenin 8 Thevenin G 5 s= 1 C 2 s / /Z L 2 s + 1 C 2 s / /Z = b 0 s + b 1 a 1 s 3 + a 2 s 2 + a 3 s + b 1 6
66 22 C 2 a 2 = L 2 b 1 C 2 + a 0 a 3 = L 2 + b 0 R 0 R p C p L 2 C 2 1. 2 G 6 S= G 1 SG 2 SG 3 SG 4 S= 2. 1 K pwm Ts + 1 1 R 1 C 1 s + 1 n 2 R L Sn 2 L tl + L th + n 2 R L + n 2 R tl + R th N = b 2 8 a 4 S 3 + a 5 S 2 + a 6 S + a 7 b 2 = K pwm Nn 2 R L a 4 = TR 1 C 1 n 2 L tl + L th a 5 = T + R 1 C 1 n 2 L tl + L th + TR 1 C 1 n 2 R L + n 2 R tl + R th a 6 = n 2 L tl + L th + T + R 1 C 1 a 7 = n 2 R L + n 2 R tl + R Th G 6 s G 5 s u = 1G 1G 4 G V s= G 5 sg 6 s= { - 1G 2 G 3 b 0 s + b 1 a 1 s 3 + a 2 s 2 + a 3 s + b 1 b 2 a 4 s 3 + a 5 s 2 + a 6 s + a 7 9 G V s= k 3 k 2 s 2 + k 1 s + k 0 10 k 0 ~ k 3 S V x t= c 1 x 1 t+ c 2 x 2 t 15 c 1 c 2 G I s= G Vs h S V x t= 0 4 = Z h 3 s 3 + h 2 s 2 + h 1 s + h 0 h 0 ~ h 4 11 2 PWM S V x t 10 [ ] [ ] [ ] x1t 0 1 x 1 t = + 0 x2t k 21 k22 x 2 t b 0 E u 12 b 0 k 21 k 22 t u [ ] 13 G 1 G 4 G 2 G 3 IGBT u S V x t x 1 t x 2 t x 1 t= V ref - u 0 14 x 2 } t= x 1t= V ref - u 0 V ref Vref u 0 u0 x 1tx2t x 1 tx 2 t 0 < k 21 c 2 x 1 t+ c 1 + k 22 c 2 x 2 t< - b 0 c 2 E 16 c 1 c 2
2 67 H 3 2 3 Fig. 3 SMC structure based on current 2 Fig. 2 SMC structure based on voltage 2. 2 SMC 11 4 4 x3t 0 1 0 x 3 t 0 FPGA x4t = 0 0 1 x 4 t + 0 u CAN USB x5t k 31 k 32 k 33 x 5 t b 1 E D \ A battery management system BMS 17 b 1 k 31 k 32 k 33 u PWM 13 u EMIelectro magnetic interference PFCpower factor correction S I x t x 3 t x 4 t x 5 t x 3 t= I ref - i 0 } BMS x 4 t= x 3t= I ref - i0 18 D / x 5 t= x 4t= ẍ 3 t= I ref - ï 0 A PWM I ref Iref i 0 i0 ï 0 RLC S I x t= c 3 x 3 t+ c 4 x 4 t+ c 5 x 5 t 19 c 3 c 4 c 5 3 S I x t= 0 0 < k 31 c 5 x 3 t+ c 3 + k 32 c 5 x 4 t+ c 4 + k 33 c 5 x 5 t< - b 1 c 5 E 20 BMS PWM c 3 c 4 c 5
68 22 Fig. 4 4 Overall structure of the charger control system k 0 = 1k 1 = 3k 2 = 2k 3 = 1h 0 = 7 PID h 1 = 21. 13h 2 = 14. 3h 3 = 0. 26h 4 = 26b 0 = - 0. 5k 21 = - 0. 5k 22 = - 1. 5b 1 = - 26k 31 = SMC - 27k 32 = - 81. 3k 33 = - 55 1 300 V 2 c 1 = 21 c 2 = 0. 001 5 1 5a u 0 5b state of charge SOC10% u bi 5c 2 SOC u l 5d 10% 5 a 299. 1 V ~ 301. 4 V FPGA 4 0. 02 s u p 1 5 0. 02 s 4. 1 2 5 SIMULINK 0. 02 s
2 69 5 Fig. 5 Waveforms with the load disturbance using SMC 4. 2 40 A 0. 02 s i 0 6a 40 A 0. 02 s 43. 9 A 6 Fig. 6 Charger output current waveform c 3 = 23 c 4 = 0. 005 c 5 = 3 10-10 i 0 6b 5 0. 02 s 40. 3 A 40 A 6a SIMULINK 6b SOC
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