New Simultaneous Switching Noise Analysis and Modeling for High-Speed and High-Density CMOS IC Package Design

IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 23, NO. 2, MAY 2000 303 New Simultaneous Switching Noise Analysis and Modeling for High-Speed and High-Density CMOS IC Package Design Yungseon Eo, Member, IEEE, William R. Eisenstadt, Senior Member, IEEE, Ju Young Jeong, Member, IEEE, and Oh-Kyong Kwon, Member, IEEE Abstract A new simple but accurate simultaneous-switchingnoise (SSN) model for complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) package design was developed. Since the model is based on the sub-micron metal-oxide-semiconductor (MOS) device model, it can fairly well predict the SSN for today s sub-micron-based very large scale integration (VLSI) circuits. In order to derive the SSN model, the ground path current is determined by taking into account all the circuit components such as the transistor resistance, lead inductance, load capacitance, and oscillation frequency of the noise signal. Since the current slew rate is not constant during the device switching, a rigorous analysis to determine the current slew rate was performed. Then a new simple but accurate closed-form SSN model was developed by accurately determining current slew rate for SSN with the alpha-power-law of a sub-micron transistor drain current. The derived SSN model implicitly includes all the critical circuit performance and package parameters. The model is verified with the general-purpose circuit simulator, HSPICE. The model shows an excellent agreement with simulation even in the worst case (i.e., within a 10% margin of error but normally within a 5% margin of error). A package design methodology is presented by using the developed model. Index Terms CMOS, integrated circuits, package, simultaneous switching noise, switching. I. INTRODUCTION WITH THE rapid improvement of semiconductor process technologies and circuit performances, today s very large scale integration (VLSI) system of 500 MHz clocks, several GHz clock bandwidth, and several million transistors needs improved circuit design methodologies [1] [3]. One of the critical bottlenecks of such system design is the voltage reference potential fluctuation due to packaging, i.e., simultaneous switching noise (SSN) [4] [10]. Particularly, the SSN results in serious performance degradation and system Manuscript received April 7, 1998; revised January 6, 2000. Y. Eo is with the Department of Electronic Engineering, Hanyang University, Ansan, Kyungki-Do 425-791, Korea (e-mail: eo@iel.hanyang.ac.kr). W. R. Eisenstadt is with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611-6130 USA (e-mail: wre@tec.ufl.edu). J. Y. Jeong is with the Department of Electronic Engineering, University of Suwon, Whasung-Gun, Korea (e-mail: jyeong@mail.suwon.ac.kr). O.-K. Kwon is with the Department of Electronic Engineering, Hanyang University, Seoul 134, Korea. Publisher Item Identifier S 1521-3323(00)03115-4. failures due to the reduction of noise margin, the increase in the effective signal delay, glitches, and signal distortion. Since the noise is proportional to the number of switching gates and the many package design parameters, circuit designers must take these packaging effects into account at an early phase of circuit design. Many package design methodologies concerned with simultaneous switching noise (SSN) models are reported [11] [16]. However, their work is approximate because they have a fundamental limitation in that they assume that the transistor has a constant current slew rate during the whole transition of the input signal. Vaydianath et al.derived a good SSN model based on the long-channel metal oxide semiconductor (MOS)-transistor approximation that considered the negative feedback due to the voltage across the inductor [4]. Since the model was based on the long-channel approximation, their model could not fully predict the SSN for sub-micron-based circuits. The simple long-channel approximation clearly overestimates the SSN noise because the model predicts much more current variation than is presented in short channel devices. Unlike the long-channel model of [4], Vemuru [5] modeled the SSN based on Sakurai s alpha-power model (i.e., linear power law) [17] and similarly, Yang et al.also modeled the SSN by employing the similar linear power law of sub-micron-device drain current [14]. However, although they take the velocity saturation effects of sub-micron devices into account, the model did not consider the physical behaviors of transistor, inductance, and capacitance as a system. Particularly, the output load capacitor strongly affects the noise oscillation frequency, which is also a function of the current slew rate. Therefore a more rigorous physical interpretation of the transistor operation regions is necessary to estimate the accurate SSN and to design the advanced packaging. In this work, the inductive effects, as well as capacitive load effects, for the SSN model are physically investigated and modeled. SSN is inherently a very complicated function of circuit and device parameters. However, the model presented here is very simple and accurate. Since the simple model shows excellent agreement with HSPICE simulation within about a 5% margin of error, package design with a minimum SSN can be achieved by using the proposed model. Thus, it is an excellent design equation for high-density and high-speed integrated circuit design and advanced package design concerned with SSN. 1521 3323/00$10.00 2000 IEEE

304 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 23, NO. 2, MAY 2000 Fig. 2. Equivalent switching circuit model for the discharging path with a package (ground) inductance: (a) circuit diagram for switching and (b) equivalent RLC circuit for the discharging path. Fig. 1. Signal transients in the input and output of a CMOS inverter: (a) circuit diagram, (b) signal transients of input ramp and output response, and (c) current flow through the NMOS device. II. EFFECTS OF CIRCUIT COMPONENTS ON SIMULTANEOUS SWITCHING NOISE A. Saturation Time of NMOS Transistor NMOS transistors are concerned with the discharging path of complementary metal-oxide-semiconductor (CMOS) gates. Thus, the SSN in the ground path of CMOS circuits is closely related to the NMOS transistor operation mode. A MOS device experiences three operation regions during the switching: i.e., cut-off, saturation, and linear region (nonsaturation region). Thus, the transistor output current is not constant during the whole transition of input gate signal. In the CMOS inverter circuit as shown in Fig. 1 (without taking the inductance into account), the CMOS inverter fall time can be decomposed of where the first term represents time slot of the linear region and the second term represents the time of the saturation region of the CMOS inverter, i.e., (1) (2) If the saturation duration is long, the maximum current peak of NMOS transistor occurs at the end of the saturation period of the device operation. The, the saturation time components of the fall time, can be approximated by using the output current model of an NMOS transistor. That is, for a very simple RC model with the abrupt input signal transition, can be derived by [18] where,, and are device transconductance, device threshold voltage, and load capacitance, respectively. Thus, the saturation time is a function of device parameters and output load capacitance. Note that has a very short time duration in many cases. Thus, without considering both inductive and capacitive reactance in the today s high-speed circuits, the overly simple saturation current modeling may result in an erroneous estimate of SSN. B. Discharging Current Model in the Ground Path In this subsection, the inductance and capacitance effects on the ground current are considered. The current flow mechanism, including both inductance and transistor, can be approximately quantitatively described by modeling the transistor as a resistance. The CMOS inverter circuit is shown in Fig. 2(a). Modeling the NMOS device as a simple resistance during the transition, an equivalent circuit for a discharging path becomes an (3)

EO et al.: HIGH-SPEED AND HIGH-DENSITY CMOS IC PACKAGE DESIGN 305 resistance, inductance, capacitance (RLC) circuit as shown in Fig. 2(b). In order to determine the current slew rate, the current must be found as a function of time. Then the time, that the maximum current flows, can be evaluated. The current in such RLC circuits can be readily determined as follows [19], [20]: where and where is a linearized transistor resistance model. However, in more detail, the solution of the current is divided into three special cases depending upon transistor resistance, package inductance, and load capacitance. Now defining a critical resistance as (4) (5) the solution may result in one of three cases, the over-damped case, the critically-damped one, or under-damped one. Since the may have different forms for these three cases, the must be determined separately for each case. That is, the time that makes the time derivative of each current equation be zero must be calculated. 1) Over-Damped Case : Then the time that maximum current flows can be determined by the first derivative of (6) as follows: (6) - (7) 2) Critical-Damped Case : Thus the maximum current flows at the time of 3) Under-Damped Case : (8) - (9) Similarly the maximum current flows at the time of (10) - (11) Therefore, the time that the maximum current flows is a complicated function of load capacitance, ground line package inductance, and device parameters. It is noteworthy that many of submicron-technology-based I/O drivers may have smaller resistance than. Thus, in many cases, the ground path current is Fig. 3. Schematic output current flow during the input and output voltage transients. dominated by the under-damped case which is oscillating [20]. The time that sinusoidal current reaches the first instantaneous peak value with reasonable parameters is usually very short in all three cases, but it is a strong function of the load capacitance. If the under-damped ground path current has more than one sinusoidal peak value during the input transition time (i.e., input rise time), during the oscillation there may be a much larger current slew rate between the positive peak and the negative peak current. This large slew rate between the peak-to-peak currents results in a significantly larger SSN. This is a very important fact because the SSN due to the large peak-to-peak current slew rate may be more than twice those of [5] and [14] which simply assume that the ground current always has only one sinusoidal peak during the input transition time. This will be discussed in more detail in Section IV. III. A NEW PHYSICAL FORMULATION FOR SSN MODEL As described in Section II, the discharging current of the transistor is dependent on its operation mode, package inductance, and the load capacitance. The transistor current flow due to the transients of the input and output signal is schematically shown in Fig. 3. The is defined as a time that an input ramp transits from 0 to and the is defined as a time that the input ramp transits from 0 to NMOS transistor threshold voltage. The current flow mechanism of NMOS transistor can be qualitatively explained as follows. At the region to, the current does not flow because the NMOS transistor does not operates until. Therefore, will stay nearly at a constant value rather than changing. In contrast, still goes up toward. Next, to transition is dominated by both transistor current and inductor voltage. Thus, there are many possible current paths as shown in Fig. 3. As mentioned, the current may not be uniformly changing during the transit time in this region. That is, the current slew rate near region is larger

306 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 23, NO. 2, MAY 2000 Fig. 4. Schematic diagram of input signal transient and the oscillating currents of RLC circuit (I ) and NMOS device switching current (I ). than that near the region because the amplifier (i.e., the inverter) has the largest voltage gain near the switching threshold voltage. Because of this fact, it cannot be simply assumed that the maximum current slew rate is equal to an average slew rate between and. In the next region, that is, the to transition, the linear region where the transit time is not as fast as the saturation region. Note, however, because of the package inductance and load capacitance, the ground path current may oscillate. If the ground path current oscillates, there may be many occasions where the current varies rapidly within a very short time as shown in Fig. 4. This results in a large current slew rate, even if the transistor is in the linear operation region. Thus, in this work, assuming that the first peak value of the sinusoidal oscillation current during the switching is larger than the value at (see Fig. 5), a new SSN model is derived. Other cases will be discussed in Section IV. Note that the current slew rate is larger near than the average current slew rate between and. Thus, it may not be accurate to estimate the real SSN by using the conventional average slew rate between and. A new accurate slew rate can be determined by defining as a time when an input ramp reaches the switching threshold voltage ( ) of a CMOS inverter. Then a more reasonable assumption can be established. Namely, that a maximum current slew rate occurs between the time interval between and rather than the average slew rate between and. Further, in most cases, since SPICE simulation of submicron-based CMOS circuits uses the higher level MOS model parameters such as level 13 (BSIM1) or level 49 (BSIM3), its device parameter is not constant with bias Fig. 5. Schematic device output current (I ) when the first peak of sinusoidal current of RLC circuit (I ) occurs during input signal transient. voltage. Therefore, it is more reasonable to employ near the. The next consideration for the slew rate is to determine the output current model. Today s sub-micron device drain current must be adapted to Sakurai s alpha-power law that the current is not dominated by the conventional long-channel-based square power but by the alpha-power [17]. The alpha of the today s deep sub-micron device current is nearly one [5]. Thus, assuming the alpha-power-law-based drain current at the saturation region, a new maximum simultaneous switching noise can be derived as follows (see Appendix A for the derivation): (12) Herein, is the device transconductance value near the switching threshold voltage ( ) of the gate. Note that the dimension of must not be considered as but. The is a constant factor to adjust the maximum current slew rate. If the is simply assumed as 2, it is similar to the conventional model. However, the intersection of the time axis of the current slope between and is not at but at some point greater than. A reasonable value for most circuit operations is about 3, which is founded empirically from many simulations. In this paper, the is assumed as 3 in order to maintain the model in a simple analytic form. However, it can be empirically extracted again for a particular technology to improve the model accuracy. Taking, (13)

EO et al.: HIGH-SPEED AND HIGH-DENSITY CMOS IC PACKAGE DESIGN 307 interval between device threshold voltage and final voltage of input ramp. Note that in the time interval between and, the transistor stays in saturation region. The simulation results are summarized in Table I. In practical designs, the package must be built in such a way that a quarter of the oscillation period should be larger than the time interval between and. Otherwise, the package noise significantly increases because the (the time interval for the current slew rate determination) becomes very small for the relatively large current change. This will be discussed in more detail in Section IV. (a) IV. SSN MODEL FOR OSCILLATING CURRENTS WITHIN SATURATION REGION If the previous assumption that a quarter of the oscillation current period is greater than the transistor saturation time is violated, a new expression is required. In order to evaluate such a case, the design should be performed by the following procedures. Step 1: Determine the noise signal oscillation period. Step 2: Find the transistor saturation time. Step 3: Determine all the current slew rates within the saturation region. Step 4: Calculate the SSN. However, to make the expression simple, reasonable approximations at Step 3 are performed. By taking the only two positive peaks within the saturation region as shown in Fig. 9, the negative noise peak due to SSN can be derived as follows (see Appendix B for the derivation): (14) where and is a period of oscillation which can be calculated as Fig. 6. (b) Verification of the SSN models with SPICE simulation results for the driver size of =43mA/V [i.e., (W=L) =(150=0:35) and (W=L) =(80=0:35)]: (a) SSN noise variations for the rise time = 0.2 ns and L = 0.2 nh and (b) SPICE-simulation-based time domain waveforms of the SSN. For the verification of our model (13), the simulation was performed with 0.35 m CMOS process-based circuits. The simulation employed the level 49 MOS model [BSIM3] of HSPICE. The NMOS device trans-conductance can be found as ma/v from HSPICE simulation. As shown in Figs. 6 and 7, (13) has excellent agreements for various package design parameters with HSPICE simulation results within about 5% error. Although [5] and [14] agree with HSPICE simulation results for small inductance values and the small number of switching gates, their errors increase as the inductance values or the number of switching gates increase. However, for the case of pf in Fig. 8, our SSN model (13) (also [5] and [14]) does not correctly predict the second peak noise because a quarter of the oscillation period is less than the time (15) Further, the is equal to the of (13) and the is negligibly small for large. However, for small (less than 1 ns) we have the following empirical relationship: (16) The second peak noise of SSN as shown in (14) may underestimate the HSPICE simulation values because the time interval of the real slew rate determination is less than. For example, let us assume that following parameters are given: the rise time is 1ns, the is 43 ma/v, and inductance is 5 nh. Then is 0.31 V and is 0.79 V (HSPICE shows about 0.82 V ). The simulation results are shown in the Fig. 9. Thus, this kind of situation definitely causes much larger SSN peak voltage than (13). Therefore, the designer must avoid this case by controlling design parameters such as load capacitances, package inductances, or transistor size. These are discussed in Section V.

308 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 23, NO. 2, MAY 2000 (a) (b) Fig. 7. (c) (d) SSN in terms of various package design parameters (i.e., the rise time, the package inductance, and the number of the switching gates). Note that the driver size is (W=L) = (150/0.35) and (W=L) = (80/0.35): (a) SSN variations for L = 0.05, 0.1, and 0.15 nh when t = 0.1 ns, (b) SSN variations for L = 0.1, 0.2, and 0.3 nh when t = 0.2 ns, (c) SSN variations for L = 0.2, 0.5, and 0.8 nh when t = 0.5 ns, and (d) SSN variations for L = 0.1, 0.5, and 1 nh when t = 1 ns. V. DESIGN CONSIDERATION The SSN variation is a strong function of inductor, load capacitor, and transistor size. Since the current slew rate maximum happens near to for practical circuits, the slew rate and transistor must be determined near the to.in addition, the capacitance size is quite important because it is a selectable design parameter unlike other fixed parameters, such as the inductor, which is dependent on the package type and ground placement within a chip. Particularly, a small load capacitor may cause the under-damped case (damped-oscillating case) by making too large. The best design guide lines are as follows. Since the inductance is strongly related with physical structures, such as package type or ground configuration, the package type with the minimum inductance should be selected. In this case, the a driver size should be large because the resistance is inversely proportional to the driver size. The transistor resistance must be calculated by using the alpha-power law as follows: (17) If the noise is still oscillating, the load capacitance must be increased. Once the resistance is determined, a quarter of the current oscillation period must be greater than. Thus the capacitance must satisfy Rearranging (18), the load capacitance should meet (18) (19)

EO et al.: HIGH-SPEED AND HIGH-DENSITY CMOS IC PACKAGE DESIGN 309 (a) (a) (b) Fig. 8. SSN waveform and output current waveform with small load capacitance (i.e., C = 1 pf and t = 0.5 ns). The second (negative) noise peak is much larger than the first (positive) one: (a) SSN voltages and (b) output currents. TABLE I THE NOISE PEAK VALUES OF FIG.8.THE PARENTHESIS VALUES OF THE FIRST PEAK MEANS THE VALUES CALCULATED WITH (13) Thus (19) gives the minimum load capacitance for nonoscillating within an input rise time for a given and a given. (b) Fig. 9. Definitions of the current differences and the time differences for the SSN analysis due to the second (negative) noise peak. Alternatively, if the load capacitance is given, the inductance must meet (19). Given the device and inductance, the load capacitance requirements with the rise time variations are shown in Fig. 10. Clearly, for a large inductance, the capacitance size must be increased. The design procedures are summarized in Fig. 11. Following the design procedures, for example, for 0.5 ns with 10 nh and (thus ), must be larger than 5.47 pf. Thus 1 pf of Fig. 8 should be replaced by a value greater than 5.47 pf. The verification with HSPICE simulation is shown in Fig. 12. It is clearly shown that the largest SSN happens in the first noise peak if the load capacitance ( ) is larger than the 5.47 pf (i.e., 5.5 and 6 pf). The second or third noise peaks are smaller than the first one which is accurately determined by using (13). In summary, (13) in Section IV and (19) in this section are extremely valuable design equations because they can provide the circuit designers with an accurate design methodology to meet their design goal as well as insight into SSN and I/O device

310 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 23, NO. 2, MAY 2000 (a) Fig. 10. Minimum load capacitance (C ) requirements for different inductances (L ) and rise times to meet the minimum SSN. (b) Fig. 12. Verification of load capacitance value (C ) determination with SPICE simulation: negative peak or next positive peak is definitely smaller than the first positive peak noise for C > 5:47 pf (i.e., 5.5 and 6 pf) of the given example: (a) SSN voltage and (b) output currents. Fig. 11. Design procedures for optimal IC package design. size. That is, circuit designers can accurately predict the SSN noise of their circuits by using (13) and therefore improve upon their design by using both (13) and (19). VI. CONCLUSION A new simultaneous switching noise model was developed. The model consists of the transistor, ground inductance, and load capacitance effects simultaneously. Unlike the conventional models where the maximum output current slew rate is determined in the time interval between and, the slew rate was determined in the shorter time interval near the, by employing the alpha-power law for submicron transistor drain current. Thus, it is more accurate than conventional models. Since the oscillation of ground current was analyzed with device parameters as well as package parameters, the device parameters and package parameters can be accurately determined. Thus the optimal package design can be achieved with the proposed design methodology and model. The model was verified with a general-purpose circuit simulator, HSPICE. The model shows excellent agreements within about a 5% margin of error. A package design methodology was presented by using the developed model. The design methodology to minimize the SSN can be directly used in the industry for advanced CMOS VLSI circuits and package designs. APPENDIX A DERIVATION OF THE MAXIMUM SSN The drain current at the saturation region is approximately given by - (A1)

EO et al.: HIGH-SPEED AND HIGH-DENSITY CMOS IC PACKAGE DESIGN 311 where is the SSN voltage. Note that the dimension of must be considered not to be but.in addition, is nearly maximum at. Thus, the drain currents at the is (A2) Since most of the CMOS circuit s switching threshold voltage is designed to be one half of, CMOS circuit s switching threshold voltage can be assumed to be Then, the noise signal at is (A3) where the is equal to the of (A9) and the is the extrapolated time from the slew rate Note that is negligibly small for large. However, small (less than 1 ns) has the following empirical relationship: (B3) (B4) Similarly, the positive noise peak can be determined by replacing. Since is the positive peak to negative peak time of the sinusoidal current, in (B2). Thus the second peak noise becomes Now plugging (A4) into (A1) results in (A4) (B5) (A5) Then defining the current difference in the time interval between and rather than that of to gives Since the maximum SSN for can be modeled (A6) simultaneous switching gates combining (A2) (A6) with (A7), SSN can be yielded as Finally rearranging (A8) it can be rewritten as follows: (A7) (A8) (A9) where is the value near the switching threshold voltage ( ) of the gate. APPENDIX B DERIVATION OF THE SSN DUE TO SECOND NOISE PEAK (NEGATIVE NOISE PEAK) The current variations between the positive-peak current and the negative-peak current can be rewritten from Fig. 9(a) as follows: (B1) where and is a period of the RLC circuit. Then the negative noise peak becomes (B2) Since the period of oscillation is given by the second noise peak can be determined from (B5) and (B6) REFERENCES (B6) (B7) [1] M. Hatamian, L. A. Hornak, E. E. Little, S. K. Tewksbury, and P. Franzon, Fundamental interconnect issues, AT&T Tech. J., vol. 66, no. 4, pp. 13 30, July 1987. [2] A. N. Saxena, Interconnect for the 90s: Alumimum-based multilevel interconnects and future directions, in Proc. IEDM 1992 Short Course: Interconnect 1990 s, San Jose, CA, 1992. [3] R. Evans and M. Tsuk, Modeling and measurement of a high-performance computer power distribution system, IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 17, pp. 467 471, Nov. 1994. [4] A. Vaidyanath, B. Thoroddsen, and J. L. Prince, Effect of CMOS driver loading conditions on simultaneous switching noise, IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 17, pp. 1724 1728, Nov. 1991. [5] S. R. Vemuru, Accurate simultaneous switching noise estimation including velocity-saturation effect, IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 19, pp. 344 349, May 1996. [6] R. Senthinathan et al., Electrical package requirements for low-voltage Ics-3.3 V high-performance CMOS devices as a case study, IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 17, pp. 493 503, Nov. 1994. [7] A. J. Rainal, Computing inductive noise of CMOS drivers, IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 19, pp. 789 802, Nov. 1996. [8] K. Bathey, M. Swaminathan, L. D. Smith, and T. J. Cockerill, Noise computation in single chip packages, IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 19, pp. 350 360, May 1996. [9] J.-G. Yook et al., Computation of switching noise in printed circuit boards, IEEE Trans. Comp., Packag., Manufact. Technol. A, vol. 20, pp. 64 75, Mar. 1997. [10] T. J. Gabara et al., Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers, IEEE J. Solid State Circuits, vol. 32, pp. 407 418, Mar. 1997. [11] H. I. Hanafi et al., Design and characterization of a CMOS off-chip driver/receiver with reduced power-supply disturbance, IEEE J. Solid State Circuits, vol. 27, pp. 783 791, May 1992. [12] R. Senthinathan and J. L. Prince, Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise, IEEE J. Solid State Circuits, vol. 28, pp. 1383 1388, Dec. 1993.

312 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 23, NO. 2, MAY 2000 [13] Y. Yang and J. R. Brews, Design trade-offs for the last stage of an unregulated, long-channel CMOS off-chip driver with simultaneous switching noise and switching time consideration, IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 19, pp. 481 486, Aug. 1996. [14] Y. Yang and J. R. Brews, Design for velocity saturated, short-channel CMOS drivers with simultaneous switching noise and switching time considerations, IEEE J. Solid State Circuits, vol. 31, pp. 1357 1360, Sept. 1996. [15] D. A. Secker and J. L. Prince, Effects and modeling of simultaneous switching noise for BiCMOS OFF-chip drivers, IEEE Comp., Packag. Manufact. Technol. B, vol. 19, pp. 473 480, Aug. 1996. [16] Y. Yang and J. R. Brews, Guidelines for high-performance electronic package interconnections-approach for strong coupling, IEEE Trans. Comp., Packag., Manufact. Technol. B., vol. 19, pp. 372 381, May 1996. [17] T. Sakurai and A. Newton, Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas, IEEE J. Solid State Circuits, vol. 25, pp. 549 584, Apr. 1990. [18] J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits. Reading, MA: Addison-Wesley, 1988, ch. 4, pp. 158 277. [19] M. E. Van Valkenburg, Network Analysis. Englewood Cliffs, NJ: Prentice Hall, 1974, ch. 6, pp. 139 163. [20] P. Larsson, Resonance and damping in CMOS circuits with on-chip decoupling capacitance, IEEE Trans. Circuits Syst., vol. 45, pp. 849 858, Aug. 1988. Yungseon Eo (M 83) received the B.S. and M.S. degrees in electronic engineering from Hanyang University, Seoul, Korea, in 1983 and 1985, respectively, and the Ph.D. degree in electrical engineering from the University of Florida, Gainesville, in 1993. From 1986 to 1988, he was with the Korea Telecommunication Authority Research Center, Seoul, where he performed telecommunication network planning and software design. From 1993 to 1994, he performed s-parameter-based BJT device characterization and modeling for the high-speed circuit design at Applied Micro Circuits Corp., San Diego, CA. From 1994 to 1995, he worked at the Research and Development Center, LSI Logic Corporation, Santa Clara, CA, where he worked in the areas of signal integrity characterization and modeling of high-speed CMOS circuits and interconnects. Since 1995, he has been with the Department of Electronic Engineering, Hanyang University, Ansan, Korea, as an Assistant Professor. His research interests are high-frequency characterization and modeling of integrated circuits and interconnects, and high-speed VLSI circuit packaging. Ju Young Jeong (M 82) was born in Seoul, Korea in 1958. He received the B.S. degree in electronic engineering from Sogang University, Seoul, in 1982, the M.S. degree in electrical engineering from the Florida Institute of Technology, Melbourne, in 1984, and the Ph.D. degree in electrical engineering from Rensselaer Polytechnic Institute, Troy, NY, in 1990. From 1990 to 1991, he was with Samsung Advanced Institute of Technology, Kihung, Korea, where he developed low temperature electronic devices. From 1991 to 1994, he was with Pan Korea Corporation as a Director of Research and Development. In 1995, he joined the University of Suwon, Kyungki-do, Korea, as an Assistant Professor of electronic engineering. His current research interests include submicron MOSFET device fabrication technique and related physics and flat panel plasma display driving system. Oh-Kyong Kwon (S 83 M 88) received the B.S. degree in electronic engineering from Hanyang University, Seoul, Korea, in 1978 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, in 1986 and 1988, respectively. From 1987 to 1992, he was with the Semiconductor Process and Design Center, Texas Instruments Inc., Dallas, TX, where he was engaged in the development of multichip module (MCM) technologies and smart power integrated circuit technologies. In 1992, he joined Hanyang University, Seoul, as an Assistant Professor in the Department of Electronic Engineering and was promoted to an Associate Professor in 1996. His research interests include interconnect and electrical noise modeling for system-level integration, wafer-scale chip size packages, smart power integrated circuit technologies and the driving methods and circuits for flat panel displays. He has authored and coauthored more than 50 papers in international journals and 28 U.S. patents. Dr. Kwon was an IEDM Subcommittee Member on solid state devices from 1997 to 1998 and Technical Program Co-Chair of the 1999 International Conference on VLSI and CAD. William R. Eisenstadt (S 78 M 84 SM 92) received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1979, 1981, and 1986, respectively. In 1984, he joined the faculty of the University of Florida, Gainesville, where he is now an Associate Professor. His research is concerned with highfrequency characterization, simulation, and modeling of integrated circuit devices, packages, and interconnect. In addition, he is interested in large-signal microwave-circuit and analog-circuit design. Dr. Eisenstadt received the NSF Presidential Young Investigator Award in 1985.