ENGR 303 Introduction to Logic Design Lecture 3. Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

Similar documents
Digital Design 2. Logic Gates and Boolean Algebra

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010

CPE100: Digital Logic Design I

Logic Design Combinational Circuits. Digital Computer Design

Digital Logic & Computer Design CS Professor Dan Moldovan Spring Copyright 2007 Elsevier 2-<101>

Chapter 2. Introduction. Chapter 2 :: Topics. Circuits. Nodes. Circuit elements. Introduction

Administrative Notes. Chapter 2 <9>

COSC3330 Computer Architecture Lecture 2. Combinational Logic

This form sometimes used in logic circuit, example:

211: Computer Architecture Summer 2016

CPE100: Digital Logic Design I

Digital Fundamentals

Chapter 7 Combinational Logic Networks

Introduction. 1854: Logical algebra was published by George Boole known today as Boolean Algebra

Chapter 2: Princess Sumaya Univ. Computer Engineering Dept.

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions

Theorem/Law/Axioms Over (.) Over (+)

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC.

CS 226: Digital Logic Design

Why digital? Overview. Number Systems. Binary to Decimal conversion

12/31/2010. Overview. 05-Boolean Algebra Part 3 Text: Unit 3, 7. DeMorgan s Law. Example. Example. DeMorgan s Law

Goals for Lecture. Binary Logic and Gates (MK 2.1) Binary Variables. Notation Examples. Logical Operations

Boolean Algebra and Logic Simplification

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata

EXPERIMENT #4: SIMPLIFICATION OF BOOLEAN FUNCTIONS

LOGIC GATES (PRACTICE PROBLEMS)

Combinational Logic Circuits Part II -Theoretical Foundations

Digital Logic Design. Malik Najmus Siraj

Computer Organization I. Lecture 13: Design of Combinational Logic Circuits

Lecture 4: More Boolean Algebra

Chapter 2: Switching Algebra and Logic Circuits

EEE130 Digital Electronics I Lecture #4

CS 121 Digital Logic Design. Chapter 2. Teacher Assistant. Hanin Abdulrahman

L4: Karnaugh diagrams, two-, and multi-level minimization. Elena Dubrova KTH / ICT / ES

UNIT 5 KARNAUGH MAPS Spring 2011

Functions. Computers take inputs and produce outputs, just like functions in math! Mathematical functions can be expressed in two ways:

Textbook: Digital Design, 3 rd. Edition M. Morris Mano

Working with Combinational Logic. Design example: 2x2-bit multiplier

ELCT201: DIGITAL LOGIC DESIGN

Computer Organization I

Standard Expression Forms

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

Digital Circuit And Logic Design I. Lecture 3

Logical Design of Digital Systems

MC9211 Computer Organization

Prove that if not fat and not triangle necessarily means not green then green must be fat or triangle (or both).

Chapter 4 Optimized Implementation of Logic Functions

The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

Unit 2 Session - 6 Combinational Logic Circuits

Combinational logic. Possible logic functions of two variables. Minimal set of functions. Cost of different logic functions.

Chapter 2 : Boolean Algebra and Logic Gates

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms

WEEK 2.1 BOOLEAN ALGEBRA

Digital Logic Design ABC. Representing Logic Operations. Dr. Kenneth Wong. Determining output level from a diagram. Laws of Boolean Algebra

for Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid

CHAPTER1: Digital Logic Circuits Combination Circuits

CHAPTER 3 LOGIC GATES & BOOLEAN ALGEBRA

14:332:231 DIGITAL LOGIC DESIGN

II. COMBINATIONAL LOGIC DESIGN. - algebra defined on a set of 2 elements, {0, 1}, with binary operators multiply (AND), add (OR), and invert (NOT):

Mark Redekopp, All rights reserved. Lecture 5 Slides. Canonical Sums and Products (Minterms and Maxterms) 2-3 Variable Theorems DeMorgan s Theorem

Basic Gate Repertoire

Chapter 2 Boolean Algebra and Logic Gates

Lecture 3. Title goes here 1. level Networks. Boolean Algebra and Multi-level. level. level. level. level

Fundamentals of Computer Systems

Simplifying Logic Circuits with Karnaugh Maps

Cover Sheet for Lab Experiment #3

Chapter 7 Logic Circuits

Minimization techniques

Part 1: Digital Logic and Gates. Analog vs. Digital waveforms. The digital advantage. In real life...

ﻮﻧﺭﺎﮐ ﺔﺸﻘﻧ ﺎﺑ ﻱﺯﺎﺳ ﻪﻨﻴﻬﺑ

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University

CMSC 313 Lecture 16 Postulates & Theorems of Boolean Algebra Semiconductors CMOS Logic Gates

Combinational Logic. Review of Combinational Logic 1

Logic Gate Level. Part 2

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

Chapter 2 Part 7 Combinational Logic Circuits

Chapter 2 (Lect 2) Canonical and Standard Forms. Standard Form. Other Logic Operators Logic Gates. Sum of Minterms Product of Maxterms

Learning Objectives. Boolean Algebra. In this chapter you will learn about:

Logic Design. Chapter 2: Introduction to Logic Circuits

Digital Logic Design. Combinational Logic

Karnaugh Maps (K-Maps)

Possible logic functions of two variables

CHAPTER III BOOLEAN ALGEBRA

Optimizations and Tradeoffs. Combinational Logic Optimization

Part 5: Digital Circuits

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

CHAPTER 7 MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES

Chapter 2 Combinational Logic Circuits

Lecture 2 Review on Digital Logic (Part 1)

Combinational Logic Design Principles

Combinatorial Logic Design Principles

Chapter 3 Combinational Logic Design

Gate-Level Minimization

Midterm1 Review. Jan 24 Armita

Standard & Canonical Forms

ECE/Comp Sci 352 Digital System Fundamentals Quiz # 1 Solutions

ENG2410 Digital Design Combinational Logic Circuits

CSE 140, Lecture 2 Combinational Logic CK Cheng CSE Dept. UC San Diego

Logic Gates and Boolean Algebra

Transcription:

Introduction to Logic Design Lecture 3 Dr. Chuck rown Engineering and Computer Information Science Folsom Lake College

Outline for Todays Lecture Logic Circuits SOP / POS oolean Theorems DeMorgan s Theorem <2>

Recap - Circuits Nodes Inputs:,, C Outputs:, Z E1 n1 Internal: n1 E3 Circuit elements C E2 Z E1, E2, E3 Each a circuit <3>

Recap - Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory Outputs determined by previous and current values of inputs inputs functional spec timing spec outputs <4>

Rules of Combinational Composition Every element is combinational Every node is either an input or connects to exactly one output The circuit contains no cyclic paths Example: <5>

oolean Equations Functional specification of outputs in terms of inputs Example: S = F(,, C in ) C out = F(,, C in ) S C L C C out in S = C in C out = + C in + C in <6>

Some Definitions Complement: variable with a bar over it,, C Literal: variable or its complement,,,, C, C Implicant: product of literals C, C, C Minterm: product that includes all input variables C, C, C Maxterm: sum that includes all input variables (++C), (++C), (++C) <7>

Sum-of-Products (SOP) Form ll equations can be written in SOP form Each row has a minterm minterm is a product (ND) of literals Each minterm is TRUE for that row (and only that row) Form function by ORing minterms where the output is TRUE Thus, a sum (OR) of products (ND terms) 0 0 0 0 1 1 1 0 0 1 1 1 minterm minterm name m 0 m 1 m 2 m 3 = F(, ) = <8>

Sum-of-Products (SOP) Form ll equations can be written in SOP form Each row has a minterm minterm is a product (ND) of literals Each minterm is TRUE for that row (and only that row) Form function by ORing minterms where the output is TRUE Thus, a sum (OR) of products (ND terms) 0 0 0 0 1 1 1 0 0 1 1 1 minterm minterm name m 0 m 1 m 2 m 3 = F(, ) = <9>

Sum-of-Products (SOP) Form ll equations can be written in SOP form Each row has a minterm minterm is a product (ND) of literals Each minterm is TRUE for that row (and only that row) Form function by ORing minterms where the output is TRUE Thus, a sum (OR) of products (ND terms) 0 0 0 0 1 1 1 0 0 1 1 1 minterm minterm name m 0 m 1 m 2 m 3 = F(, ) = + = Σ(1, 3) <10>

Product-of-Sums (POS) Form ll oolean equations can be written in POS form Each row has a maxterm maxterm is a sum (OR) of literals Each maxterm is FLSE for that row (and only that row) Form function by NDing the maxterms for which the output is FLSE Thus, a product (ND) of sums (OR terms) 0 0 0 0 1 1 1 0 0 1 1 1 maxterm + + + + = F(, ) = ( + )( + ) = Π(0, 2) maxterm name M 0 M 1 M 2 M 3 <11>

oolean Equations Example ou are going to the cafeteria for lunch ou won t eat lunch (E) If it s not open (O) or If they only serve corndogs (C) Write a truth table for determining if you will eat lunch (E). O C E 0 0 0 1 1 0 1 1 <12>

oolean Equations Example ou are going to the cafeteria for lunch ou won t eat lunch (E) If it s not open (O) or If they only serve corndogs (C) Write a truth table for determining if you will eat lunch (E). O C E 0 0 0 1 1 0 1 1 0 0 1 0 <13>

SOP & POS Form SOP sum-of-products O C E 0 0 0 1 1 0 1 1 minterm O C O C O C O C POS product-of-sums O C E 0 0 0 1 1 0 1 1 maxterm O + C O + C O + C O + C <14>

SOP & POS Form SOP sum-of-products O C E 0 0 0 0 1 0 1 0 1 1 1 0 minterm O C O C O C O C E = OC = Σ(2) POS product-of-sums O C E 0 0 0 1 1 0 1 1 0 0 1 0 maxterm O + C O + C O + C O + C E = (O + C)(O + C)(O + C) = Π(0, 1, 3) <15>

oolean Theorems <16>

oolean Theorems ( ) Note: T8 differs from traditional algebra: OR (+) distributes over ND ( ) <17>

Simplifying oolean Equations Example 1: = + <18>

Simplifying oolean Equations Example 1: = + = ( + ) T8 = (1) T5 = T1 <19>

DeMorgan s Theorem The complement of the product of all the terms is equal to the sum of the complement of each term. That is, a NND gate is equivalent to an OR gate with inverted inputs = = + Likewise, the complement of the sum of all the terms is equal to the product of the complement of each term Or, a NOR gate is equivalent to an ND gate with inverted inputs = + = <20>

DeMorgan s -> ubble Pushing ackward: Gate changes dds bubbles to inputs Forward: Gate changes dds bubble to output <21>

DeMorgan s - > ubble Pushing What is the oolean expression for this circuit? C D <22>

DeMorgan s -> ubble Pushing What is the oolean expression for this circuit? C D = + CD <23>

DeMorgan s -> Procedure egin at output, then work toward inputs Push bubbles on final output back Draw gates in a form so bubbles cancel C D <24>

DeMorgan ubble Pushing Example C D <25>

DeMorgan ubble Pushing Example no output bubble C D <26>

DeMorgan ubble Pushing Example no output bubble C D bubble on input and output C D <27>

DeMorgan ubble Pushing Example no output bubble C D C D C D no bubble on input and output = C + D bubble on input and output <28>