Homework Assignment #3 EE 477 Spring 2017 Professor Parker Note:! " = $ " % &' ( ) * ),! + = $ + % &' (, *,, -.. = 1.8 -, 345 = 0 - Question 1: a) (8%) Define the terms V OHmin, V IHmin, V ILmax and V OLmax, and arrange them from lowest value to highest value. V OHmin : Lowest output voltage representing high output (logic 1) V OLmax : Highest output voltage representing low output (logic 0) V IHmin : Lowest input voltage recognized as high input (logic 1) V ILmax : Highest input voltage recognized as low input (logic 0) - 7*89' - ;*89' - ;<8=" - 7<8=" b) (8%) Suppose you want to achieve maximum noise margin and you can change each of the above values individually while keeping the others fixed. Which ones would you increase and which ones would you decrease? Example: If V IHmin, V ILmax and V OLmax are constant, V OHmin should increase/decrease? (Do this for all 4) So to increase noise margins, we need: V OHmin : Increase V OLmax : Decrease V IHmin : Decrease V ILmax : Increase >? < = - 7<8=" - ;<8=" and >? * = - ;*89' - 7*89' c) (4%) If you could get an ideal inverter in this technology, what would be the numerical values for V OHmin, V IHmin, V ILmax and V OLmax? Hint: An ideal inverter voltage transfer curve looks like a unit step. V OHmin = Vdd = 1.8 V V OLmax = Gnd = 0 V V IHmin = V ILmax = Vdd/2 = 0.9 V (of course V IHmin would be slightly greater than.9 and V ILmax would be slightly less to avoid confusion). Note: For this ideal inverter, NMH = NML = Vdd/2, which is the maximum possible.
Question 2: The diagram shows a 2-input NOR gate. a) (4%) Identify the inputs setting up your worst case rise and fall times by discharging/charging all transistors. Worst case rise time setup: A = 1, B = 0 (Discharge all caps) Worst case fall time setup: A = 0, B = 0 (Charge all caps) Remember that setup is the stage before the transition. b) (8%) Then, identify the input transition leading to worst case rise time and the one leading to worst case fall time. Explain why you chose these transitions. Your answer for each case should be a single transition, like you would do in Cadence. 1 input should be fixed while the other changes value. Worst case rise time transition: A transitions 1->0, B fixed at 0 Initially all capacitances were discharged. When A goes to 0, all capacitances get charged. Worst case fall time transition: A transitions 0->1, B fixed at 0 Initially all capacitances were charged. When A goes to 1, all capacitances get discharged. These transitions are chosen because they lead to maximum charge displacement, i.e. all capacitors change their state. So these give the worst case times. Note: The worst case transitions simply switch between the worst case rise and fall time cases. This is generally true for 2-input gates.
Question 3: Consider the logic function X = ~[(A.B)+(C+D).(E+F+G)] realized using this compound gate. a) (10%) Locate all the drain and source capacitances of all the NMOS and PMOS which will be charged/discharged.
b) (10%) Identify the critical path leading to worst case rise time. Clearly mention the logic level of each input. Your answer should only give the final logic levels of all inputs, transition is not required. Do all capacitors get charged? A = C = Vdd (NMOS on) B = D = E = F = G = Gnd (PMOS on) The equivalent circuit is shown below where transistors that are off have been removed. Note: All capacitors are charged since a path exists from all of them to Vdd There is no path connecting anything to Gnd
Note: Some of you may have done this: A = D = Vdd (NMOS on) B = C = E = F = G = Gnd (PMOS on) Based on what you have learnt so far, this is also correct since length of resistive path is maximum and all capacitances get charged. You ll get full marks if you have done this. (In reality, only the 1 st answer gives the worst case, not the 2 nd one. This can be shown using Elmore Delay calculations, which is not part of the present scope.)
c) (10%) Repeat part b) for worst case fall time. Do all capacitors get discharged? A = B = C = Vdd (NMOS on) D = E = F = G = Gnd (PMOS on) The equivalent circuit is shown below where transistors that are off have been removed. Note: All capacitors are discharged since a path exists from all of them to Gnd There is no path connecting anything to Vdd Just like for rise time, you can switch the results to make PMOS C on and NMOS D on. This is correct based on what you ve learnt so far.
Question 4: The first diagram shows a Cadence inverter setup to do DC analysis, as shown in the discussion classes. Both the NMOS and PMOS have width = 300 nm and length = 200 nm. The second diagram shows results of the DC analysis: Vout vs Vin (top) and current vs Vin (bottom). Note that Vin = 678 mv corresponds to Vout = Vdd/2 = 900 mv. This value of Vin also gives a spike in current.
a) (2%) What region is each transistor in when Vin = 678 mv? Both transistors are in saturation. You can put values V tn = V tp = 500 mv, then compute V gs, V ds etc to verify that both are in saturation. b) (3%) What can you conclude about the relation between Kp and Kn? When both transistors are in saturation, equating current gives:! " 2 - EFG - HG I =! + 2 - FEJ - HJ I where V gate for both transistors = 0.678 V. => =>! +! " = - EFG - HG I - FEJ - HJ I =! +! " (0.678 0.5) I (1.8 0.678 0.5) I =>! +! " < 1 Note: You don t need to solve for the exact value of Kp/Kn since the threshold voltage values are just an assumption. But you should realize that Kp/Kn < 1. c) (3%) Which is greater: rise time or fall time? Since Kp < Kn, the PMOS is weaker (more resistive). So, rise time is greater. d) (6%) The beta ratio for this technology is given to be 4. How can you improve your design to make rise time and fall time almost equal? To make rise and fall time almost equal, we need Kp = Kn. So: Lengths are generally kept fixed and C ox is constant. Given: T ) T, = U = 4 So you should increase the PMOS width to 1.2 μm. $ + % &' R + S + = $ " % &' R " S " => $ + R + = $ " R " => R + R " = $ " $ + => W X = YW Z
Question 5: a) (8%) Visually inspect the Vout vs Vin curve from Q4 and estimate both the noise margins. Assume V OHmin = 1.8 V and V OLmax = 0 V. If you can t see the x-axis properly: The x-axis major markings are at every 0.3 V, starting from 0 up till 1.8. Each major interval has 5 minor markings, so each minor interval = 0.06 V. Approximate answers for noise margins are fine. The values shown are approximate. NMH = 1.8 0.76 = 1.04 V NML = 0.62 0 = 0.62 V Note: Since Kp/Kn < 1, the entire curve is shifted to the left, so NML < NMH. b) (6%) The width of the NMOS transistor is now increased from 300 nm to 600 nm. What is the effect on NMH and NML (do they increase/decrease)? Since! " = $ " % &' ( ) * ), when W n increases, Kn increases. So the ratio Kp/Kn decreases, which results in the voltage transfer curve shifting to the left even more. So NML decreases and NMH increases.
Question 6: Consider a 2-input XOR gate. It s logic equation can be written in 2 ways: Option 1: A XOR B = A.(~B) + (~A).B -> Sum-of-products uses 2-input NAND gates Option 2: A XOR B = (A + B). (~A + ~B) -> Product-of-sums uses 2-input NOR gates a) (8%) Assume beta ratio = 4 and all NMOS transistors have width = 300 nm. You need to design 2- input NAND and 2-input NOR gates so that worst case rise time = worst case fall time. Calculate the width of PMOS for the NAND and NOR. To get worst case rise time = worst case fall time, we need: R +,\] R ",\] = 4 where W p,eq and W n,eq are the PMOS and NMOS widths of the worst-case equivalent inverter (this technique was shown in the discussion). 2-input NAND: Since NMOS are in series, Assuming width of both PMOS transistors = W p : So we get: R ",\] = R " 2 R +,\] = R + = 150 4^ R + 150 = 4 => R + = _`` Za Note: A width of 150 nm is not actually allowed because it is less than the minimum width of 300 nm (for this technology). I have written W n,eq = 150 nm just to show that the series combination of 2 NMOS of width 300 nm behaves like a single equivalent NMOS of width 150 nm. This equivalent NMOS doesn t actually exist. 2-input NOR: R ",\] = R " = 300 4^ Assuming width of both PMOS transistors = W p, since PMOS are in series: So we get: R +,\] = R + 2 R + 2 300 = 4 => R + = c. Y da b) (2%) Which option of XOR is better for achieving a small design? NMOS sizes are the same for both gates, but 2-input NAND is definitely better because its PMOS size is much lower.