ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells

Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification " ROM Memories " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery (time permitting) Penn ESE 570 Spring 2018 - Khanna 2

Charge Leakage

Charge Storage and Leakage 5

Example Overview: Min Hold Time! Find min voltage value for storage node to maintain data " V x = voltage across storage capacitor! With dimensions of switch MOS and load MOS " Calculate C ext = C gb + C int = C gb + C poly + C metal " Calculate C j = junction capacitance! With max leakage value " Calculate min hold time (i.e. min time for storage capacitor to leak to min V x ) min(t hold ) = Δt = C x min I leakage max ΔV x = C x min I leakage max (V x max V x min ) Penn ESE 570 Spring 2018 - Khanna 6

Charge Sharing

Dynamic Circuit Techniques 8

Shift Register! Shift registers store and delay data! Simple design: cascade of latches D D- Latch ϕ 2 D- Latch ϕ 1 ϕ 1 D- Latch Out 9

Shift Register with Dynamic D Latches When V out(i) = 0V (or 5V) and V in(i+1) = 5V (or 0V) for i = 1,2 (stage) Charge Sharing is an issue when ϕ 1 /ϕ 2 close. 10

Charge Sharing V b >> V a 11

Charge Sharing V b >> V a 12

Charge Sharing Rule of Thumb make C out1 = 10 C in2 V b >> V a 13

Charge Sharing V b << V a 14

Charge Sharing V b << V a If V b = 0 and V a >> V b # V R C in2 C out1 + C in2 15

Charge Sharing V b << V a If V b = 0 and V a >> V b # V R C in2 C out1 + C in2 If C out1 >> C in2 # V R C in2 C out1 << 16

Charge Sharing Rule of Thumb make C out1 = 10 C in2 V b << V a If V b = 0 and V a >> V b # V R C in2 C out1 + C in2 If C out1 >> C in2 # V R C in2 C out1 << 17

Domino Logic Design Considerations

Requirements! Single transition " Once transitioned, it is done # like domino falling! All inputs at 0 during precharge " Outputs pre-charged to 1 then inverted to 0 " I.e. Inputs are pre-charge to 0! Non-inverting gates 19

Cascaded Domino CMOS Logic Gates propagating 20

Pre-charge Leakage weak keeper (W/L) p-keeper < (W/L) n-min 21

Charge Sharing within PDN 22

Charge Sharing within PDN 23

Charge Sharing within PDN 24

Charge Sharing within PDN 25

Charge Sharing within PDN 26

Charge Sharing within PDN Since all nodes are precharged there is no chargesharing. C 4 Z4 Z3 C 3 C 2 Z2 Z1 P0 C 1 Z1 = G1 + P1 * P0 Z2 = G2 + P2 * G1 + P2 * P1 * P0 = G2 + P2 * Z1 Z3 = G3 + P3 * G2 + P3 * P2 * G1 + P3 * P2 * P1 * P0 = G3 + P3 * Z2 Z4 = G4 + P4 * G3 + P4 * P3 * G2 + P4 * P3 * P2 * G1 + P4 * P3 *P1 * P0 = G4 + P4 * Z3 27

CMOS Logic! Best option in the majority of CMOS circuits! Advantages: " Noise-immunity not sensitive to k n /k p " does not involve pre-charging of nodes " dissipates no DC power " layout can be automated! Disadvantages: " Large fan-in gates lead to complex circuit structures (2N transistors) " larger parasitics " slower and higher dynamic power dissipation than alternatives " no clock and no synchronization. 28

Pseudo-nMOS/Ratioed Logic! Finds widest utility in large fan-in gates! Advantages: " Requires only N+1 transistors for N fan-in " smaller parasitics " faster and lower dynamic power dissipation than full CMOS! Disadvantages: " Noise-immunity sensitive to k n /k p " dissipates DC power when pulled down " not well-suited for automated layout " no clock and no synchronization. 29

CMOS domino-logic! Used for low-power, high-speed applications.! Advantages: " Requires N+k transistors for N fan-in (size advantages of pseudonmos) " dissipates no DC power " noise immunity not sensitive to k n /k p " use of clocks enables synchronous operation! Disadvantages: " Relies on storage on soft nodes " will require thorough simulation at all the process corners to insure proper operation " some of the speed advantage over static gates is diminished by the required pre-charge (pre-discharge) time 30

Memory Overview

CPU Memory Hierarchy CPU Chip L1 on-cpu cache 1k to 64 k SRAM (register file) off-chip cache memory L2 L3 L4 64k to 4M 4M to 32M 8M SRAM or DRAM 32

Locality and Cacheing! Memory hierarchies exploit locality by cacheing (keeping close to the processor) data likely to be used again! This is done because we can build " large, slow memories OR " small, fast memories BUT " we can t build large, fast memories! If hierarchy works, we get the illusion of SRAM access time with disk based memory capacity. " SRAM (static RAM) -- 5-20 ns access time, very expensive (on-cpu faster) " DRAM (dynamic RAM) -- 60-100 ns, cheaper " Disk -- access time measured in milliseconds, very cheap 33

Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM Penn ESE 570 Spring 2018 - Khanna

Memory Architecture: Core M bits M bits N Words S 0 S 1 S 2 S N-2 S N_1 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell A 0 A 1 A K-1 Decoder S 0 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell Input-Output (M bits) Input-Output (M bits) N words => N select signals Too many select signals Decoder reduces # of select signals K = log 2 N Penn ESE 570 Spring 2018 - Khanna

Memory Architecture: Decoders M bits M bits N Words S 0 S 1 S 2 S N-2 S N_1 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell A 0 A 1 A K-1 Decoder S 0 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell Input-Output (M bits) Input-Output (M bits) N words => N select signals Too many select signals Decoder reduces # of select signals K = log 2 N Penn ESE 570 Spring 2018 - Khanna

Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K A K+1 A L-1 Row Decoder Word Line Sense Amplifiers / Drivers M.2 K Amplify swing to rail-to-rail amplitude A 0 A K-1 Column Decoder Selects appropriate word Input-Output (M bits) Penn ESE 570 Spring 2018 - Khanna

Latches/Register Can Store a State! Build master-slave register from pair of latches! Control with non-overlapping clocks Penn ESE 570 Spring 2018 - Khanna 38

ROM Memories Penn ESE 570 Spring 2018 - Khanna 39

MOS NOR ROM Pull-up devices WL[0] WL[1] GND WL[2] WL[3] GND BL[0] BL[1] BL[2] BL[3] Penn ESE 570 Spring 2018 - Khanna

MOS NOR ROM Pull-up devices WL[0] WL[1] 1 0 1 1 GND WL[2] GND WL[3] BL[0] BL[1] BL[2] BL[3] Penn ESE 570 Spring 2018 - Khanna

MOS NOR ROM Pull-up devices WL[0] WL[1] 1 0 0 1 1 1 1 0 GND WL[2] 1 0 1 0 GND WL[3] 1 1 1 1 BL[0] BL[1] BL[2] BL[3] Penn ESE 570 Spring 2018 - Khanna

MOS NAND ROM BL[0] BL[1] BL[2] BL[3] Pull-up devices WL[0] WL[1] WL[2] WL[3] All word lines high by default with exception of selected row Penn ESE 570 Spring 2018 - Khanna

MOS NAND ROM Pull-up devices WL[0] WL[1] 0 BL[0] BL[1] BL[2] BL[3] 1 0 0 WL[2] WL[3] All word lines high by default with exception of selected row Penn ESE 570 Spring 2018 - Khanna

MOS NAND ROM Pull-up devices WL[0] WL[1] WL[2] WL[3] 0 1 0 0 BL[0] BL[1] BL[2] BL[3] 1 0 0 0 0 1 1 0 1 0 0 0 All word lines high by default with exception of selected row Penn ESE 570 Spring 2018 - Khanna

Non-Volatile Memory ROM PseudonMOS NOR gate 49

Contact-Mask Programmable ROM 50

Contact-Mask Programmable ROM 51

Read-Write Memories (RAM)! Static (SRAM) " Data stored as long as supply is applied " Large (6 transistors/cell) " Fast " Differential! Dynamic (DRAM) " Periodic refresh required " Small (1-3 transistors/cell) " Slower " Single ended Penn ESE 570 Spring 2018 - Khanna

6T SRAM Cell! Cell size accounts for most of memory array size! 6T SRAM Cell " Used in most commercial chips " Data stored in cross-coupled inverters! Read: " Precharge BL, BL BL bit " Raise WL word WL! Write: " Drive data onto BL, BL " Raise WL BL bit_b 53

6-transistor CMOS SRAM Cell WL M2 M4 M5 Q Q M6 M1 M3 BL BL Penn ESE 570 Spring 2018 - Khanna

6-transistor CMOS SRAM Cell WL Assume 1 is stored (Q=1) M5 M2 Q 0 M4 Q 1 M6 M1 M3 BL BL Penn ESE 570 Spring 2018 - Khanna

CMOS SRAM Analysis (stored 1) WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 M1 C bit C bit Penn ESE 570 Spring 2018 - Khanna

6-transistor CMOS SRAM Cell WL Assume 1 is stored (Q=1) Read Operation: - First bitlines get VDD precharged high (Vdd) - Then wordline goes high (Vdd) BL M5 M2 Q 0 M1 M4 M3 Q 1 M6 BL VDD Penn ESE 570 Spring 2018 - Khanna

CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit Penn ESE 570 Spring 2018 - Khanna

CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit ( ) 2 = k n,m1 ( V Tn )ΔV ΔV 2 k n,m5 ΔV V Tn 2 Penn ESE 570 Spring 2018 - Khanna

CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit k n,m 1 k n,m 5 = W L W L 1 5 = ( ΔV V Tn ) 2 ( V Tn )ΔV ΔV 2 2 Penn ESE 570 Spring 2018 - Khanna

CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit k n,m 1 k n,m 5 = W L W L Penn ESE 570 Spring 2018 - Khanna 1 5 = ( ΔV V Tn ) 2 ( V Tn )ΔV ΔV 2 2 ΔV =V Tn W L W L 1 5 = ( 2V Tn ) 2 ( 1.5V Tn )V Tn

CMOS SRAM Analysis (Read) 1.2 1 Voltage Rise (V) 0.8 0.6 0.4 0.2 0 0 0.5 1 1.2 1.5 2 Cell Ratio (CR) 2.5 3

CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit Penn ESE 570 Spring 2018 - Khanna

6-transistor CMOS SRAM Cell WL Assume 1 is stored (Q=1) Write Operation: - Want to write a 0 VDD - First drive bitlines with input data - Then wordline goes high (Vdd) BL M5 M2 Q 0 M1 M4 M3 Q 1 M6 BL 0 Penn ESE 570 Spring 2018 - Khanna

CMOS SRAM Analysis (Write) VDD WL M4 M5 0 Q = 0 Q = 1 1 M6 M1 VDD BL = 1 0 BL = 0 Penn ESE 570 Spring 2018 - Khanna

CMOS SRAM Analysis (Write) VDD WL M4 M5 0 Q = 0 Q = 1 1 M6 M1 VDD BL = 1 0 BL = 0 ( ) 2 = k n,m 4 ( V Tp )V Q V Q k n,m 6 V Tn 2 2 Penn ESE 570 Spring 2018 - Khanna

CMOS SRAM Analysis (Write) VDD WL M4 M5 0 Q = 0 Q = 1 1 M6 M1 VDD BL = 1 0 BL = 0 k n,m 4 k n,m 6 = ( V Tn ) 2 ( V Tp )V Q V 2 Q 2 Penn ESE 570 Spring 2018 - Khanna

CMOS SRAM Analysis (Write) VDD WL M5 0 Q = 0 M4 Q = 1 1 M6 PR = W 4 L 4 W 6 L 6 M1 VDD BL = 1 0 BL = 0 k n,m 4 k n,m 6 = ( V Tn ) 2 ( V Tp )V Q V 2 Q 2 Penn ESE 570 Spring 2018 - Khanna V Q =V Tn k n,m 4 k n,m 6 = ( V Tn ) 2 ( V Tp )V Tn V 2 Tn 2

CMOS SRAM Analysis (Write) PR = W 4 L 4 W 6 L 6

CMOS SRAM Analysis (Write) VDD WL M5 0 Q = 0 M4 Q = 1 1 M6 PR = W 4 L 4 W 6 L 6 M1 VDD BL = 1 0 BL = 0 Penn ESE 570 Spring 2018 - Khanna

DRAM! Smaller than SRAM! Require data refresh to compensate for leakage 72

3-Transistor DRAM Cell BL1 BL2 WWL RWL WWL RWL M1 X M2 M3 X BL1 -V T C S BL2 -V T ΔV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL -V Tn

1-Transistor DRAM Cell BL WL WL Write "1" Read "1" M1 C S X GND V T C BL BL /2 sensing /2 Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance C ΔV V BL V ( PRE V BIT V ) S = = ----------------------- PRE C S + C BL Voltage swing is small; typically around 250 mv.

DRAM Cell Observations! 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out! DRAM memory cells are single ended in contrast to SRAM cells! The read-out of the 1T DRAM cell is destructive " Read and refresh operations are necessary for correct operation! Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design! When writing a 1 into a DRAM cell, a threshold voltage is lost " This charge loss can be circumvented by bootstrapping the word lines to a higher value than

Idea! Memory for compact state storage! Share circuitry across many bits " Minimize area per bit # maximize density! Aggressively use: " Pass transistors, Ratioing " Precharge, Amplifiers to keep area down Penn ESE 570 Spring 2018 - Khanna 76

Admin! Homework 7 due Thursday! Final Project " Design and layout memory " Handout posted before Thursday class " Due 4/24 (last day of class) " Everyone gets an extension until 5/4 " Keep in mind our final exam is on 4/30 " Leave time to study! Penn ESE 570 Spring 2018 - Khanna 77