Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Chapter 7 Combinational Logic Networks SKEE223 Digital Electronics Mun im/rif/izam KE, Universiti Teknologi Malaysia October 30, 205
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Overview Overview 2 Design Example 3 Design Example 2 4 Universal Gates 5 NND-NND Networks
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Design Process Conceptualize Truth Table Equations Schematic Get the big picture or overall view. During this step, determine the number of inputs and outputs from the specifications. Obtain the truth table for the outputs based on their relationship to the input. Simplify the oolean expression for each output. Use Karnaugh maps or oolean algebra. Draw the circuit diagram that represents the simplified oolean expressions. Verify the design by analyzing or simulating the circuits.
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Design Example Majority decider circuit Problem: Implement a three-input majority decider circuit. Understand the Specification majority decider circuit outputs a if the majority of its inputs are. or a 3-input circuit, the output is if 2 or 3 inputs are. Optional Sketch a top-level block diagram showing all inputs an outputs. Label all inputs and outputs. C Majority decider M
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Design Example Majority decider circuit 2 Truth Table Carefully fill in the truth table. C M 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Design Example Majority decider circuit 3 Equations Get the equations using K-map (recommended) or oolean algebra. C 0 00 0 0 0 0 0 C 0 C
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Design Example Majority decider circuit 4 Circuit Diagram inally, draw the circuit schematic. C M
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Design Example 2 CD to XS3 Converter Problem: Implement a CD to Excess-3 converter circuit. Understand the Specification CD and XS3 codes are 4-bit codes. We can assign CD to input and WXYZ to output. C D CD to Excess-3 Converter W X Y Z
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Design Example CD to XS3 Converter 2 Truth Table Carefully fill in the truth table. Inputs 00 - are don t cares. Input Output C D W X Y Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Design Example CD to XS3 Converter 3 Equations CD 00 0 0 00 CD 00 0 0 00 0 0 0 0 W = + C + D X = C + D + C D CD 00 0 0 00 CD 00 0 0 00 0 0 0 0 Y = CD + C D Z = D
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Design Example CD to XS3 Converter 4 Schematic Diagram C D W X Y Z
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Review of DeMorgan s Theorem = Ā + + = Ā and = Ā + + = Ā
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips DeMorgan s Theorem pplied to NND Gates + 0 0 0 0 0 0 0 0 0 0 = = +.
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips NND to Other Gates NOT ND OR
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips DeMorgan s Theorem pplied to NOR Gates + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = + =.
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips NOR to Other Gates NOT ND OR
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Pushing ubbles Pushing bubbles to the right. Pushing bubbles to the left.
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips = + C Using only NND and NOT C C C
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips = C + C + C Using only NND and NOT C C Two consecutive bubbles cancel C
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips = + C Using only NND and NOT C C C
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips NND Devices 4 3 2 0 9 8 4 3 2 0 9 8 V CC V CC GND 2 3 4 5 6 7 74x00 GND 2 3 4 5 6 7 74x0 4 3 2 0 9 8 4 3 2 0 9 8 V CC V CC GND 2 3 4 5 6 7 74x20 GND 2 3 4 5 6 7 74x30
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Using ND/OR/NOT: 3 chips Y S Ua 2 U2a 2 U2b 4 5 3 6 U3a 2 3 Y S
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips Using NND: chip only Y S Y S 2 Ub Ua 4 3 5 Uc 9 0 6 8 2 3 Ud Y S
Overview Design Example Design Example 2 Universal Gates NND-NND Networks NND Chips SKEE 223 https://www.openlearning.com/courses/skee223x