OS LSI L L Digital to Analog onverters with Serial Interface Legacy Device: otorola/reescale, The L and L are low cost 6 bit D/A converters with serial interface ports to provide communication with OS microprocessors and microcomputers. The L contains six static D/A converters; the L contains four converters. Due to a unique feature of these DAs, the user is permitted easy scaling of the analog outputs of a system. Over a to V supply range, these DAs maybe directly interfaced to OS PUs operating at V. P DIP = VP PLASTI DIP ASE 707 Direct R R Network Outputs uffered Emitter ollower Outputs Serial Data Input Digital Data Output acilitates ascading Direct Interface to OS µp Wide Operating Voltage Range:. to V Wide Operating Temperature Range: TA = 0 to Software Information is ontained in Document 6HR/AD 0 SO 0W = -6P SOG PAAGE ASE 7D LO DIAGRA Q OUT R OUT Qn Rn OUT OUT 6 P DIP = P PLASTI DIP ASE 66 SO 6W = -P SOG PAAGE ASE 7G R R R R R R R R R R R R HEX UER (INVERTING) ROSS REERENE/ORDERING INORATION PAAGE OTOROLA LANSDALE P DIP P LVP SO 0W DW L-6P P DIP P LP SO 6W DW L-P Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from L to LE. HEX LATH L * D Q D 6 IT SHIT REGISTER * Transparent Latch Page of
L, L PIN ASSIGNENTS LVP L-6P 0 Q Out 7 Q Out 9 R Out 3 6 R6 Out R Out 3 R6 Out Q Out Q6 Out Q Out 7 Q6 Out R Out R Out R Out 6 R Out Q3 Out 6 3 Q Out Q3 Out 6 Q Out R3 Out 7 R Out R3 Out 7 R Out Q Out 3 Q Out 9 L 9 L N N LP L-P 6 Q Out 3 Q Out R Out 3 R Out R Out 3 R Out Q Out Q Out Q Out 3 Q Out R Out R3 Out R Out R3 Out 6 9 Q3 Out 6 Q3 Out 7 L 7 L N 9 N N = NO ONNETION Page of
L, L AXIU RATINGS* (Voltages referenced to ) Parameter Symbol Value Unit D Supply Voltage 0. to + V Input Voltage, All Inputs Vin 0. to + 0. V D Input urrent, per Pin I ± ma Power Dissipation (Per Output) TA = 70, TA =, Power Dissipation (Per Package) TA = 70, TA =, POH PD 30 0 0 0 0 0 mw mw This device contains protection circuitry to guard against damage due to high static voltages or electric fields; however, it is advised that precautions be taken to avoid application of voltage higher than maximum rated voltages to this high impedance circuit. or proper operation it is recommended that Vin and Vout be constrained to the range (Vin or Vout). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Storage Temperature Range Tstg 6 to + 0 * aximum Ratings are those values beyond which damage to the device may occur. ELETRIAL HARATERISTIS (Voltages referenced to, TA = 0 to unless otherwise indicated) Symbol Parameter Test onditions in ax Unit VIH High Level Input Voltage (,, L) VIL Low Level Input Voltage (,, L) IOH High Level Output urrent () Vout = 0. V 00 µa IOL Low Level Output urrent () Vout = 0. V 00 µa IDD Quiescent Supply urrent L L Iout = 0 µa Iin Input Leakage urrent (,, L) Vin = or 0 V ± µa Vnonl Nonlinearity Voltage (Rn Out) See igure Vstep Step Size (Rn Out) See igure Voffset Offset Voltage from = $00, See igure LS IE Emitter Leakage urrent VRn Out = 0 V µa he D urrent Gain IE = 0. to.0 ma TA = 3.0 3. 9 39 0. 0. 0. 0 00 300 37 7 V V ma mv mv 0 VE ase to Emitter Voltage Drop IE =.0 ma 0. 0.7 V Page 3 of
L, L SWITHING HARATERISTIS (Voltages referenced to, TA = 0 to, L = 0 p, Input tr = tf = 0 ns unless otherwise indicated) Symbol Parameter in ax Unit twh Positive Pule Width, L (igures 3 and ) twl Negative Pulse Width, L (igure 3 and ) tsu Setup Time, to L (igures 3 and ) tsu Setup Time, to L (igures 3 and ) th Hold Time, L to (igures 3 and ) th Hold Time, L to (igures 3 and ) tr, tf Input Rise and all Times in Input apacitance 7. p. 3. 3. 00 70 00 3. 3. ns O UTPUT VOLTAGE @ Rn Out, % (V D D V S S ) 0 7 0 0 0 $00 Voffset IDEAL $0 3 $ Vnonl PROGRA STEP 7 $ LINEARITY ERROR (integral linearity). A measure of how straight a device s transfer function is, it indicates the worst case deviation of linearity of the actual transfer function from the best fit straight line. It is normally specified in parts of an LS. igure. D/A Transfer unction ATUAL 63 $3 Page of
L, L VRn OUT STEP SIZE Step Size = ± 0.7 6 6 (or any adjacent pair of digital numbers) DIGITAL NUER igure. Definition of Step Size 0% tsu th L 0% N twh twl D D DN tsu th igure 3. Serial Input, Positive lock tsu th L N twl twh D D DN tsu th igure. Serial Input, Negative lock Page of
L, L INPUTS Data Input PIN DESRIPTIONS Six bit words are entered serially, S first, into digital data input,. Six words are loaded into the L during each D/A cycle; four words are loaded into the L. The last 6 bit word shifted in determines the output level of pins Q Out and R Out. The next to last 6 bit word affects pins Q Out and R Out, etc. Negative Logic Enable The pin must be low (active) during the serial load. On the low to high transition of, data contained in the shift register is loaded into the latch. L Shift Register lock Data is shifted into the register on the high to low transition of L. L is fed into the D input of a transparent latch, which is used for inhibiting the clocking of the shift register when is high. The number of clock cycles required for the L is usually 36. The L usually uses cycles. SeeTable for additional information. OUTPUTS Data Output The digital data output is primarily used for cascading the DAs and may be fed into of the next stage. R Out through Rn Out Resistor Network Outputs These are the R R resistor network outputs. These outputs may be fed to high impedance input ET op amps to bypass the on chip bipolar transistors. The R value of the resistor network ranges from 7 to kω. Q Out through Qn Out NPN Transistor Outputs uffered DA outputs utilize an emitter follower configuration for current gain, thereby allowing interface to low impedance circuits. SUPPLY PINS Negative Supply Voltage This pin is usually ground. Positive Supply Voltage The voltage applied to this pin is used to scale the analog output swing from. to V p p. Table. Number of hannels vs locks Required Number of hannels Required Number of lock ycles Outputs Used on L Outputs Used on L 6 Q/R Q/R Q/R, Q/R Q/R, Q/R 3 Q/R, Q/R, Q3/R3 Q/R, Q/R, Q3/R3 Q/R, Q/R, Q3/R3, Q/R Q/R, Q/R, Q3/R3, Q/R 30 Q/R, Q/R, Q3/R3, Q/R, Q/R Not Applicable 6 36 Q/R, Q/R, Q3/R3, Q/R, Q/R, Q6/R6 Not Applicable Page 6 of
L, L OUTLINE DIENSIONS P DIP = VP (LVP) PLASTI DIP ASE 707 0 9 NOTES:. POSITIONAL TOLERANE O LEADS (D), SHALL E WITHIN 0. (0.0) AT AXIU ATERIAL ONDITION, IN RELATION TO SEATING PLANE AND EAH OTHER.. DIENSION L TO ENTER O LEADS WHEN ORED PARALLEL. 3. DIENSION DOES NOT INLUDE OLD LASH. H G A D N SEATING PLANE L DI A D G H L N ILLIETERS IN AX. 3. 6. 6.60 3.6.7 0.36 0.6.7.7. S.0 0.0.9 7.6 S 0 0.. 0.30 3.3.0 INHES IN AX 0.7 0.9 0.0 0.60 0.0 0.0 0.0 0.0 0.00 0.070 0.0 S 0.00 0.00 0. 0.060 0.0 0.3 0.300 S 0 0.00 0.00 0 A X P 0.0 (0.) SO 0W = -6P (L-6P) SOG PAAGE ASE 7D 0 NOTES:. DIENSIONING AND TOLERANING PER ANSI Y., 9.. ONTROLLING DIENSION: ILLIETER. 3. DIENSIONS A AND DO NOT INLUDE OLD PROTRUSION.. AXIU OLD PROTRUSION 0.0 (0.006) PER SIDE.. DIENSION D DOES NOT INLUDE DAAR PROTRUSION. ALLOWALE DAAR PROTRUSION SHALL E 0.3 (0.00) TOTAL IN EXESS O D DIENSION AT AXIU ATERIAL ONDITION. 0X D 0.0 (0.) T A S S X G T SEATING PLANE R X ILLIETERS INHES DI IN AX IN AX A.6.9 0.99 0. 7.0 7.60 0.9 0.99.3.6 0.093 0. D 0.3 0.9 0.0 0.09 0.0 0.90 0.00 0.03 G.7 S 0.00 S 0. 0.3 0.0 0.0 0. 0. 0.00 0.009 0 7 0 7 P.0. 0.39 0. R 0. 0.7 0.0 0.09 Page 7 of
L, L 7 A H G D N SEATING PLANE OUTLINE DIENSIONS P DIP = P (LP) PLASTI DIP ASE 66 06 L NOTES:. LEADS WITHIN 0.3 (0.00) RADIUS O TRUE POSITION AT SEATING PLANE AT AXIU ATERIAL ONDITION.. DIENSION L TO ENTER O LEADS WHEN ORED PARALLEL. 3. DIENSION DOES NOT INLUDE OLD LASH.. ROUNDED ORNERS OPTIONAL. INHES ILLIETERS DI IN AX IN AX A 0.7 0.770.6 9.6 0.0 0.60 6. 6.60 0. 0. 3.69.69 D 0.0 0.0 0.3 0.3 0.00 0.070.0.7 G 0.0 S. S H 0.0 0.09.3. 0.00 0.0 0.0 0.3 0. 0.3.9 3.3 L 0.300 S 7.6 S 0 0 N 0.0 0.039 0.39.0 A 6 9 6X D X G 0.0 (0.) T A S S X P T SEATING PLANE 0.0 (0.) SO 6W = -P (L-P) SOG PAAGE ASE 7G 0 R X NOTES:. DIENSIONING AND TOLERANING PER ANSI Y., 9.. ONTROLLING DIENSION: ILLIETER. 3. DIENSIONS A AND DO NOT INLUDE OLD PROTRUSION.. AXIU OLD PROTRUSION 0. (0.006) PER SIDE.. DIENSION D DOES NOT INLUDE DAAR PROTRUSION. ALLOWALE DAAR PROTRUSION SHALL E 0.3 (0.00) TOTAL IN EXESS O D DIENSION AT AXIU ATERIAL ONDITION. ILLIETERS INHES DI IN AX IN AX A.. 0.00 0. 7.0 7.60 0.9 0.99.3.6 0.093 0. D 0.3 0.9 0.0 0.09 0.0 0.90 0.00 0.03 G.7 S 0.00 S 0. 0.3 0.0 0.0 0. 0. 0.00 0.009 0 7 0 7 P.0. 0.39 0. R 0. 0.7 0.0 0.09 Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Typical parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by the customer s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page of