MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

Similar documents
Unit 2 Session - 6 Combinational Logic Circuits

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

Boolean algebra. Examples of these individual laws of Boolean, rules and theorems for Boolean algebra are given in the following table.

CHAPTER III BOOLEAN ALGEBRA

CHAPTER III BOOLEAN ALGEBRA

E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev

UNIT 5 KARNAUGH MAPS Spring 2011

Chapter 2 Combinational Logic Circuits

Digital Logic Design. Combinational Logic

II. COMBINATIONAL LOGIC DESIGN. - algebra defined on a set of 2 elements, {0, 1}, with binary operators multiply (AND), add (OR), and invert (NOT):

Chapter-2 BOOLEAN ALGEBRA

Gate-Level Minimization

Standard & Canonical Forms

E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev. Section 2: Boolean Algebra & Logic Gates

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions

Chap 2. Combinational Logic Circuits

Binary logic consists of binary variables and logical operations. The variables are

MC9211 Computer Organization

ELC224C. Karnaugh Maps

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University

Chapter 2 : Boolean Algebra and Logic Gates

Midterm1 Review. Jan 24 Armita

This form sometimes used in logic circuit, example:

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata

Week-I. Combinational Logic & Circuits

COE 202: Digital Logic Design Combinational Logic Part 2. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

CS 121 Digital Logic Design. Chapter 2. Teacher Assistant. Hanin Abdulrahman

Karnaugh Maps Objectives

ELCT201: DIGITAL LOGIC DESIGN

EC-121 Digital Logic Design

L4: Karnaugh diagrams, two-, and multi-level minimization. Elena Dubrova KTH / ICT / ES

Theorem/Law/Axioms Over (.) Over (+)

ENG2410 Digital Design Combinational Logic Circuits

Chapter 2: Boolean Algebra and Logic Gates

Chapter 2. Boolean Algebra and Logic Gates

Lecture 2 Review on Digital Logic (Part 1)

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC.

Digital Circuit And Logic Design I. Lecture 4

Chapter 2 (Lect 2) Canonical and Standard Forms. Standard Form. Other Logic Operators Logic Gates. Sum of Minterms Product of Maxterms

CHAPTER1: Digital Logic Circuits Combination Circuits

UNIVERSITI TENAGA NASIONAL. College of Information Technology

Chapter 2 Boolean Algebra and Logic Gates

Chapter 2. Digital Logic Basics

Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms

Combinational Logic Fundamentals

Unit 2 Boolean Algebra

Boolean Algebra and Logic Gates

Chapter 2 Boolean Algebra and Logic Gates

DIGITAL ELECTRONICS & it0203 Semester 3

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive

Chapter 2: Switching Algebra and Logic Circuits

Combinational Logic. Review of Combinational Logic 1

Minimization techniques

Boolean Algebra & Logic Gates. By : Ali Mustafa

Logic Design. Chapter 2: Introduction to Logic Circuits

211: Computer Architecture Summer 2016

Digital Logic. Lecture 5 - Chapter 2. Outline. Other Logic Gates and their uses. Other Logic Operations. CS 2420 Husain Gholoom - lecturer Page 1

Computer Organization I. Lecture 13: Design of Combinational Logic Circuits

Combinational Logic Design/Circuits

CPE100: Digital Logic Design I

Standard Expression Forms

Digital Logic Design ABC. Representing Logic Operations. Dr. Kenneth Wong. Determining output level from a diagram. Laws of Boolean Algebra

L2: Combinational Logic Design (Construction and Boolean Algebra)

Optimizations and Tradeoffs. Combinational Logic Optimization

EEE130 Digital Electronics I Lecture #4

Chapter 4 Optimized Implementation of Logic Functions

KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE

DIGITAL CIRCUIT LOGIC BOOLEAN ALGEBRA

Boolean Algebra and Logic Design (Class 2.2 1/24/2013) CSE 2441 Introduction to Digital Logic Spring 2013 Instructor Bill Carroll, Professor of CSE

Boolean Algebra, Gates and Circuits

Number System conversions

BOOLEAN ALGEBRA TRUTH TABLE

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

Logic Gate Level. Part 2

CHAPTER 5 KARNAUGH MAPS

UNIT 4 MINTERM AND MAXTERM EXPANSIONS

Logic Design Combinational Circuits. Digital Computer Design

Chapter 2 Combinational logic

Chapter 3. Boolean Algebra. (continued)

CHAPTER 2 BOOLEAN ALGEBRA

Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011

EEA051 - Digital Logic 數位邏輯 吳俊興高雄大學資訊工程學系. September 2004

Review for Test 1 : Ch1 5

Chapter 2 Combinational Logic Circuits

Unit 6. Quine-McClusky Method. Unit 6 1

ECE 238L Boolean Algebra - Part I

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents

Chapter 2 Combinational Logic Circuits

CSE 140 Midterm I - Solution

DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN

Boolean Algebra and logic gates

ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES

SAMPLE ANSWERS MARKER COPY

Chapter 2 Boolean Algebra and Logic Gates

BOOLEAN ALGEBRA. Introduction. 1854: Logical algebra was published by George Boole known today as Boolean Algebra

In Module 3, we have learned about Exclusive OR (XOR) gate. Boolean Expression AB + A B = Y also A B = Y. Logic Gate. Truth table

MODULAR CIRCUITS CHAPTER 7

Cs302 Quiz for MID TERM Exam Solved

Chapter 7 Logic Circuits

Transcription:

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 DEPARTMENT: ECE QUESTION BANK SUBJECT NAME: DIGITAL ELECTRONICS UNIT I: Boolean Functions and Logic Gates PART -A ( Marks). What are the limitations of Karnaugh map? (AUC MAY ) SEMESTER III SUBJECT CODE: EC. For more than 4 input variables, K-map is complex to solve.. Redundant terms cannot be avoided in K-Map.. What are don t care condition? (AUC MAY ) In some logic circuits certain conditions never occurs,therefore the corresponding output never appears. These output levels are indicated by or d in the truth tables and are called don t care conditions or incompletely specified functions.. State Demorgan s theorem. (AUC MAY,APR ) Theorem : The compliment of a product is equal to the sum of the compliments. AB = A +B Theorem : The compliment of a sum is equal to the product of the compliments. A+B = A.B 4. Map the standard SOP expression on a karnaugh map. (AUC NOV ) ABC + A B C +ABC +A B C A A B C B C BC BC PREPARED BY L.M.I.LEO JOSEPH A.P/ECE

5. Draw the logic diagram of OR gate using universal gates. (AUC NOV ) A A+B 6. Draw an active-high tri-state buffer and write its truth table. (AUC APR ) PUT CHIP SELECT INPUT UTPUT Z PREPARED BY L.M.I.LEO JOSEPH A.P/ECE

7. Prove that the logical sum of all minterms of a Boolean function of variables is. (AUC NOV 9) Minterms formed by variables = n combinations ( =4) Let the input variables are x and y and the 4 possible combinations are x y,x y, xy, xy. Sum of all minterms are x y +x y+ xy + xy = x(y+y )+x (y+y ) =x+x = 8. Show that a positive logic NAND gate is a negative logic NOR gate. (AUC NOV 9) = 9. Simplify the given function : F=A BC + AB C +ABC +ABC. (AUC NOV 8) F=BC(A+A )+AC (B+B ) F=BC+AC. Using Boolean algebra prove x+x y + xy =x + y (AUC NOV 7) x(+y )+x y = x+x y = x+y. Minimize the function using Boolean algebra f=x(y+w z)+wxz (AUC JUNE 7) f=xy+w xz+wxz = xy +xz(w+w ) = xy+xz =x(y+z). What is tristate logic? What are its demerits? (AUC MAY ) In the tristate logic, in addition to low impedance outputs and there is a third state known as high impedance state. When the gate is disabled it is in the third state. When the output changes from low to high,a large current is drawn from the supply during the transition. This generates noise spike in the supply system. PREPARED BY L.M.I.LEO JOSEPH A.P/ECE

. State the features of bipolar logic families. (AUC MAY ) Speed of operation Power dissipation Fan-in Fan-out Noise margin Operating temperature 4. Draw a input CMOS NOR gate. (AUC NOV 7) 5. Define fanout of a digital IC. (AUC NOV 7) It is the maximum number of similar logic gates that a gate can drive without any degradation in its voltage level is called Fan-out. 6. What is the advantage of using schottky TTL gate. (AUC JUNE 7) Low power dissipation Higher speed of operation Driving capability. PREPARED BY L.M.I.LEO JOSEPH A.P/ECE 4

PART B (6 Marks). Reduce the following functions using Karnaugh map technique i)f(a,b,c)= m(,,,7)+ d(,5) (AUC MAY ) ii)f(w,x,y,z)= m(,7,8,9,,)+ d(,5,) i) K MAP FOR F A/BC F=A'C ii) K MAP FOR F AB/CD F=AB'+B'D'+AB'D PREPARED BY L.M.I.LEO JOSEPH A.P/ECE 5

. Simplify the given Boolean function into i)sum of products form ii) product of sum form f(a,b,c,d)= m(,,,5,8,9,)(auc MAY ) K MAP FOR F AB/CD F=B'C'+B'D'+A'C'D B'C'=B'C'(A+A') (D+D') =AB'C'D+A'B'C'D+AB'C'D'+A'B'C'D' B'D'=B'D'(A+A')(C+C') =AB'CD+A'B'CD+AB'C'D+A'B'C'D AC'D(B+B')=A'BC'D+A'BC'D SOP : A'B'C'D'+A'B'C'D+A'B'CD+A'BC'D+AB'C'D'+AB'C'D+AB'CD POS :(A+B+C'+D)(A+B'+C+D)(A+B'+C'+D) (A+B'+C'+D')(A'+B+C'+D)(A'+B'+C+D) (A'+B'+C'+D)(A'+B'+C'+D') PREPARED BY L.M.I.LEO JOSEPH A.P/ECE 6

. Simplify the Boolean function using Quine Mc Clusky method f(a,b,c,d)= m(,5,7,8,9,,,4,5)(aucmay,, 7 ) LIST OF MINTERMS 8 5 9 7 4 5 4 5 7 8 9 4 5 4,8* - 5,7-8,9* - 8, - 9, -,5* - 4,5* - 8,,9, -- 5,7,9, -- PRIME IMPLICANTS 5 7 8 9 4 5 8,,9,* 5,7,9,*,5 4,5*,8* 8,9 * * * * PREPARED BY L.M.I.LEO JOSEPH A.P/ECE 7

PRIME IMPLICANTS are 8,,9,*, 5,7,9,*, 4,5*,,8* F= ab +ad+abc+b c d 4. Elaborate the basic laws of Boolean alzebra with sample. (AUC MAY ) Write the steps for multiplying a logic expression using a karnaugh map. Description of the Laws and Theorems Annulment Law - A term AND ed with a "" equals or OR ed with a "" will equal. A. =, A variable AND'ed with is always equal to. A + =, A variable OR'ed with is always equal to. Identity Law - A term OR ed with a "" or AND ed with a "" will always equal that term. A + = A, A variable OR'ed with is always equal to the variable. A. = A, A variable AND'ed with is always equal to the variable Indempotent Law - An input AND ed with itself or OR ed with itself is equal to that input. A + A = A, A. A = A, A variable OR'ed with itself is always equal to the variable. A variable AND'ed with itself is always equal to the variable. Complement Law - A term AND ed with its complement equals "" and a term OR ed with its complement equals "". A. A =, A variable AND'ed with its complement is always equal to. A + A =, A variable OR'ed with its complement is always equal to. Commutative Law - The order of application of two separate terms is not important. A. B = B. A, A + B = B + A, The order in which two variables are AND'ed makes no difference. The order in which two variables are OR'ed makes no difference. Double Negation Law - A term that is inverted twice is equal to the original term. A = A, A double complement of a variable is always equal to the variable. PREPARED BY L.M.I.LEO JOSEPH A.P/ECE 8

de Morgan s Theorem - There are two "de Morgan s" rules or theorems, Two separate terms NOR ed together is the same as the two terms inverted (Complement) and AND ed for example, A+B = A. B. Two separate terms NAND ed together is the same as the two terms inverted (Complement) and OR ed for example, A.B = A +B. Distributive Law - This law permits the multiplying or factoring out of an expression. Absorptive Law - This law enables a reduction in a complicated expression to a simpler one by absorbing like terms. Associative Law - This law allows the removal of brackets from an expression and regrouping of the variables. Procedure to solve k map Consider the karnaugh map 4 x 5 x 7 6 Consider no of one s adjacent to each other We can form combinations as octet,quad, pair and unique Combining 8 no of s is octet Combining 4 no of s is quad Combining no of s is pair Uncombined form is termed as unique term are don t care condition will be treated as when it is adjacent to atleast one minterm () Combining two groups with atleast one minterm seems to be free is called overlapping. Combining the minterms in the corner is called rolling. 5. Simplify the logic function using Quine McCluskey method and realize using NAND gates. (AUC NOV,7) f(a,b,c,d)= m(,,5,9,,)+ d(6,8) PREPARED BY L.M.I.LEO JOSEPH A.P/ECE 9

5 D6 D8 9 D8 5 D6 9, -,5* -,9* -,* - 9, -,* -,,9, -- PRIME IMPLICANTS 5 9,,9,*,5*,9,*,* * * * PRIME IMPLICANTS are,,9,*,,5*,,*,,* F=b d+ a c d+ b cd+ ab c 6. Express the Boolean function as POS form ()SOP form D = (A + B) (B + C) (4) D=(A'+B)(B'+C) A'+B = A'+B+CC =(A'+B+C)(A'+B+C') B'+C=B+C+AA' =(B'+C+A)(B'+C+A') D=(A'+B+C)(A'+B+C')(B'+C+A)(B'+C+A') PREPARED BY L.M.I.LEO JOSEPH A.P/ECE

Minimize the given terms πm (,, 4,,, 5) + π d (5, 7, 8) using Quine-McClusky methods and verify the results using K-map methods. () (AUC APR,7) 4 D5 D7 D8 5 4 4 D8 D5 D7 D D 5 4, -,4 -,8* -,5-4,5-5,7-5, - 7,5 -,5* -,5 - PRIME IMPLICANTS : (,8),(,5),,4,5 * -- 5,7,,5 * --,4,,5 -- 5,,7,5 -- PRIME IMPLICANTS : (,,4,5) (5,7,,5) PREPARED BY L.M.I.LEO JOSEPH A.P/ECE

PRIME IMPLICANTS 4 5 7 8 5 (,8)* (,5)* (,,4,5)* (5,7,,5)* * * * * * * PRIME IMPLICANTS are (,8)* (,5)* (,,4,5)* (5,7,,5)* F=-+-+--+--=B C D +ACD+A C +BD =(B+C+D)(A +C +D )(A+C)(B +D ) K-MAP VERIFICATION K MAP FOR F AB/CD F=(B+C+D)(A +C +D )(A+C)(B +D ) 7. i)implement the following function using NOR gates. (8) (AUC APR ) Output = when the inputs are Σ m(,,,,4) = when the inputs are Σ m(5,6,7). A B C Y PREPARED BY L.M.I.LEO JOSEPH A.P/ECE

K MAP FOR Y A/BC Y=A'+B'C' DIAGRAM USING BASIC GATES A U B C U U U4 AND U5 Y OR DIAGRAM USING NORGATES PREPARED BY L.M.I.LEO JOSEPH A.P/ECE

A U6 NOR U B U C U U U4 AND U7 NOR Y A U6 NOR U B U C U U U4 AND U7 NOR Y A U6 NOR U Y B C U7 NOR U7 NOR PREPARED BY L.M.I.LEO JOSEPH A.P/ECE 4

A U6 NOR U6 Y NOR B C U7 NOR U7 NOR 8. Express the Boolean function F = Y + Z in product of Maxterm.(6) Y+Z Y(Z+Z')=YZ+YZ' Z(Y+Y')=YZ+Y'Z F=('+Y+Z')('+Y'+Z)('+Y+Z') Reduce the following function using K-map technique (AUC NOV 9) f (A, B, C, D) = π (,, 4, 7, 8,,, 4) + d (, 6). () ) (AUC NOV 9) K MAP FOR F AB/CD F=D(A+C') PREPARED BY L.M.I.LEO JOSEPH A.P/ECE 5

9. Simplify the following Boolean function by using Quine Mcclusky method F(A,B,C,D)= Σ(,,, 6, 7, 8,,, )(6) (AUC NOV 9) 6 7 8 8 6 7, -,8 -, -,6 -, - 8, - 8,* -,7-6,7 -,* - PRIME IMPLICANTS :(8,),(,),,6,7* --,,8,* --,6,,7 --,8,, -- PRIME IMPLICANTS : (,,6,7*) (,,8,*) PRIME IMPLICANTS 6 7 8 (,,6,7)* (,,8,)* (8,) (,)* * * * * * * PREPARED BY L.M.I.LEO JOSEPH A.P/ECE 6

PRIME IMPLICANTS are (,,6,7)* (,,8,)* (,)* F=--+-+-- =A C+ABC +B D. Simplify the given function using K map F= m(,,4,5,9,,,,4,5) (AUC NOV 8,7) List all the prime implicants and draw the logic diagram for the minimized expression using gates (4) (AUC NOV 8) K MAP FOR F AB/CD F=AB+C'D+BC' A B U9 AND C U7 D U AND U OR 4 F U AND PREPARED BY L.M.I.LEO JOSEPH A.P/ECE 7