Lecture 6: Circuit design part 6. Combinational circuit design 6. Sequential circuit design 6.3 Circuit simulation 6.4. Hardware description language Combinational Circuit Design. Combinational circuit design Circuit designer must learn to think in terms of NND and NOR to take advantage of static CMOS CMOS stages are inherently inverting, DeMorgan s law helps with this conversion:
. Combinational circuit design ubble Pushing Start with network of ND / OR gates Convert to NND / NOR + inverters Push bubbles around to simplify logic Remember DeMorgan s Law 3 Example Example: Design a circuit to compute F + CD using NNDs and NORs. 4
Compound Gates Compound Gates OI: ND-OR-INVERT- OI: ND-OR-INVERT- 5 Logical Effort of compound gates 6 3
Example Example: Calculate the minimum delay, in τ, to compute F + CD using the following circuits: Using NND gate Using compound gate Each input can present a maximum of 0 λ of transistor width. The output must drive a load equivalent to 00 λ of transistor width. 7 Example Solution: The path electrical effort is H 00/0 5 The branching effort is Using NND gate No. of stages N Logical effort G (4/3) (4/3) 6/9 Parasitic delay P + 4 Path efforts F GH 80/9 Path delays D NF /N + P 9.96 Using compound gate N G (6/3) P /3 + 5 F GH 5 0 D NF /N + P.3 > Using compound gates does not always result in faster circuits; simple -input NND gates can be quite fast. 8 4
Input Order Our parasitic delay model was too simple Calculate parasitic delay for falling If arrives latest? τ If arrives latest?.33τ x 6C C D R(6C) 6RC τ D (R/)(C) + R(6C) 7RC.33 τ 9 Inner & Outer Inputs Inner input is closest to output () Outer input is closest to rail () If input arrival time is known Connect latest input to inner terminal 0 5
symmetric Gates symmetric gates favor one input over another Ex: suppose input of a NND gate is most critical Use smaller transistor on (less capacitance) oost size of noncritical input So total resistance is same g 0/9 g g total g + g 8/9 reset reset symmetric gate approaches g on critical input ut total logical effort goes up 4/3 4 Symmetric Gates Inputs can be made perfectly symmetric 6
Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical nmos transistor HI-skew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance) / / Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. g u.5 / 3 5/6 g d.5 /.5 5/3 3 HI- and LO-Skew Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nmos) LO-skew gates favor falling output (small pmos) Logical effort is smaller for favored direction ut larger for the other direction 4 7
Catalog of Skewed Gates Inverter NND NOR unskewed gu u gd d gavg avg gu u 4/3 gd d 4/3 gavg avg 4/3 4 4 gu u 5/3 gd d 5/3 gavg avg 5/3 HI-skew / gu u 5/6 gd d 5/3 gavg avg 5/4 g u gd d gavg avg 3/ gu / 4 4 / gu u 3/ gd d 3 gavg avg 9/4 LO-skew gu u 4/3 gd d /3 gavg avg g u gd d gavg avg 3/ gu gu u gd d gavg avg 3/ 5 symmetric Skew Combine asymmetric and skewed gates Downsize noncritical transistor on unimportant input Reduces parasitic delay for critical input reset reset 4/3 4 6 8
est P/N Ratio We have selected P/N ratio for unit rise and fall resistance (µ -3 for an inverter). lternative: choose ratio for least average delay Ex: inverter Delay driving identical inverter P t pdf (P+) t pdr (P+)(µ/P) t pd (P+)(+µ/P)/ (P + + µ + µ/p)/ dt pd / dp (- µ/p )/ 0 Least delay for P µ 7 P/N Ratios In general, best P/N ratio is sqrt of equal delay ratio. Only improves average delay slightly for inverters ut significantly decreases area and power 8 9
Observations For speed: NND vs. NOR Many simple stages vs. fewer high fan-in stages Latest-arriving input For area and power: Many simple stages vs. fewer high fan-in stages 9 Review 0 0
Pseudo-nMOS What makes a circuit fast? I C dv/dt -> t pd (C/I) V low capacitance high current small swing Logical effort is proportional to C/I 4 4 pmos are the enemy! High capacitance for a given current Can we take the pmos capacitance off the input? Various circuit families try to do this Pseudo-nMOS In the old days, nmos processes had no pmos Instead, use pull-up transistor that is always ON In CMOS, use a pmos that is always ON Ratio issue Make pmos about ¼ effective strength of.8 pulldown network load I ds P/.5. V out 0.9 P 4 V out V in 6/ 0.6 0.3 P 4 P 4 0 0 0.3 0.6 0.9..5.8 V in
Pseudo-nMOS Gates Design for unit current on output to compare with unit inverter. pmos fights nmos inputs f Inverter NND NOR g u g d g avg p u p d p avg g u g d g avg p u p d p avg g u g d g avg p u p d p avg 3 Pseudo-nMOS Gates Design for unit current on output to compare with unit inverter. pmos fights nmos inputs f Inverter NND NOR /3 4/3 g u 4/3 g d 4/9 g avg 8/9 p u 6/3 p d 6/9 p avg /9 /3 8/3 8/3 g u 8/3 g d 8/9 g avg 6/9 p u 0/3 p d 0/9 p avg 0/9 /3 4/3 4/3 g u 4/3 g d 4/9 g avg 8/9 p u 0/3 p d 0/9 p avg 0/9 4
Pseudo-nMOS Design Ex: Design a k-input ND gate using pseudo-nmos. Estimate the delay driving a fanout of H G * 8/9 8/9 F GH 8H/9 P + (4+8k)/9 (8k+3)/9 N D NF /N 4 H 8k + 3 + P + 3 9 In In k Pseudo-nMOS H 5 Pseudo-nMOS Power Pseudo-nMOS draws power whenever 0 Called static power P I DD V DD few m / gate * M gates would be a problem Explains why nmos went extinct Use pseudo-nmos sparingly for wide NORs Turn off pmos when not in use en C 6 3
Ratio Example The chip contains a 3 word x 48 bit ROM Uses pseudo-nmos decoder and bitline pullups On average, one wordline and 4 bitlines are high Find static power drawn by the ROM I on-p 36 µ, V DD.0 V Solution: P V I 36 µw pull-up P static DD pull-up (3+ 4) P.98 mw pull-up 7 Dynamic Logic Dynamic gates uses a clocked pmos pullup Two modes: precharge and evaluate /3 4/3 Static Pseudo-nMOS Dynamic Precharge Evaluate Precharge 8 4
The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight. precharge transistor inputs f inputs f foot footed unfooted 9 Logical Effort Inverter NND NOR unfooted g d /3 p d /3 g d /3 p d 3/3 g d /3 p d 3/3 footed 3 3 g d /3 g d 3/3 p d 3/3 3 p d 4/3 g d /3 p d 5/3 30 5
Monotonicity Dynamic gates require monotonically rising inputs during evaluation 0 -> 0 0 -> -> ut not -> 0 violates monotonicity during evaluation Precharge Evaluate Precharge Output should rise but does not 3 Monotonicity Woes ut dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! X Precharge Evaluate X Precharge X monotonically falls during evaluation should rise but cannot 3 6
Domino Gates Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs domino ND Precharge Evaluate W Precharge W X Z C X Z dynamic NND static inverter W X H C H X Z C Z 33 Domino Optimizations Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic S0 S S S3 D0 D D D3 H S4 D4 S5 D5 S6 D6 S7 D7 34 7
Dual-Rail Domino Domino only performs noninverting functions: ND, OR but not NND, NOR, or XOR Dual-rail domino solves this problem Takes true and complementary inputs Produces true and complementary outputs sig_h sig_l Meaning 0 0 Precharged _l _h 0 0 inputs f f 0 invalid 35 Example: ND/NND Given _h, _l, _h, _l Compute _h, _l Pulldown networks are conduction complements _l * _h _h * _l _l _h 36 8
Example: XOR/XNOR Sometimes possible to share transistors _l xnor _h _l _l _h _h xor _l _h 37 Leakage Dynamic node floats high during evaluation Transistors are leaky (I OFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds Use keeper to hold dynamic node Must be weak enough not to fight evaluation k X weak keeper H 38 9
Charge Sharing Dynamic gates suffer from charge sharing 0 x C x C Charge sharing noise x C V V V x DD Cx + C 39 Secondary Precharge Solution: add secondary precharge transistors Typically need to precharge every other node ig load capacitance C helps as well x secondary precharge transistor 40 0
Noise Sensitivity Dynamic gates are very sensitive to noise Inputs: V IH V tn Outputs: floating output susceptible noise Noise sources Capacitive crosstalk Charge sharing Power supply noise Feedthrough noise nd more! 4 Power Domino gates have high activity factors Output evaluates and precharges If output probability 0.5, α 0.5 Output rises and falls on half the cycles Clocked transistors have α Leads to very high power consumption 4
Domino Summary Domino logic is attractive for high-speed circuits.3 x faster than static CMOS ut many challenges: Monotonicity, leakage, charge sharing, noise Widely used in high-performance microprocessors in 990s when speed was king Largely displaced by static CMOS now that power is the limiter Still used in memories for area efficiency 43 Pass Transistor Circuits Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates CMOS + Transmission Gates: -input multiplexer Gates should be restoring S S S S S S 44
LEP LEn integration with Pass transistors Get rid of pmos transistors Use weak pmos feedback to pull fully high Ratio constraint S S L 45 CPL Complementary Pass-transistor Logic Dual-rail form of pass transistor logic voids need for ratioed feedback Optional cross-coupling for rail-to-rail swing S S S S L L 46 3
Pass Transistor Summary Researchers investigated pass transistor logic for general purpose applications in the 990 s enefits over static CMOS were small or negative No longer generally used However, pass transistors still have a niche in special circuits such as memories where they offer small size and the threshold drops can be managed 47 Review. What are pseudo-nmos gates?. What are drawbacks of pseudo-nmos gates? 3. What are dynamic gates? 4. What is the foot of dynamic gates? 5. Why do we need secondary precharge for dynamic gates? 6. Why are dynamic gates very sensitive to noise? 7. What are domino gates? 8. What is CPL? 48 4
Review. Compute logical effort for rising and falling g u and g d of the following gates a) b) c) d) e) 49 5