Lecture 8: Combinational Circuit Design

Lecture 8: Combinational Circuit Design Mark McDermott Electrical and Computer Engineering The University of Texas at ustin 9/5/8

Verilog to Gates module mux(input s, d0, d, output y); assign y = s? d : d0; endmodule Sketch a design using ND, OR, and NOT gates. D0 S D S 9/5/8 Page

Example ) Sketch the design using NND, NOR, and NOT gates. ssume ~S is available. D0 S D S 9/5/8 Page 3

Example 3 3) Sketch a design using one compound gate and one NOT gate. ssume ~S is available. D0 S D S 9/5/8 Page 4

Sizing Compound Gates Inverter equivalence unit inverter OI OI = =! + C = + CD C C D D E C Complex OI!! ( ) =! + C + DE! 4 4 4 4 6 C C 4 C 4 D 4 C D C D E 6 3 6 E 6 D C g = 3/3 g = 6/3 g = 6/3 g = 5/3 p = 3/3 g = 6/3 g = 6/3 g = 8/3 g C = 5/3 g C = 6/3 g C = 8/3 p = 7/3 g D = 6/3 g D = 8/3 p = /3 g E = 8/3 p = 6/3 9/5/8 Page 5

Input Order Matters Our parasitic delay model was too simple Calculate parasitic delay for falling If arrives latest? t If arrives latest?.33t x 6C C 9/5/8 Page 6

Inner & Outer Inputs Outer input is closest to rail () Inner input is closest to output () If input arrival time is known Connect latest input to inner terminal 9/5/8 Page 7

symmetric Gates symmetric gates favor one input over another Example: Suppose input of a NND gate is most critical Use smaller transistor on (less capacitance) oost size of noncritical input So total resistance is same reset reset 4/3 4 9/5/8 Page 8

Symmetric Gates Inputs can be made perfectly symmetric 9/5/8 Page 9

Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical NMOS transistor HI-skew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance) / / 9/5/8 Page 0

HI- and LO-Skew Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nmos) LO-skew gates favor falling output (small pmos) Logical effort is smaller for favored direction ut larger for the other direction 9/5/8 Page

Catalog of Skewed Gates Inverter NND NOR unskewed g u = g d = g avg = g u = 4/3 g d = 4/3 g avg = 4/3 4 4 g u = 5/3 g d = 5/3 g avg = 5/3 HI-skew / g u = 5/6 g d = 5/3 g avg = 5/4 g u = g d = g avg = 3/ / 4 4 / g u = 3/ g d = 3 g avg = 9/4 LO-skew g u = 4/3 g d = /3 g avg = g u = g d = g avg = 3/ g u = g d = g avg = 3/ 9/5/8 Page

symmetric Skew Combine asymmetric and skewed gates Downsize noncritical transistor on unimportant input Reduces parasitic delay for critical input reset reset 4/3 4 9/5/8 Page 3

est P/N Ratio We have selected P/N ratio for equivalent rise and fall resistance (µ = -3 for an inverter). lternative: choose ratio for least average delay Ex: inverter Delay driving identical inverter t pdf = (P+) t pdr = (P+)(µ/P) t pd = (P+)(+µ/P)/ = (P + + µ + µ/p)/ Differentiate t pd w.r.t. P Least delay for P = µ P 9/5/8 Page 4

P/N Ratios In general, best P/N ratio is square root of that giving equal delay Only improves average delay slightly for inverters ut significantly decreases area and power Inverter NND NOR fastest.44 P/N ratio g u =.5 g d = 0.8 g avg = 0.98 g u = 4/3 g d = 4/3 g avg = 4/3 g u = g d = g avg = 3/ 9/5/8 Page 5

Device Sizing Device sizing is one of the key techniques for circuit optimization For standard cell type of designs, gate sizing For example of inverters, INV-, INV-, INV-C,, INV-N,, each having a different driving capabilities. For microprocessor or custom designs, more fine-grained control, transistor sizing For each transistor 9/5/8 Page 6

Driver Sizing Given: chain of cascaded drivers driving a load Ignore the interconnect between drivers (i.e. assume driver and load CL is closer enough) Obtain: Optimize the driver sizes to minimize delay, or minimize total area while meeting target delay Delay and area/power tradeoff d d d k C L C g C g Cgk 9/5/8 Page 7

Driver Sizing using stage ratios d d d k C L C g C g C gk Constant stage ratio: where!"#$!"!"#$!". (i.e..78) = ( '( ') )$/, We will use 3-4 in this class 9/5/8 Page 8

Stage ratio example 0 60 Inverter equivalent stage ratio = 3 beta ratio = 40 0 Sized NND beta ratio = 40 0 40 60 9/5/8 Page 9

Sizing example Size these three circuits. Load on node : 40/0 inverter Use stage ratio of 4 Use beta ratio of 40 40 0 0 40 0

Stage ratio example HW #3 Use stage ratio of 3 Use beta ratio of F G 0 60 C 80 D 90 E 9/5/8 Page

ackup: Logical Effort 9/5/8

Introduction Chip designers face a plethora of choices What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be? Logical effort is one method to make these decisions Uses a simple model of delay llows back-of-the-envelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries 9/5/8 Page 4

Example Design the decoder for a register file. Decoder specifications: 6 word register file Each word is 3 bits wide Each bit presents load of 3 unit-sized transistors True and complementary address inputs [3:0] Each input may drive 0 unit-sized transistors Need to decide: How many stages to use? How large should each gate be? How fast can decoder operate? [3:0] [3:0] 4:6 Decoder 6 3 bits Register File 6 words 9/5/8 Page 5

Delay in a Logic Gate Express delays in process-independent unit d = d abs t Delay has two components: d = f + p Effort delay f = gh (a.k.a. stage effort) τ = 3RC» ps in 80 nm process 3 ps in 65nm µm process g: logical effort Measures relative ability of gate to deliver current g = for inverter h: electrical effort = Cout / Cin Ratio of output to input caps. Sometimes called fanout effort Parasitic delay p Represents intrinsic delay of gate driving no load Set by internal parasitic capacitance 9/5/8 Page 6

Delay Plots d = f + p d = gh + p Normalized Delay: d 6 5 4 3 -input NND Inverter g = 4/3 p = d = (4/3)h + g = p = d = h + Effort Delay: f 0 Parasitic Delay: p 0 3 4 5 Electrical Effort: h = C out / C in What about a NOR? 9/5/8 Page 7

Computing Logical Effort Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current Measure from delay vs. fanout plots Or estimate by counting transistor widths 4 4 C in = 3 g = 3/3 C in = 4 g = 4/3 C in = 5 g = 5/3 9/5/8 Page 8

Computing Logical Effort for a NND Gate Recall that delay = t pd /τ and τ 3RC For the -NND gate below x 6C C 4hC R (6+4h)C The rising propagation delay is: t pdr = 6+ 4h RC ( ) Therefore d = t pd /τ = (6 + 4h)RC/3RC = 4/3h + Recall d = gh + p therefore g=4/3 9/5/8 Page 9

Computing Logical Effort for a NND Gate (cont) The logical effort for the falling signal is the same, however the intrinsic delay is not. x 6C C 4hC R/ x R/ C (6+4h)C tpdf = C + ë + h Cû + = 7+ 4h RC ( )( R ) ( 6 4 ) ( R R é ù ) ( ) Where d = t pd /τ = (7 + 4h)RC/3RC = 4/3h +7/3 9/5/8 Page 30

Catalog of Gates Logical effort of common gates Gate type Number of inputs 3 4 n Inverter NND 4/3 5/3 6/3 (n+)/3 NOR 5/3 7/3 9/3 (n+)/3 Tristate / mux XOR, XNOR 4, 4 6,, 6 8, 6, 6, 8 9/5/8 Page 3

Catalog of Gates Parasitic (intrinsic) delay of common gates In multiples of p inv (») Gate type Number of inputs 3 4 n Inverter NND 3 4 n NOR 3 4 n Tristate / mux 4 6 8 n XOR, XNOR 4 6 8 9/5/8 Page 3

Example: Ring Oscillator Estimate the frequency of an N-stage ring oscillator 3 stage ring oscillator in Logical Effort: g = 0.6 µm process has Electrical Effort: h = frequency of ~ 00 MHz Parasitic Delay: p = Stage Delay: d = Frequency: f osc = /(*N*d) = /4N Recall that the signal has to propagate through the inverter chain twice to make a complete waveform Page 33 9/5/8

Example: FO4 Inverter Estimate the delay of a fanout-of-4 (FO4) inverter d Logical Effort: g = Electrical Effort: h = 4 Parasitic Delay: p = Stage Delay: d = 5 The FO4 delay is about 00 ps in 0.6 µm process 60 ps in a 80 nm process f/3 ns in an f µm process (f/3 ps in an f nm process) Page 34 9/5/8

Multistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort à Path Electrical Effort à G = Õ g i H = C C out-path in-path Path Effort à F= Õ fi = Õgh i i 0 g = h = x/0 x g = 5/3 h = y/x y g 3 = 4/3 h 3 = z/y z g 4 = h 4 = 0/z 0 Can we write F = GH in general? Page 35 9/5/8

Paths that ranch No! Consider paths that branch: G = H = 90 / 5 = 8 GH = 8 h = (5 +5) / 5 = 6 h = 90 / 5 = 6 F = g g h h = 36 = GH 5 5 5 90 90 Page 36 9/5/8

ranching Effort Introduce branching effort ccounts for branching between stages in path b = C on path C + C on path off path = Õb i hi Õ Note: = H We compute the path effort F = GH Page 37 9/5/8

Multistage Delays Path Effort Delay D F = å f i Path Parasitic Delay P= å p i Path Delay = å = + i F D d D P Page 38 9/5/8

Designing Fast Circuits = å i = F + D d D P Delay is smallest when each stage bears same effort ˆ N f = gh i i = F Thus minimum delay of N stage path is N D = NF + P This is a key result of logical effort Find fastest possible delay Doesn t require calculating gate sizes Page 39 9/5/8

Gate Sizes How wide should the gates be for least delay? fˆ = gh = g Þ C = in i Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives C C out i in gc fˆ out i Check work by verifying input cap spec is met 9/5/8 Page 40

Example: 3-stage path Select gate sizes x and y for least delay from to x x y 45 8 x y 45 9/5/8 Page 4

Example: 3-stage path x x y 45 8 x y 45 Logical Effort G = (4/3)*(5/3)*(5/3) = 00/7 Electrical Effort H = 45/8 ranching Effort = 3 * = 6 Path Effort F = GH = 5 est Stage Effort 3 f ˆ = F = 5 Parasitic Delay P = + 3 + = 7 Delay D = 3*5 + 7 = = 4.4 FO4 Page 4 9/5/8

Example: 3-stage path Work backward for sizes y = 45 * (5/3) / 5 = 5 x = (5*) * (5/3) / 5 = 0 45 P: 4 N: 4 P: 4 N: 6 P: N: 3 45 9/5/8 Page 43

est Number of Stages How many stages should a path use? Minimizing number of stages is not always fastest Example: drive 64-bit datapath with unit inverter Initial Driver D = NF /N + P = N(64) /N + N 8 4.8 6 8 3 Datapath Load 64 64 64 64 N: f: D: 64 65 8 8 3 4 5 Fastest 4.8 5.3 Page 44 9/5/8

Derivation Consider adding inverters to end of path How many give least delay? = n N + å i + - i= D NF p N n p ( ) inv Logic lock: n Stages Path Effort F N - n Extra Inverters Define best stage effort r = F N D N N N N = - F ln F + F + p = 0 inv p + r - ln r = 0 inv ( ) Page 45 9/5/8

est Stage Effort p + r - ln r = 0 ( ) has no closed-form solution inv Neglecting parasitics (p inv = 0), we find r =.78 (e) For p inv =, solve numerically for r = 3.59 Page 46 9/5/8

Sensitivity nalysis How sensitive is delay to using exactly the best number of stages? D(N) /D(N).6.4..0.5.5.6 (r=6) (r =.4) 0.0 0.5 0.7.0.4.0.4 < r < 6 gives delay within 5% of optimal We can be sloppy! For example, use r = 4 N / N Page 47 9/5/8

Let s revisit the decoder specifications Design the decoder for a register file. Decoder specifications: 6 word register file Each word is 3 bits wide Each bit presents load of 3 unit-sized transistors True and complementary address inputs [3:0] Each input may drive 0 unit-sized transistors Need to decide: How many stages to use? How large should each gate be? How fast can decoder operate? [3:0] [3:0] 4:6 Decoder 6 3 bits Register File 6 words 9/5/8 Page 48

Decoder Ex: Number of Stages Decoder effort is mainly electrical and branching Electrical Effort: H = (3*3) / 0 = 9.6 ranching Effort: = 8 If we neglect logical effort (assume G = ) Path Effort: F = GH = 76.8 Number of Stages: N = log 4 F = 3. Try a 3-stage design based on rough estimation Page 49 9/5/8

Decoder: Gate Sizes & Delay Logical Effort: G = * 6/3 * = (not an estimation) Path Effort: F = GH = 54 Stage Effort: Path Delay: /3 f ˆ = F = 5.36 D= 3 fˆ + + 4 + =. Gate sizes: z = 96*/5.36 = 8; y = 8*/5.36 = 6.7 [3] [3] [] [] [] [] [0] [0] 0 0 0 0 0 0 0 0 y z word[0] 96 units of wordline capacitance y z word[5] Page 50 9/5/8

Decoder: Comparison Compare many alternatives with a spreadsheet Design N G P D NND4-INV 5 9.8 NND-NOR 0/9 4 30. INV-NND4-INV 3 6. NND4-INV-INV-INV 4 7. NND-NOR-INV-INV 4 0/9 6 0.5 NND-INV-NND-INV 4 6/9 6 9.7 INV-NND-INV-NND-INV 5 6/9 7 0.4 NND-INV-NND-INV-INV-INV 6 6/9 8.6 9/5/8 Page 5

Review of Definitions Term Stage Path number of stages logical effort electrical effort branching effort effort effort delay parasitic delay delay g h = b = f f p = C C C out in on-path gh + C C on-path d = f + p off-path N G = Õ g i H = C C out-path in-path = Õb i F D = GH F = å P = å p i å f i i D = d = D + P F Page 5 9/5/8

Logical Effort Methodology Summary Compute path effort Estimate best number of stages Sketch path with N stages Estimate least delay Determine best stage effort F = GH N = log 4 N D = NF + P ˆ f = F N F Find gate sizes C in i = gc i fˆ out i 9/5/8 Page 53

Limits of Logical Effort Chicken and egg problem Need path to compute G ut don t know number of stages without G Simplistic delay model Neglects input rise time effects Interconnect Iteration required in designs with wire Maximum speed only Not minimum area/power for constrained delay 9/5/8 Page 54

Summary Logical effort is useful for thinking of delay in circuits Numeric logical effort characterizes gates NNDs are faster than NORs in CMOS Paths are fastest when effort delays are ~4 Path delay is weakly sensitive to stages, sizes ut using fewer stages doesn t mean faster paths Delay of path is about log 4 F FO4 inverter delays Inverters and NND best for driving large caps Provides language for discussing fast circuits ut requires practice to master 9/5/8 Page 55

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