Lecture 11: MOSFET Modeling

Similar documents
Lecture 4: Technology Scaling

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

ECE-305: Fall 2017 MOS Capacitors and Transistors

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Practice 3: Semiconductors

Lecture 4: CMOS Transistor Theory

EE5311- Digital IC Design

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

Device Models (PN Diode, MOSFET )

Integrated Circuits & Systems

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

The Devices: MOS Transistors

Nanoscale CMOS Design Issues

MOS Transistor I-V Characteristics and Parasitics

MOSFET: Introduction

ECE 305: Fall MOSFET Energy Bands

Device Models (PN Diode, MOSFET )

Lecture 5: CMOS Transistor Theory

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

EECS130 Integrated Circuit Devices

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

ECE 342 Electronic Circuits. 3. MOS Transistors

Scaling Issues in Planar FET: Dual Gate FET and FinFETs

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits

Lecture 12: MOSFET Devices

MOS Transistor Theory

VLSI Design The MOS Transistor

HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

Semiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Refinement. Last Time. No Field. Body Contact

Lecture 3: CMOS Transistor Theory

Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007

A Multi-Gate CMOS Compact Model BSIMMG

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

Lecture #27. The Short Channel Effect (SCE)

The Devices. Jan M. Rabaey

ECE-305: Spring 2016 MOSFET IV

Microelectronics Part 1: Main CMOS circuits design rules

Lecture 9: Interconnect

ECE315 / ECE515 Lecture-2 Date:

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

The Gradual Channel Approximation for the MOSFET:

ECE 546 Lecture 10 MOS Transistors

MOSFET. Id-Vd curve. I DS Transfer curve V G. Lec. 8. Vd=1V. Saturation region. V Th

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

Section 12: Intro to Devices

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

Lecture 04 Review of MOSFET

Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)

Technische Universität Graz. Institute of Solid State Physics. 11. MOSFETs

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

MOS Device Modeling. C.K. Ken Yang UCLA Courtesy of Agilent eesoft EE 215B

MOS Transistor Theory

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling?

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Nanometer Transistors and Their Models. Jan M. Rabaey

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor

Semiconductor Integrated Process Design (MS 635)

FIELD-EFFECT TRANSISTORS

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

CMOS Inverter (static view)

ECE 497 JS Lecture - 12 Device Technologies

Lecture 11: MOS Transistor

MOS Transistor. EE141-Fall 2007 Digital Integrated Circuits. Review: What is a Transistor? Announcements. Class Material

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

Compact Modeling of Semiconductor Devices: MOSFET

EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow

N Channel MOSFET level 3

EE 560 MOS TRANSISTOR THEORY

Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007

MOSFET Capacitance Model

Introduction and Background

The PSP compact MOSFET model An update

MOSFET Physics: The Long Channel Approximation

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

RFIC2017 MO2B-2. A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits

Lecture 12: MOS Capacitors, transistors. Context

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania

Advanced Compact Models for MOSFETs

VLSI Design and Simulation

The Devices. Devices

EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow

EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow

Transcription:

Digital Integrated Circuits (83-313) Lecture 11: MOSFET ing Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 18 June 2017 Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited; however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed, please feel free to email adam.teman@biu.ac.il and I will address this as soon as possible.

MOSFET Current ing In Digital Electronic Circuits, we used the Shockley for hand-analysis of circuit operation. However, there are many models with varying levels of accuracy to estimate the I-V curves of a MOSFET. In this section, we will overview several models that will come in use throughout this course and your future. 2

3 Lecture Content

4 Basic MOS s

Switch The Switch The most simple MOSFET model is the Switch. V GS > V T R on S D I DS I DS 1/R on 5 V T V GS V DS

The Piece-Wise Linear The Switch As we know, when the channel pinches off, the current saturates. I DS This can be depicted with the simple Piece-Wise Linear Switch I DSAT linear saturation The Piece-wise Linear 1/R on V GT V DS 6

Adding Channel Length Modulation Channel Length Modulation modeled as a finite output resistance, causes a saturation current dependence on V DS. The Switch The Piece-wise Linear I DSAT 1/λIDSAT I DS D V DS I DSAT I DS Channel Length Modulation λi DSAT S 1/R on -1/λ V GT V DS 7

8 Square Law (Shockley) To get a more accurate model, we already are familiar with the Shockley or Square Law. Current is just charge times velocity, so at any point, x, along the channel: I x x Q x Wdx We found that charge can be approximated as: D Q x C ox V GS VCS x VT And the velocity is the mobility times the electrical field: dv x E x n dx The Switch The Piece-wise Linear The Square Law

Square Law (Shockley) The Switch So we get: I dx C W V V V dv D n ox GS T At pinch-off (V DS =V GS -V T ), the voltage over the channel is constant, so we get: This is where the Square-Law name comes from. And integrating from source to drain, we get L V DS W 1 I I dx C W V V V dv C V V V V L 2 DS D n ox GS T n ox DS GS T DS 0 0 W I C V V 2L 2 DSAT n ox GS T The Piece-wise Linear The Square Law 9

Square Law (Shockley) Replacing V DS with V DSeff =min(v GS -V T, V DS ) we get: 2 W V I C V V V V L 2 DSeff 1 DS n ox GS T DSeff DS The Switch The Piece-wise Linear The Square Law 10

The Velocity Saturation However, when looking at a short channel device, we see a linear dependence on V GS. This can be attributed to Velocity Saturation. sat 5 10 m s The Switch The Piece-wise Linear The Square Law The V-Sat 11

The Velocity Saturation A good approximation of the mobility curve is: 1 crit sat crit crit The Switch The Piece-wise Linear The Square Law The V-Sat 12 For continuity: crit After integration, we get: 2 sat C W I V V V 1 L 2 n ox DS DS GS T DS V DS L 2 crit V

The Velocity Saturation The Switch 13 This is hard to use, but we can reach an important conclusion. We found that: And we know that for a velocity saturated device: Equating, we get: V DSAT C W I V V V 1 L 2 n ox DS DS GS T DS V DS L 2 V V L GS T crit V V L GS T crit crit V I DS WCox VGS VDSAT VT sat DSAT crit GT GS T V L V V V pinch off V L V L vel sat DSAT crit GT crit The Piece-wise Linear The Square Law The V-Sat

The Unified for Hand Analysis A few simple estimations will make the V-Sat model more user-friendly: The mobility is piecewise linear, saturating at ξ>ξ crit /2 V DSAT is piecewise linear, saturating at V DSAT =ξ crit L/2, when V GT >ξ crit L/2 The Switch The Piece-wise Linear The Square Law The V-Sat The Unified 14

The Unified for Hand Analysis This brings us to the Unified : 2 W V DSeff I C V V V 1 V L 2 DS n ox GS T DSeff DS V min V V, V, V DSeff GS T DS DSAT V DSAT crit 2 L crit 2 sat The Switch The Piece-wise Linear The Square Law The V-Sat The Unified 15

16 Advanced MOS s

17 VT* Sometimes we want to use a really simple model. We can assume that if the transistor is on, it s velocity saturated. 2 V DSAT IDS kn VGS VT VDSAT 2 I DS VDSAT k V V V 2 * VT n GS T DSAT k V V V V V * 0 VGS VT * * n GS T DSAT GS T The Switch The Piece-wise Linear The Square Law The V-Sat The Unified The VT*

The Alpha Power Law Sakurai found that by changing the exponent of the square law, a better fit can be found with simple calculations. Shockley (α=2) Alpha (α=1.3) W I C V V 2L DSAT n ox GS T The Switch The Piece-wise Linear The Square Law The V-Sat The Unified The VT* The Alpha Power Law 18

BSIM The main model used by simulators today is the BSIM4 model. This model uses hundreds of parameters to achieve a good fit. This model takes into account all known physical effects, as well as many fitting parameters. The Switch The Piece-wise Linear The Square Law The V-Sat The Unified The VT* The Alpha Power Law BSIM 19

Newer s BSIM Group Webpage: http://www-device.eecs.berkeley.edu/bsim/ Compact Coalition (CMC) Webpage: https://www.si2.org/cmc_index.php Newer BSIM s: BSIM6 Bulk CMOS BSIMSOI - SoI model standardized in 2001 (built on BSIM3.3) BSIM-CMG multi-gate FETs (FinFet, Nanowire) written in Verilog-A BSIM-IMG Independent Multi-Gate for UTBB-SoI EKV : http://ekv.epfl.ch/ Developed in 1995 to provide accuracy even in subthreshold PSP: http://psp.ewi.tudelft.nl/ Standard for current bulk CMOS The Switch The Piece-wise Linear The Square Law The V-Sat The Unified The VT* The Alpha Power Law BSIM And more 20

21 Threshold Voltage Revisited

Energy Band Diagrams To understand the threshold voltage and other secondary effects of the MOS device, we often use energy band diagrams. The first approach is looking in from the gate: 22

Energy Band Diagrams The second approach is looking from the source to the drain. 23

Threshold Voltage - Basic Theory Basic Theory The basic definition of threshold voltage is the gate voltage (V G ) required to invert the channel V Q OX T 0 MS 2 F Cox Q C dep ox Q 2qN 2 dep A si F N A F T ln T n i kt q 24

Body The appearance of a voltage difference between the source and body (V SB ) is known as The Body This can be modeled by the additional charge that needs to be depleted. Basic Theory Classic Body Q 2qN 2 V dep A si F SB V V 0 2 V 2 T T F SB F 25 V Q ox T 0 MS 2 F Cox Q dep0 C ox 2q si N A C ox

Modern Body A different approach is to look at the capacitive voltage divider between the gate and body (C GB ) Basic Theory Classic Body Modern Body C dep s W d max V S S V G G C C oxe 26 Q C V V V C V V inv oxe GS CS T 0 dep SB CS C dep Coxe VGS nvcs VT 0 n 1 1 C oxe 3T W oxe d max V B B C dep

Modern Body This can be shown to redefine V T as: C V V V V C ( ) dep T SB T0 SB oxe Basic Theory Classic Body Modern Body In modern technologies, C dep /C oxe is a constant, so V T is linearly dependent on V SB! 27

Poly Depletion and Channel Depth Basic Theory The threshold voltage is affected by two additional factors that we have disregarded until now: Polysilicon Depletion Since polysilicon is, itself, a semiconductor, the depletion layer into the poly effectively increases the oxide thickness. Classic Body Modern Body Channel Depth Since the channel is not a 2-dimensional line along the surface, the oxide thickness is essentially increased. n Cdep 1 1 C oxe 3T W oxe d max 28

Hot Carrier s Electrons can get so fast that they can tunnel into the gate oxide and increase the threshold voltage. V OX T 0 MS 2 F Cox This is a reliability issue as it happens over time. Q Q C dep ox Basic Theory Classic Body Modern Body Hot Carriers 29

V T Roll Off (Short Channel ) As channel length is reduced, effective channel length is reduced by depletion regions. Basic Theory Classic Body Modern Body Hot Carriers VT Roll-Off A trapezoid is created under the gate, dividing the channel into the region controlled by the gates and by the drain. 65nm technology. t ox =1.2nm V dd =1V K. Goto et al., IEDM 2003 30 In essence, V T is reduced.

DIBL (Drain Induced Barrier Lowering) In short channels, the barrier of the channel is essentially lowered, as the drain causes the energy band to drop closer to the source. This is exponentially dependent on V DS. Basic Theory Classic Body Modern Body Hot Carriers VT Roll-Off DIBL 31 V V V 0.4 T T,long DS C C d oxe

Roll Off / DIBL combined Basic Theory Classic Body Modern Body Hot Carriers VT Roll-Off DIBL 32

Reverse Short Channel (RSCE) V T actually increases at channel lengths a bit higher than minimum Basic Theory Classic Body Modern Body Hot Carriers VT Roll-Off DIBL RSCE 33

How to Measure VT There are various ways to measure V T One classic way takes a small V DS and sweeps V GS. Basic Theory Classic Body Modern Body 2 Id k ( Vgs Vt ) Vds 0.5V ds Vgs Vt So we can find the V GS at which the linear part crosses I ds =0. V T,gm V DS =50mV Hot Carriers VT Roll-Off DIBL RSCE Measuring VT 34

How to Measure VT One of the more common ways is to find the V GS at which I DS =100 na x W/L. For V T,lin, set a low V DS (V DS =50mV) For V T,sat set a high V DS (V DS =V DD ) Basic Theory Classic Body Modern Body Hot Carriers VT Roll-Off DIBL RSCE Measuring VT 35

OP and MP in Spectre Basic Theory Classic Body Modern Body Hot Carriers VT Roll-Off DIBL RSCE Measuring VT 36

Further Reading J. Rabaey, Digital Integrated Circuits 2003, Chapters 2.5, 3.3-3.5 Weste, Harris CMOS VLSI Design, Chapter 7 C. Hu, Modern Semiconductor Devices for Integrated Circuits, 2010, Chapters 4-7 Tzividis, et al. Operation and ing of MOS Transistor Chapters 1-5 E. Alon, Berkeley EE-141, Lecture 9 (Fall 2009) M. Alam, Purdue ECE-606 lectures 32-38 (2009) nanohub.org A. B. Bhattacharyya Compact MOSFET models for VLSI design, 2009, T. Sakurai, Alpha Power-Law MOS JSSC Newsletter Oct 2004 Managing Process Variation in Intel s 45nm CMOS Technology, Intel Technology Journal, 2008 Berkeley BSIM 4.6.4 User s Manual http://www-device.eecs.berkeley.edu/~bsim/bsim4/bsim464/bsim464_manual.pdf 37