Lecture 11: Adders. Slides courtesy of Deming Chen. Slides based on the initial set from David Harris. 4th Ed.

Similar documents
Where are we? Data Path Design

Where are we? Data Path Design. Bit Slice Design. Bit Slice Design. Bit Slice Plan

Lecture 4. Adders. Computer Systems Laboratory Stanford University

Full Adder Ripple Carry Adder Carry-Look-Ahead Adder Manchester Adders Carry Select Adder

EECS 427 Lecture 8: Adders Readings: EECS 427 F09 Lecture 8 1. Reminders. HW3 project initial proposal: due Wednesday 10/7

Homework 4 due today Quiz #4 today In class (80min) final exam on April 29 Project reports due on May 4. Project presentations May 5, 1-4pm

Bit-Sliced Design. EECS 141 F01 Arithmetic Circuits. A Generic Digital Processor. Full-Adder. The Binary Adder

EE141-Fall 2010 Digital Integrated Circuits. Announcements. An Intel Microprocessor. Bit-Sliced Design. Class Material. Last lecture.

Hw 6 due Thursday, Nov 3, 5pm No lab this week

ISSN (PRINT): , (ONLINE): , VOLUME-4, ISSUE-10,

Overview. Arithmetic circuits. Binary half adder. Binary full adder. Last lecture PLDs ROMs Tristates Design examples

VLSI Design I; A. Milenkovic 1

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Arithmetic Circuits Didn t I learn how to do addition in the second grade? UNC courses aren t what they used to be...

CMPUT 329. Circuits for binary addition

Digital Integrated Circuits A Design Perspective

CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design

Fundamentals of Computer Systems

VLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1

EE141- Spring 2004 Digital Integrated Circuits

EECS150. Arithmetic Circuits

Arithmetic Building Blocks

EFFICIENT MULTIOUTPUT CARRY LOOK-AHEAD ADDERS

L8/9: Arithmetic Structures

CSE477 VLSI Digital Circuits Fall Lecture 20: Adder Design

Parallelism in Computer Arithmetic: A Historical Perspective

EECS150 - Digital Design Lecture 10 - Combinational Logic Circuits Part 1

EECS150 - Digital Design Lecture 22 - Arithmetic Blocks, Part 1

CMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays

CS 140 Lecture 14 Standard Combinational Modules

Floating Point Representation and Digital Logic. Lecture 11 CS301

CSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego

ECE 645: Lecture 3. Conditional-Sum Adders and Parallel Prefix Network Adders. FPGA Optimized Adders

Lecture 12: Datapath Functional Units

The equivalence of twos-complement addition and the conversion of redundant-binary to twos-complement numbers

Binary addition by hand. Adding two bits

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Computer Architecture 10. Fast Adders

Review. EECS Components and Design Techniques for Digital Systems. Lec 18 Arithmetic II (Multiplication) Computer Number Systems

Homework #2 10/6/2016. C int = C g, where 1 t p = t p0 (1 + C ext / C g ) = t p0 (1 + f/ ) f = C ext /C g is the effective fanout

Part II Addition / Subtraction

Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two.

ECE 2300 Digital Logic & Computer Organization

Looking at a two binary digit sum shows what we need to extend addition to multiple binary digits.

Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space

Logic Synthesis and Verification

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Digital Logic

GALOP : A Generalized VLSI Architecture for Ultrafast Carry Originate-Propagate adders

Reversible ALU Implementation using Kogge-Stone Adder

Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space

EE141. Administrative Stuff

The logic is straightforward. Adding two 0s will result in 0. Adding two 1s results in 10 where 1 is the carry bit and 0 is the sum bit.

Part II Addition / Subtraction

Implementation of Reversible ALU using Kogge-Stone Adder

Hardware Design I Chap. 4 Representative combinational logic

3. Combinational Circuit Design

Chapter 5 Arithmetic Circuits

Computer Architecture. ESE 345 Computer Architecture. Design Process. CA: Design process

Area-Time Optimal Adder with Relative Placement Generator

Design of A Efficient Hybrid Adder Using Qca

Implementation of Carry Look-Ahead in Domino Logic

CMSC 313 Lecture 16 Announcement: no office hours today. Good-bye Assembly Language Programming Overview of second half on Digital Logic DigSim Demo

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

CMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays

CMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps

CPE/EE 427, CPE 527 VLSI Design I L07: CMOS Logic Gates, Pass Transistor Logic. Review: CMOS Circuit Styles

Quantum Carry-Save Arithmetic

9. Datapath Design. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017

Slide Set 6. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Basic Gate Repertoire

Lecture 6: DC & Transient Response

Arithmetic Circuits How to add and subtract using combinational logic Setting flags Adding faster

CPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles

14:332:231 DIGITAL LOGIC DESIGN

Design and Implementation of Carry Tree Adders using Low Power FPGAs

Latches. October 13, 2003 Latches 1

CMSC 313 Lecture 15 Good-bye Assembly Language Programming Overview of second half on Digital Logic DigSim Demo

Design of a Novel Reversible ALU using an Enhanced Carry Look-Ahead Adder

1 Short adders. t total_ripple8 = t first + 6*t middle + t last = 4t p + 6*2t p + 2t p = 18t p

Addition and Subtraction

Very Large Scale Integration (VLSI)

CSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing

A General Method for Energy-Error Tradeoffs in Approximate Adders

CprE 281: Digital Logic

Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI

Adders allow computers to add numbers 2-bit ripple-carry adder

ECE429 Introduction to VLSI Design

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic

Digital- or Logic Circuits. Outline Logic Circuits. Logic Voltage Levels. Binary Representation

Chapter #7: Sequential Logic Case Studies Contemporary Logic Design

Lecture 7: Logic design. Combinational logic circuits

Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components

ARITHMETIC COMBINATIONAL MODULES AND NETWORKS

Adders, subtractors comparators, multipliers and other ALU elements

Lecture 5: Arithmetic

CSEE 3827: Fundamentals of Computer Systems. Combinational Circuits

Serial Parallel Multiplier Design in Quantum-dot Cellular Automata

ECE 425 Midterm Overview. Fall 2017

Lecture 8: Logic Effort and Combinational Circuit Design

Lecture 12: Datapath Functional Units

Transcription:

Lecture : dders Slides courtesy of Deming hen Slides based on the initial set from David Harris MOS VLSI Design

Outline Single-bit ddition arry-ripple dder arry-skip dder arry-lookahead dder arry-select dder arry-increment dder Tree dder Readings:.-.2.2.8 2

Single-it ddition Half dder S out out S Full dder S out (,, ) S out S out S 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 MJ out

PGK For a full adder, define what happens to carries (in terms of and ) Generate: out = independent of G = Propagate: out = P = Kill: out = 0 independent of K = ~ ~ 4

MJ Full dder Design I rute force implementation from eqns S out MJ (,, ) S out S out 5

Full dder Design II Factor S in terms of out S = + ( + + )(~ out ) ritical path is usually to out in ripple adder MINORITY out S S out 6

Layout lever layout circumvents usual line of diffusion Use wide transistors on critical path Eliminate output inverters 7

Full dder Design III omplementary Pass Transistor Logic (PL) Slightly faster, but more area S out S out 8

arry Propagate dders N-bit adder called P Each sum bit depends on all previous carries How do we compute all these carries quickly? N... N... out 00000 + in +0000 +0000 0000 S N... out in out in carries 4... 4... S 4... 9

arry-ripple dder Simplest design: cascade full adders ritical path goes from in to out Design full adder to have fast carry delay 4 4 3 3 2 2 out in 3 2 S 4 S 3 S 2 S 0

Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j G G P G i: j i: k i: k k : j P P P i: j i: k k : j 0:00:00inGP ase case G G Sum: i: i i i i P P i: i i i i Si Pi Gi :0 G0:0 G0 in P0:0 P0 0

PG Logic 4 4 3 3 2 2 in G 4 P 4 G 3 P 3 G 2 P 2 G P G 0 P 0 : itwise PG logic 2: Group PG logic G 3:0 G 2:0 G :0 G 0:0 3 2 0 3: Sum logic 4 out S 4 S 3 S 2 S 2

arry-ripple Revisited G G P G i:0 i i i :0 4 4 3 3 2 2 in G 4 P 4 G 3 P 3 G 2 P 2 G P G 0 P 0 G 3:0 G 2:0 G :0 G 0:0 3 2 0 4 out S 4 S 3 S 2 S 3

Delay arry-ripple PG Diagram it Position 5 4 3 2 0 9 8 7 6 5 4 3 2 0 t t ( N ) t t ripple pg O xor 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 4

PG Diagram Notation lack cell Gray cell uffer i:k k-:j i:k k-:j i:j i:j i:j i:j G i:k P i:k G k-:j G i:j G i:k P i:k G i:j G k-:j G i:j G i:j P k-:j P i:j P i:j P i:j 5

arry-skip dder arry-ripple is slow through all N stages arry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal 6:3 6:3 2:9 2:9 8:5 8:5 4: 4: P 6:3 P 2:9 P 8:5 P 4: 2 8 4 out 0 + 0 + 0 + 0 + in S 6:3 S 2:9 S 8:5 S 4: 6

arry-skip PG Diagram 6 5 4 3 2 0 9 8 7 6 5 4 3 2 0 6:0 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 For k n-bit groups (N = nk) tskip tpg 2 n ( k ) t O t xor 7

Variable Group Size 6 5 4 3 2 0 9 8 7 6 5 4 3 2 0 6:0 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 Delay grows as O(sqrt(N)) 8

arry-lookahead dder arry-lookahead adder computes G i:0 for many bits in parallel. Uses higher-valency cells with more than two inputs. 6:3 6:3 2:9 2:9 8:5 8:5 4: 4: out G 6:3 P 6:3 2 G 2:9 P 2:9 8 G 8:5 P 8:5 4 G 4: P 4: + + + + in S 6:3 S 2:9 S 8:5 S 4: 9

0 0 0 arry-select dder Trick for critical paths dependent on late input X Precompute two possible outputs for X = 0, Select proper output when X arrives arry-select adder precomputes n-bit sums For both possible carries into n-bit group 6:3 6:3 2:9 2:9 8:5 8:5 4: 4: + 0 + 0 + 0 out + 2 + 8 + 4 + in S 6:3 S 2:9 S 8:5 S 4: 20

Tree dder If lookahead is good, lookahead across lookahead! Recursive lookahead gives O(log N) delay Many variations on tree adders 2

rent-kung 5 4 3 2 0 9 8 7 6 5 4 3 2 0 5:4 3:2 :0 9:8 7:6 5:4 3:2 :0 5:2 :8 7:4 3:0 5:8 7:0 :0 3:0 9:0 5:0 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 22

Sklansky 5 4 3 2 0 9 8 7 6 5 4 3 2 0 5:4 3:2 :0 9:8 7:6 5:4 3:2 :0 5:2 4:2 :8 0:8 7:4 6:4 3:0 2:0 5:8 4:8 3:8 2:8 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 23

Kogge-Stone 5 4 3 2 0 9 8 7 6 5 4 3 2 0 5:4 4:3 3:2 2: :0 0:9 9:8 8:7 7:6 6:5 5:4 4:3 3:2 2: :0 5:2 4: 3:0 2:9 :8 0:7 9:6 8:5 7:4 6:3 5:2 4: 3:0 2:0 5:8 4:7 3:6 2:5 :4 0:3 9:2 8: 7:0 6:0 5:0 4:0 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 24

Tree dder Taxonomy Ideal N-bit tree adder would have L = log N logic levels Fanout never exceeding 2 No more than one wiring track between levels Describe adder with 3-D taxonomy (l, f, t) Logic levels: L + l Fanout: 2 f + Wiring tracks: 2 t Known tree adders sit on plane defined by l + f + t = L- 25

Summary dder architectures offer area / power / delay tradeoffs. hoose the best one for your application. rchitecture lassification Logic Levels Max Fanout Tracks arry-ripple N- N ells arry-skip n=4 N/4 + 5 2.25N arry-inc. n=4 N/4 + 2 4 2N rent-kung (L-, 0, 0) 2log 2 N 2 2N Sklansky (0, L-, 0) log 2 N N/2 + 0.5 Nlog 2 N Kogge-Stone (0, 0, L-) log 2 N 2 N/2 Nlog 2 N 26

2024 © sciencedocbox.com Privacy Policy | Terms of Service | Feedback