INTEGRATED CIRCUITS 9-bit dual latch traceiver with 8-bit parity Supersedes data of 993 Oct 4 IC23 Data andbook 998 Jan 6
9-bit dual latch traceiver with 8-bit parity FEATURES Symmetrical (A and B bus functio are identical) Selectable generate parity or feed-through parity for A-to-B and B-to-A directio Independent traparent latches for A-to-B and B-to-A directio Selectable parity Continuously checks parity of both A bus and B bus latches as ERRA and ERRB Ability to simultaneously generate and check parity Can simultaneously read/latch A and B bus data Output capability: +64 ma/ 32mA atch-up protection exceeds 5mA per Jedec JC4.2 Std 7 ESD protection exceeds 2 V per MI STD 883 Method 35 and 2 V per Machine Model Power up 3-State Power-up reset ive iertion/extraction permitted DESCRIPTION The is a 9-bit to 9-bit parity traceiver with separate traparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SE input. Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-State. The features independent latch enables for the A and B bus latches, a select pin for parity, and separate error signal output pi for checking parity. FUNCTIONA DESCRIPTION The has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directio. Traparent latch, Generate parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If EA and EB are igh and the Mode Select (SE) is ow, the parity generated from A-A7 and B-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.) Traparent latch, Feed-through parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A) in a feed-through mode if SE is igh. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU. atched input, Generate/Feed-through parity, Check A (and B) bus parity: Independent latch enables (EA and EB) allow other permutatio of: Traparent latch / bus latched / both buses latched Feed-through parity / generate parity Check in bus parity / check out bus parity / check in and out bus parity QUICK REFERENCE DATA SYMBO t P t P t P t P An to Bn or Bn to An An to ERRA PARAMETER CONDITIONS T amb = 25 C; GND = V TYPICA UNIT C = 5pF; V CC = 5V 2.9 C = 5pF; V CC = 5V 6. C IN Input capacitance V I = V or V CC 4 pf C I/O Output capacitance Outputs disabled; V O = V or V CC 7 pf I CCZ Total supply current Outputs disabled; V CC =5.5V 5 µa ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORT AMERICA NORT AMERICA DWG NUMBER 28-Pin Plastic PCC 4 C to +85 C A A SOT26-3 28-Pin Plastic SOP 4 C to +85 C D D SOT36-28-Pin Plastic SSOP 4 C to +85 C DB DB SOT34-998 Jan 6 2 853-623 8864
9-bit dual latch traceiver with 8-bit parity PIN CONFIGURATION PCC PIN CONFIGURATION 28 V CC ERRA EA 2 27 3 26 OEB B B B2 B3 B4 B5 B6 B7 25 24 23 22 2 2 9 A A A2 A3 A4 A5 A6 A7 4 5 6 7 8 9 TOP VIEW 25 24 23 22 2 2 9 8 B B2 B3 B4 B5 B6 B7 BPAR B 26 OEB 27 V CC 28 ODD/ EVEN ERRA 2 EA A 3 4 8 BPAR 7 EB 6 SE 5 ERRB 4 GND 3 OEA 2 APAR APAR 2 7 EB 5 6 7 8 9 OEA 3 6 SE A A2 A3 A4 A5 A6 A7 GND 4 5 ERRB SA289 SA29 PIN DESCRIPTION SYMBO PIN NUMBER NAME AND FUNCTION OGIC SYMBO A - A7 4, 5, 6, 7, 8, 9,, atched A bus 3-State inputs/outputs 4 5 6 7 8 9 2 B - B7 9, 2, 2, 22, 23, 24, 25, 26 atched B bus 3-State inputs/outputs 3 7 A A A2 A3 A4 A5 A6 A7 APAR EA EB APAR 2 A bus parity 3-State input 6 SE ERRA 2 BPAR 8 B bus parity 3-State input ERRB 5 ODD/ EVEN Parity select input (ow for EVEN parity) 27 3 OEB OEA OEA, OEB 3, 27 Output enable inputs (gate A to B, B to A) B B B2 B3 B4 B5 B6 B7 BPAR SE 6 Mode select input (ow for generate) 26 25 24 23 22 2 2 9 8 EA, EB 3, 7 atch enable inputs (traparent igh) ERRA, ERRB 2, 5 Error signal outputs (active-ow) SA29 GND 4 Ground (V) V CC 28 Positive supply voltage 998 Jan 6 3
9-bit dual latch traceiver with 8-bit parity OE 27 OEB 9 bit Traparent atch 9 bit Output Buffer EA A A A2 A3 A4 A5 A6 A7 APAR 3 4 5 6 7 8 9 2 E Parity Generator mux 26 25 24 23 22 2 2 9 8 B B B2 B3 B4 B5 B6 B7 BPAR 9 bit Output Buffer 9 bit Traparent atch OEA SE 3 6 OE mux Parity Generator E 7 2 EB ERRA 5 ERRB ODD/ EVEN SA292 FUNCTION TABE S OEB OEA SE EA EB OPERATING MODE X X X 3-State A bus and B bus (input A & B simultaneously) B A, traparent B latch, generate parity from B - B7, check B bus parity B A, traparent A & B latch, generate parity from B - B7, check A & B bus parity X B A, B bus latched, generate parity from latched B - B7 data, check B bus parity X B A, traparent B latch, parity feed-through, check B bus parity B A, traparent A & B latch, parity feed-through, check A & B bus parity X A B, traparent A latch, generate parity from A - A7, check A bus parity A B, traparent A & B latch, generate parity from A - A7, check A & B bus parity X A B, A bus latched, generate parity from latched A - A7 data, check A bus parity A B, traparent A latch, parity feed-through, check A bus parity A B, traparent A & B latch, parity feed-through, check A & B bus parity X X X Output to A bus and B bus (NOT AOWED) = igh voltage level = ow voltage level X = Don t care 998 Jan 6 4
9-bit dual latch traceiver with 8-bit parity PARITY AND ERROR FUNCTION TABE S S SE xpar (A or B) Σ of igh Inputs xpar (B or A) ERRt ERRr* PARITY MODES Mode Feed-through/check parity Mode Mode Generate parity Mode = igh voltage level = ow voltage level t = Tramit if the data path is from A B then ERRt is ERRA r = Receive if the data path is from A B then ERRr is ERRB * Blocked if latch is not traparent ABSOUTE MAXIMUM RATINGS, 2 SYMBO PARAMETER CONDITIONS RATING UNIT V CC DC supply voltage.5 to +7. V I IK DC input diode current V I < 8 ma V I DC input voltage 3.2 to +7. V I OK DC output diode current V O < 5 ma V OUT DC output voltage 3 output in Off or igh state.5 to +5.5 V I OUT DC output current output in ow state 28 ma T stg Storage temperature range 65 to 5 C NOTES:. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 55C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 998 Jan 6 5
9-bit dual latch traceiver with 8-bit parity RECOMMENDED OPERATING CONDITIONS SYMBO PARAMETER IMITS UNIT Min Max V CC DC supply voltage 4.5 5.5 V V I Input voltage V CC V V I igh-level input voltage 2. V V I ow-level Input voltage.8 V I O igh-level output current 32 ma I O ow-level output current 64 ma t/ v Input traition rise or fall rate 5 /V T amb Operating free-air temperature range 4 +85 C DC EECTRICA CARACTERISTICS IMITS SYMBO PARAMETER TEST CONDITIONS T amb = +25 C T amb = 4 C to +85 C UNIT Min Typ Max Min Max V IK Input clamp voltage V CC = 4.5V; I IK = 8mA.9.2.2 V V CC = 4.5V; I O = 3mA; V I = V I or V I 2.5 3.5 2.5 V V O igh-level output voltage V CC = 5.V; I O = 3mA; V I = V I or V I 3. 4. 3. V V CC = 4.5V; I O = 32mA; V I = V I or V I 2. 2.6 2. V V O ow-level output voltage V CC = 4.5V; I O = 64mA; V I = V I or V I.42.55.55 V V RST Power-up output low voltage 3 V CC = 5.5V; I O = ma; V I = GND or V CC.3.55.55 V I I Input leakage Control pi V CC = 5.5V; V I = GND or 5.5V ±. ±. ±. µa current Data pi V CC = 5.5V; V I = GND or 5.5V ±5 ± ± µa I OFF Power-off leakage current V CC =.V; V O or V I 4.5V ±5. ± ± µa I PU /I PD Power-up/down 3-State V CC = 2.V; V O =.5V; V I = GND or V CC ; output current 4 V OE = Don t care ±5. ±5 ±5 µa I I + I OZ 3-State output igh current V CC = 5.5V; V O = 2.7V; V I = V I or V I 5. 5 5 µa I I + I OZ 3-State output ow current V CC = 5.5V; V O =.5V; V I = V I or V I 5. 5 5 µa I CEX Output igh leakage current V CC = 5.5V; V O = 5.5V; V I = GND or V CC 5. 5 5 µa I O Output current V CC = 5.5V; V O = 2.5V 5 8 8 5 8 ma I CC V CC = 5.5V; Outputs igh, V I = GND or V CC 5 25 25 µa I CC Quiescent supply current V CC = 5.5V; Outputs ow, V I = GND or V CC 28 34 34 ma I CCZ V CC = 5.5V; Outputs 3-State; V I = GND or V CC 5 25 25 µa I CC Additional supply current per input pin 2 V CC = 5.5V; one input at 3.4V, other inputs at V CC or GND.3.5.5 ma NOTES:. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any V CC between V and 2.V, with a traition time of up to msec. From V CC = 2.V to V CC = 5V ± %, a traition time of up to µsec is permitted. 998 Jan 6 6
9-bit dual latch traceiver with 8-bit parity AC CARACTERISTICS GND = V; t R = t F = 2.5; C = 5pF, R = 5Ω SYMBO PARAMETER WAVEFORM t P t P t P t P t P t P t P t P t P t P t P t P t P t P t P t P t P t P t P t P t P t P t P t P t PZ t PZ t PZ t PZ An to Bn or Bn to An An to BPAR or Bn to APAR An to ERRA or Bn to ERRB APAR to BPAR or BPAR to APAR APAR to ERRA or BPAR to ERRB to APAR or BPAR to ERRA or ERRB SE to APAR or BPAR SE to ERRA or ERRB EA to Bn or EB to An EA to BPAR or EB to APAR EA to ERRA or EB to ERRB Output enable time OEA to An, APAR or OEB to Bn, BPAR Output disable time OEA to An, APAR or OEB to Bn, BPAR 2 3 6 5 4 8 8 9 9 7, 2, 2 T amb = +25 o C V CC = +5.V C = 5pF R = 5Ω IMITS T amb = 4 to +85 o C V CC = +5.V ±% C = 5pF R = 5Ω Min Typ Max Min Max.. 3. 2.5 2.8 2.8 2..3.5.5 2.6 2.5 2.3 2.6.3.4 3.7 5... 2..7 2. 2.....5 3.2 2.7 6. 6.4 6. 6.7 4. 3.2 4.2 4. 5.5 5.3 5.4 5.7 4. 4. 6.8 8.3 3.2 3. 6.8 6.3 6.3 7. 3. 3.4 3.4 3. 4.5 4. 7.5 7.9 8. 8.5 5.2 4.4 5.4 5.4 6.8 6.7 6.8 7.2 5.2 5.3 8.3 9.7 4.4 4.5 8.3 7.9 8.3 9.2 4.3 4.8 4.7 4.2.. 3. 2.5 2.8 2.8 2..3.5.5 2.6 2.5 2.3 2.6.3.4 3.7 5... 2..7 2. 2.....5 4.9 4.6 9. 8.8 9. 9.3 5.7 5. 6. 6. 8. 7.8 7.9 8.4 6. 5.9 9.8. 4.9 5. 9.7 9. 9.6.3 5. 5.4 5.5 4.7 UNIT AC SETUP REQUIREMENTS GND = V; t R = t F = 2.5; C = 5pF, R = 5Ω SYMBO PARAMETER WAVEFORM t s () t s () t h () t h () t w () Setup time, igh or ow An, APAR to EA or Bn, BPAR to EB old time, igh or ow An, APAR to EA or Bn, BPAR to EB Pulse width, igh EA or EB T amb = +25 o C V CC = +5.V C = 5pF R = 5Ω IMITS T amb = 4 to +85 o C V CC = +5.V ±% C = 5pF R = 5Ω Min Typ Max Min Max 2..5.5..4...2 2..5.5. UNIT 3..9 3. 998 Jan 6 7
9-bit dual latch traceiver with 8-bit parity AC WAVEFORMS =.5V, V IN = GND to 3.V SE An, APAR (Bn, BPAR) t P t P Bn, BPAR (An, APAR) SA293 Waveform. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR SE EA (EB) An (Bn) ODD PARITY EVEN PARITY ODD PARITY t P t P BPAR (APAR) NOTE: Only even parity mode is shown, odd parity mode would be with = Waveform 2. Propagation Delay, An to BPAR or Bn to APAR SA294 APAR (BPAR) EA (EB) An (Bn) ODD PARITY EVEN PARITY ODD PARITY t P t P ERRA (ERRB) NOTE: Only even parity mode is shown, odd parity mode would be with = Waveform 3. Propagation Delay, An to ERRA or Bn to ERRB SA295 998 Jan 6 8
9-bit dual latch traceiver with 8-bit parity APAR (BPAR) An (Bn) EVEN PARITY t P t P ERRA (ERRB) NOTE: Only even parity mode is shown, odd parity mode would cause inverted output SA296 Waveform 4. Propagation Delay, to ERRA or to ERRB SE APAR (BPAR) An (Bn) EVEN PARITY t P t P BPAR (APAR) NOTE: Only even parity mode is shown, odd parity mode would cause inverted output SA297 Waveform 5. Propagation Delay, to APAR or to BPAR 998 Jan 6 9
9-bit dual latch traceiver with 8-bit parity An (Bn) EVEN PARITY APAR (BPAR) t P t P ERRA (ERRB) NOTE: Only even parity mode is shown with even parity. parity mode would cause inverted output and odd parity mode would be with = SA298 Waveform 6. Propagation Delay, APAR to ERRA or BPAR to ERRB APAR (BPAR) An (Bn) EVEN PARITY ODD PARITY EVEN PARITY EA (EB) t P t P ERRA (ERRB) NOTE: Only odd parity mode is shown. parity mode would be with = o Waveform 7. Propagation Delay, EA to ERRA or EB to ERRB SA299 998 Jan 6
9-bit dual latch traceiver with 8-bit parity APAR (BPAR) An (Bn) EVEN PARITY SE t P t P BPAR (APAR) NOTE: Only even parity mode is shown with even parity. parity mode would cause inverted output and odd parity mode would be with = SA3 Waveform 8. Propagation Delay, SE to BPAR or SE to APAR SE APAR, An] (BPAR, Bn) EA (EB) t P t P Bn, BPAR (An, APAR) SA3 Waveform 9. Propagation Delay, EA to BPAR or EB to APAR, EA to Bn or EB to An APAR, BPAR, An, Bn ÉÉÉ ÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ t s () t h () t s () t h () EA, EB t w () The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform. Data Setup and old Times, Pulse Width igh SA32 998 Jan 6
9-bit dual latch traceiver with 8-bit parity OEA, OEB t PZ t PZ An, APAR, Bn, BPAR V O.3V V SA33 Waveform. 3-State Output Enable Time to igh evel and Output Disable Time from igh evel OEA, OEB t PZ t PZ An, APAR, Bn, BPAR V O +.3V SA34 Waveform 2. 3-State Output Enable Time to ow evel and Output Disable Time from ow evel TEST CIRCUIT AND WAVEFORM From Output Under Test C = 5 pf 5 Ω 5 Ω S 7 V Open GND oad Circuit TEST t pd t PZ /t PZ t PZ /t PZ S open 7 V open DEFINITIONS C = oad capacitance includes jig and probe capacitance; see AC CARACTERISTICS for value. SA2 998 Jan 6 2
9-bit dual latch traceiver with 8-bit parity PCC28: plastic leaded chip carrer; 28 leads; pedestal SOT26-3 998 Jan 6 3
9-bit dual latch traceiver with 8-bit parity SO28: plastic small outline package; 28 leads; body width 7.5mm SOT36-998 Jan 6 4
9-bit dual latch traceiver with 8-bit parity SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm SOT34-998 Jan 6 5
9-bit dual latch traceiver with 8-bit parity Data sheet status Data sheet status Product status Definition [] Objective specification Preliminary specification Product specification Development Qualification Production This data sheet contai the design target or goal specificatio for product development. Specification may change in any manner without notice. This data sheet contai preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contai final specificatio. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [] Please coult the most recently issued datasheet before initiating or completing a design. Definitio Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. imiting values definition imiting values given are in accordance with the Absolute Maximum Rating System (IEC 34). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditio above those given in the Characteristics sectio of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applicatio that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applicatio will be suitable for the specified use without further testing or modification. Disclaimers ife support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applicatio do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no respoibility or liability for the use of any of these products, conveys no licee or title under any patent, copyright, or mask work right to these products, and makes no representatio or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 8 East Arques Avenue P.O. Box 349 Sunnyvale, California 9488 349 Telephone 8-234-738 Copyright Philips Electronics North America Corporation 998 All rights reserved. Printed in U.S.A. print code Date of release: 5-96 Document order number: 9397-75-3478 yyyy mmm dd 6