Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator

IEEE TRANSACTIONS ON COMPUTERS, VOL, NO, FEBRUARY Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator Prabir Dasgupta, Santanu Chattopadhyay, P Pal Chaudhuri, and Indranil Sengupta AbstractÐThis paper presents a recursive technique for generation of pseudoexhaustive test patterns The scheme is optimal in the sense that the first k vectors cover all adjacent k-bit spaces exhaustively It requires substantially lesser hardware than the existing methods and utilizes the regular, modular, and cascadable structure of local neighborhood Cellular Automata (CA), which is ideally suited for VLSI implementation In terms of XOR gates, this approach outperforms earlier methods by to percent Moreover, test effectiveness and hardware requirements have been established analytically, rather than by simple simulation and logic minimization Index TermsÐData path architecture, pseudoexhaustive testing, BIST, cellular automata INTRODUCTION æ WITH the maturity of VLSI technology, the complexity of circuits housed on a silicon floor is growing significantly Unfortunately, test technology has failed to match this growth in circuit complexity Consequently, improvements in testing schemes are constantly sought With this goal in mind, this paper proposes an on-chip test generation scheme that reduces the test overhead significantly For complex circuits with a large number of inputs, pseudoexhaustive testing has been found to be suitable for many cases where each of the outputs depends only on a subset of the inputs [] This results in much smaller test size compared to the exhaustive test size of n for n-input circuit under test (CUT) Several schemes for generation of n-bit patterns with all m bits m <n exhaustively covered have been studied in [], [3], [], [] Schemes based on linear cyclic codes [3], [], [], constant weight vectors [], iterative procedure [], etc, have been reported Implementation of a pseudoexhaustive testing scheme based on punctured cyclic codes has been studied in [] and schemes for generation of exhaustive test patterns on one or several subsets of cell positions of a long shift register have been reported in [8] In most of the above approaches, the goal is to generate exhaustive patterns in all possible combinations of m cell positions m <n of the n-bit LFSR For achieving this capability, the test size inevitably becomes at least double m, except for constant weight vector generation scheme [], which accomplishes the task with lowest test length but higher implementation cost Das and Chaudhuri [9] reported a Cellular Automata (CA) based scheme for pseudoexhaustive test pattern generation which exploits the cyclic decomposition of total vector space generated by a group P Dasgupta is with the Variable Energy Cyclotron Centre, /AF, Bidhan Nagar, Calcutta-, India E-mail: pdgupta@hotmailcom S Chattopadhyay is with the Department of Computer Science and Engineering, Indian Institute of Technology, Guwahati, Guwahati-8, India E-mail: c_santanu@posstmarknet PP Chaudhuri is with the Department of Computer Science and Technology, Bengal Engineering College (Deemed University), Howrah- 3, India E-mail: ppc@becsacin I Sengupta is with the Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, Kharagpur-3, India E-mail: isg@cseiitkgpernetin Manuscript received June 99; revised June 999; accepted 3 Apr For information on obtaining reprints of this article, please send e-mail to: tc@computerorg, and reference IEEECS Log Number 8 Fig Contiguous -bit subspaces CA But, this may require more than i time-steps for generating i-bit pseudoexhaustive patterns Moreover, pseudoexhaustive testing of building blocks of certain types of circuits, such as digital signal processing systems, data-path architectures, and embedded memories, requires a special type of pattern set Here, an n-bit space is said to be pseudoexhaustively covered if, for all (n k ) contiguous k-bit subspaces, each of the possible k patterns occur at least once Pseudoexhaustive (RPE) Such testing schemes are known as Recursive testing schemes The RPE test pattern set for -bit test vectors with -bit pseudoexhaustive covering is given below Fig illustrates the case of recursive pseudoexhaustive pattern generation for n ˆ, k ˆ Such a type of recursive pseudoexhaustive (RPE) test pattern generation cannot be handled with the CA-based schemes proposed in [9] Section briefly introduces the theory of RPE test pattern generation Section 3 builds the analytical basis of the RPE test pattern generation scheme using cellular automata The implementation details are noted in Section RECURSIVE PSEUDOEXHAUSTIVE (RPE) TEST PATTERN GENERATION A set of n-bit test patterns is said to be recursive pseudoexhaustive if any subset of k contiguous patterns of it exhaustively covers all possible k-bit subspaces For example, Table provides the list of RPE test vectors for string length n ˆ and -bit (k ˆ ) contiguous subspace So, the first 3 (ˆ ) vectors cover all -bit subspaces exhaustively First, two test vectors cover all -bit subspaces, first vectors cover all -bit subspaces, first 8 vectors cover all 3-bit subspaces, exhaustively, and so on RPE test pattern generation based on characteristic function was elaborated in [] In the following, we briefly introduce the RPE test pattern generation scheme presented in [] Let P be an ordered set of k binary strings of k-bit each, such that all i-bit contiguous subspaces ( i<k ) are covered exhaustively in consecutive i steps Let P be described by the characteristic function f k x x x k, which equals if vector x ;x ; ::::x k ŠP and zero otherwise So, f k x x x k describes the complementary set P such that P [ P exhaustively covers the k-bit space Now, if a new kth bit is appended at the most significant position of each vector of set P, then all new i-subspaces comprising this bit x k are exhaustively covered if the characteristic function f k x x x k is true (ˆ ) for each such vectors Hence, for such an extended set P e, the characteristic 8-93//$ ß IEEE

8 IEEE TRANSACTIONS ON COMPUTERS, VOL, NO, FEBRUARY TABLE Test Vectors for n ˆ and k ˆ function which features exhaustive coverage of all i-bit ( i<k ) contiguous subspaces is: f k x x x k f k x x x k Similarly, the characteristic function for the set P e is: f k x x x k f k x x x k Now, P e [ P e features exhaustive coverage of contiguous subspaces upto size k and is described by the characteristic function: f k x x x k ˆf k x x x k f k x x x k f k x x x k f k x x x k ) f k x x x k ˆf k x x x k f k x x x k : Starting with f x ˆx, one can recursively generate successive characteristic functions as: f x x ˆf x f x ˆx x ˆ x x f x x x ˆf x x f x x ˆx x f 3 x x x x 3 ˆf x x x f x x x 3 ˆx x x x 3 f x x x x 3 x ˆf 3 x x x x 3 f 3 x x x 3 x ˆx x : It has been shown in [] that if there are two vectors v and v such that f k v ˆf k v, then f k v v ˆ So, to generate patterns satisfying f k x x x k, one can take any vector v such that f k v ˆ and perform bitwise XOR of the vector v with successive v i s for which f k v i ˆ For generating patterns of string length n and k-bit contiguous subspace, one can follow the same method; starting with the all-zero vector, already existing binary patterns are inverted employing successive characteristic functions The number of k-bit contiguous subspaces is n k and some of them will overlap So, the inversion vector should be product of respective characteristic functions; this is defined as inversion mask for generating test vectors (length ˆ n) of k-bit contiguous subspaces, and is denoted by

IEEE TRANSACTIONS ON COMPUTERS, VOL, NO, FEBRUARY 9 Fig Structure of the inversion masks m n k x x x n ˆ n k iˆ f k x x i k : Test patterns can be generated by inverting with each of the so-far generated test vectors of k -bit contiguous subspaces Theorem Given the characteristic function f p, any corresponding inversion mask features s on bit position i which satisfy the relation p ^ i ˆ p [] The resultant structures of the inversion masks are shown in Fig Starting with the all-zero test pattern vector v, the successive test patterns can be recursively generated as follows: 3 CELLULAR AUTOMATA CHARACTERISTICS Cellular Automata (CA) consists of a number of interconnected cells arranged spatially in a regular manner [], [] Here, we consider simple -state per cell 3-neighborhood CA with cells arrayed linearly in one dimension The output q i of the ith cell depends on itself and its left and right neighbor at the most, given by q i t ˆf q i t ;q i t ;q i t

8 IEEE TRANSACTIONS ON COMPUTERS, VOL, NO, FEBRUARY Fig 3 Mask patterns generated by CA for n ˆ 8, denotes inversion Function f is XOR function for linear CA If the next state function of a cell is expressed in the form of a truth table, then the decimal equivalent of the output column in the truth table is conventionally called the rule number for the cell [] Upon minimization, the truth tables for rules and result in the following logic functions: rule : q i t ˆq i t q i t left & self dependencyš rule : q i t ˆq i t self dependencyš: In total, there are seven (, 9,,,,, ) linear rules with XOR logic [3] If f t is the column vector representing the state of the automata at the tth instant of time, then next state for a linear CA is f t ˆ T f t, where T is the characteristic matrix of the CA;

IEEE TRANSACTIONS ON COMPUTERS, VOL, NO, FEBRUARY 8 Fig A -cell - CA: (a) structure, (b) characteristic matrix, (c) state-transition graph T i; j ˆ iff output of the ith cell depends on the jth cell and zero otherwise A CA is called a Group CA if its characteristic matrix T is nonsingular State transition graph of such a CA (as shown in Fig ) consists of a set of cycles If T is singular, then the CA is called Nongroup CA State transition graph of such a CA contains some tree-like structures, apart from the cycles Theory and many applications of Additive Cellular Automata have been presented in [] Group CA has been extensively studied in [9], [3], [], [], [], [8] Many applications have also been reportedðpseudorandom [3] and pseudoexhaustive pattern generation [9], signature analysis [], [9], delay-fault testing [], error-correcting codes [], [], cryptography [3], and synthesis of testable FSM [] In the following section, we enumerate the properties of CA that enables it to generate the mask patterns 3 CA Characteristics for Mask Generation Let us consider an unrestricted neighborhood linear CA of characteristic matrix T c, where the lower triangle has all s and upper triangle all zeros as shown below 3 : Then, starting with an input string of all s, such a CA will directly generate the successive mask patterns, as shown in Fig 3 However, for the n-bit test vector string, this will require n = XOR gates with inputs (fan in) up to n Interestingly, the inverse of this CA, with characteristic matrix T x ˆ Tc is restricted within the 3-neighborhood and requires only -input XOR-gates T x ˆ T c 3 ˆ 3 ˆ : This CA can be realized with - structure having the first cell governed by rule and the rest by rule ; Fig shows such a four-cell CA with its characteristic matrix and transition graph The following theorems and lemmas give the characterization and prove that this CA will generate mask patterns in reverse order Lemma If T is the characteristic matrix of an n-cell - CA, then the jth row (j ˆ ; ; 3; ;n)oft i i ˆ ; ; ;n will have at columns j and j i only Proof The characteristic matrix of a - CA is:

8 IEEE TRANSACTIONS ON COMPUTERS, VOL, NO, FEBRUARY Fig Pseudoexhaustive pattern generation in contiguous p-bit spaces 3 3 T ˆ ˆ 3 ˆ I nn T : Hence, T ˆ I T ˆ I T i Let T ˆ I T i be valid for some i Now, T i ˆ T i T i ˆ IT i i i IT ˆIT Thus, by induction, T m ˆ IT m, for all m> From the construction of T, it follows immediately that, in T k, the jth row will have a at column j k only All the remaining entries are zero Hence, in T i, the jth row will have at column j i only On XORing with the identity matrix, we will have another at the jth column Hence, the proof tu Theorem The period of an n-cell - CA is m such that m <n< m Proof As per Lemma, T m ˆ IT m Since m n, T m ˆ So, T m ˆ I Thus, the period of T is at most m To show the period is no less than m, let us assume the contrary, that is, the period of T is k, where k<m Now, T k ˆ I T k ˆ IT k In each multiplication of the T matrix, the lower diagonal gets shifted further lower by -position Hence, it requires at least n such steps for T n to be Since k<m, T k cannot be the all zero matrix Thus, T ˆ I Hence, a contradiction tu Since the period of the CA is m, the cycle-lengths are factors of m only [] The next theorem finds the length of the cycle on which the state < ::: > lies The states on this cycle generate the masks patterns Theorem 3 In the state-transition graph of an n-cell - CA, the state < ::: > lies on a cycle of length m such that m <n< m Proof From Theorem, the state < ::: > can lie on a cycle of length at most m (since the period of CA is m ) If possible, let the state lie on a cycle of length l, where l<m Then, 3 3 3 T l l ˆ IT ˆ : Multiplication with indentity matrix results in a column vector with first row ªº and the rest all s As proven before, matrix T l will have a ªº at the first column of the l th row On its multiplication, a column vector will result with ªº in the l th row, with the rest of the entries all s So, xoring of these two cannot result in a zero column vector Hence, a contradiction tu The next theorem establishes the capability of the - CA to generate the masks for the recursive pseudoexhaustive pattern generation

IEEE TRANSACTIONS ON COMPUTERS, VOL, NO, FEBRUARY 83 TABLE CA-Based RPE Test Pattern Generation (p ˆ, k ˆ ) Theorem An n-cell - CA seeded with < ::::: > as initial pattern generates the ith mask pattern in the m i th cycle, where m <n< m Proof Let T be the characteristic matrix of the CA, then, as shown in Lemma, it can be decomposed into two matrices I and T For any i, if its binary expression is b k b k b b, where, for all js, b j f; g; let S denote the set consisting of all nonzero b j sof the expression Then, T i ˆ IT i ˆ IT bkk IT bk k IT b : For any k, if b k ˆ, then IT bkk ˆ I, else if b k ˆ, then IT bkk ˆ IT k ˆ IT k Hence, IT k can be replacd by Ib k T k So, T i ˆ I b k T k I b k T k I b T I b T ˆ I b T b T b b T b T b b T b b T b b b T b k T k : 3 In (3), T l will be present iff S l S i Since m <n< m,so the binary expression of n-bit CA requires m number of bits to represent all the states of the CA lying on this cycle; so, if (3) of T i contains T l, then S l S i, ie, l ^ m i ˆ m i Now, with reference to Fig, if we generate the masks in reverse order, starting from the vector < >, then

8 IEEE TRANSACTIONS ON COMPUTERS, VOL, NO, FEBRUARY TABLE 3 Comparision of Overhead in XOR Gates 3 T l ˆ I b T b T b b T b T b b T 3 b b T b b b T b k T k : From the construction of T, it immediately follows that, in T k, the jth row will have ªº at the column j k only; the rest entries are all zeros So, T k: :::Št will have ªº only in the kth bit of the resultant column, all the rest of the entries are zeros Hence, on xoring the columns of (), we get the resultant column vector in which all such lth rows will be ªº and the rest are zeros, where S l S i (that is, iff T l is present in the expression of T i ) So, T i ::Š t will generate a mask vector which will have ªº in all such lth bits, where l ^ m i ˆ m i, with the rest of the entries zero Referring to Theorem and Fig, we see that this is precisely the ith mask pattern (filled dots are considered ªº and the others zero) Hence, the proof tu CABASED IMPLEMENTATION SCHEME The basic scheme of CA based RPE pattern generation for p-bit contiguous case is shown in Fig The length of pattern vector and, hence, the number of CA cells is n, where p <k p and n k Here, CA generates the masks, Counter/shifter keeps the number of test patterns (ˆ k) to be generated, Register outputs the test patterns sequentially The hardware generates the RPE test patterns as per the set of steps described by the following scheme: Initialize Counter to zeros While k patterns are not generated do steps 3 through 9 3 Initialize CA to < ::: > vector, Register to zero Increment Counter/Shifter by Do steps to 8 while CA has not run p cycles Shift left the Counter If load = ªº then Register Register CA content 8 Send a clock pulse to CA

IEEE TRANSACTIONS ON COMPUTERS, VOL, NO, FEBRUARY 8 9 Output test pattern from the Register End An example of pattern generation as per the aforesaid scheme is given in Table Each pattern will be generated after p clock cycles It is optimal in the sense that it covers exhaustively every block of p adjacent bits in the first p pattern vectors This scheme uses a modular cascadable CA with only local interconnections between the cells for parallel generation of test vectors The registers can be realized using data path registers of the computer and does not require any additional cost; the actual overhead is only the number of extra XOR gates present in CA based scheme This, for a p cell CA, will require p plus k XOR gates, that is, p XOR gates Table 3 gives a comparison of hardware overhead in this approach and that in [], for parallel generation of test vectors Comparatively, the CAbased scheme requires to percent less XOR gates than the scheme in [] as test string length increases from to 3 CONCLUSIONS The method proposed in this paper uses Cellular Automata to generate recursive pseudoexhaustive test patterns The proposed CA-based RPE hardware is very useful for built-in self-test of classes of circuits such as digital signal processing systems, datapath architecture, and embedded memories The modular, regular, and cascadable structure of CA makes it highly suitable for VLSI implementation The hardware requirement of the proposed scheme is to percent less compared to the existing reported methods [] and time complexity of generation is linear with respect to test vector set size REFERENCES [] EJ McClusky, ªVerification TestingÐA Pseudoexhaustive Test Technique,º IEEE Trans Computers, vol 33, no, pp -, June 98 [] D Tang and L Woo, ªExhaustive Test Pattern Generation with Constant Weight Vector,º IEEE Trans Computers, vol 3, no, pp -, Dec 983 [3] L Wang and E McClusky, ªCondensed Linear Feedback Shift Register (LFSR) TestingÐA Pseudo-Exhaustive Test Technique,º IEEE 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