Delay Testing from the Ivory Tower to Tools in the Workshop Einar Johan Aas Department of Electronics and Telecommunications, NTNU Nordic Test Forum, Tallinn, 25. November 2008 Name, title of the presentation
OUTLINE Outline Introduction to delay testing Delay fault models Built-In Self Test tactics for path delay faults Current status of application in Norway Trends Conclusion
Some modern products
Why testing? Introduction to testing Why testing?
Testing of an integrated circuit Introduction to testing HOW do you test a circuit with half a billion GHz-transistors? At-speed?
Testing of an integrated circuit Introduction to testing TESTER 10 0 1 10 0 1 0 1 0 1 10 01 01 1 0
Testing of an integrated circuit Introduction to testing Alt1: Use Expensive tester EXPENSIVE TESTER PRICE: 10 0 1 10 0 1 0 1 CHANNEL COUNT: VECTOR MEMORY: SPEED: 0 1 10 01 01 1 0
Testing of an integrated circuit Alt2: Use less expensive tester: Leave some of the test job to the chip. Add de-compressor/compressor on chip Introduction to testing
Testing of an integrated circuit Introduction to testing Alt3: Use Cheaper tester + Built-In Self-Test Leave most of the test job to the chip CHEAPER TESTER PRICE: CHANNEL COUNT: Built-In Self-Test VECTOR MEMORY: SPEED:
Built-In Self-Test Built-In Self-Test facilitates: 10 0 1 10 0 1 0 1 - At-speed testing - Shorter test application time - Cheaper testers can be used 0 1 10 01 01 1 0 - Implemented in both hardware and software
Software based Built-In Self-Test Test Procedure 1. Upload test program to cache 2. Test CPU 3. Use CPU to test other modules 4. Send out result CACHE CPU GPU UART B.TOOTH MPEG
Defect types WHAT can go wrong during the manufacturing process of an integrated circuit? Chinese proverb: There are a thousand diseases but only one healthy state..
Defect types Spot defects Distributed defects
Defect types Short Spot defects Open Distributed defects Variations in: - oxide thickness - doping - polysilicon thickness.
Delay fault: output arrives too late Circuit Under Test CUT passed the delay test Circuit Under Test CUT did not pass the delay test
Delay Fault models Transition delay fault model Gate delay fault model Line delay fault model Path delay fault model Segment delay fault model
Delay Fault models Transition delay fault model Gate delay fault model Line delay fault model Path delay fault model Segment delay fault model
Transition Delay Fault Model Delay fault model based spot defects Assumes the delay fault affects only one gate Slow-to-rise or Slow-to-fall A path through the slow gate can not reach any output in time: T(delay) > T(clock)
Transition Delay Fault Model Similarities with stuck-at fault model: Slow-to-rise : infinitely slow-to-rise Ξ stuck-at-0 Slow-to-fall : infinitely slow-to-fall Ξ stuck-at-1 No. of transition delay faults < no. of stuck-at faults Method to generate test vectors: similar to stuck-at test vectors; but needs vector pair to propagate transition. Important difference: propagate through longest path from faulty gate No. of test vectors: typically 2-3 times as many as stuck-at vectors
Path Delay Fault Model Delay fault model based on distributed defects that accumulate along some path A path has a path-delay fault if T(delay) > T(clock)
PATH DELAY FAULT MODEL Classification of Faults Classification of tests according to quality: A test that has low chance of being invalidated by delays on other paths than the target path, is a high quality test. High Quality Test - example: Can not be invalidated Single path sensitizable fault (SS) MWSCAS 2005
PATH DELAY FAULT MODEL Classification of Faults Lower Quality Test: Can be invalidated 2) Must arrive last 3) -or else no transition can be observed non-robust (NR) test 1) Must arrive first
Path Delay Fault Model Complexity? No. of paths? Finding all paths? Method for vector pair generation? Implementation of Design for Testability logic?
Benefits and problems of the path-delay fault model Detects distributed defects caused by process variations. But also detects spot defects. Number of paths can be exponential due to reconvergent fanout. 2 n paths from input x to output y
Example of paths in a moderately large circuit (c1908): More than 700 000 paths in that circuit!
General requirements: Two pattern tests T = (v 1, v 2 ) Test of a Path-Delay Fault
Test of a Path-Delay Fault General requirements: Two pattern tests T = (v 1, v 2 ) Hold v1 until all signals reach their final value (typically 2T) v2 fire transition at target path [v 1,v 2 ] [0,0] [1,1] [0,1] [0,0] [0,0]
Test of a Path-Delay Fault General requirements: Two pattern tests T = (v 1, v 2 ) Hold v1 until all signals reach their final value v2 fire transition at target path Transition must be propagated along target path Propagated transition: [1,1] Blocked transition: [0,0] [0,0] [v 1,v 2 ] [0,0] [1,1] [0,1] [0,0] [0,0]
Test of a Path-Delay Fault General requirements: Two pattern tests T = (v 1, v 2 ) Hold v1 until all signals reach their final value v2 fire transition at target path Transition must be propagated along target path PDF detected if transition arrives late at output Propagated transition: [1,1] Blocked transition: [0,0] [0,0] [v 1,v 2 ] [0,0] [0,0] [1,1] [1,0] [1,0] [0,1] [0,1] [0,1] [0,0] [0,0] [1,1] [0,0] [1,1] [1,1] [0,0] [0,0]
Non-robust testable path delay faults Non-robust propagation: Off-inputs: non-controlling values under v 2. Non-robust test: Guarantees to detect a path-delay fault, when no other path-delay fault is present.
Simulation alphabet We need to model two-vector events: stable values single transition transitions and settling value Several alphabets exist...
Simulation alphabet Smith s alphabet: [S0, S1, P0, P1, -0, -1] S0: Stable 0 through both test patterns (corresponds to [0,0]) S1: Stable 1 through both test patterns (corresponds to [1,1]) P0: Transition 1->0. (corresponds to [1, 0]) P1: Transition 0->1. (corresponds to [0, 1]) -0 : zero or some transitions before settling to 0-1 : zero or some transitions before settling to 1
Contribution to PDF BIST research [Gj 06] Experimentation platform for PDF BIST Research -Event based simulator -Exact fault grading -PDF ATPG for longest paths - Result analysis tools - Grid computing Path Delay Fault Model (PDF) (Smith) PDF Classification (Cheng, Chen) Enumerative PDF simulator (Kapoor) FAN Algorithm (Fujiwara, Shimono) Automatic Test Pattern Generator for K longest paths (Qiu and Walker)
Experimentation platform for PDF BIST Research -Event based simulator -Exact fault grading -PDF ATPG for longest paths - Result analysis tools - Grid computing Experiments - weighting schemes - accumulator based generators Path Delay Fault Model (PDF) (Smith) PDF Classification (Cheng, Chen) Enumerative PDF simulator (Kapoor) FAN Algorithm (Fujiwara, Shimono) Automatic Test Pattern Generator for K longest paths (Qiu and Walker) Weighted pseudo random generators (Schnurmann, ) Arithmetic Built-In Self-Test (Gupta, Rajski, Tyszer)
Looking for: Single Input Change tests 010010 010110 010110 010010 Proven to be most efficient for path delay fault detection
Stimuli generators GA: Accumulator based generators A i+1 = (A i + C) mod 2 n, A 0 = I Low complexity Not the best pseudo-random properties
Stimuli generators random types GA: Accumulator based generators A i+1 = (A i + C) mod 2 n, A 0 = I Low complexity Not the best pseudo-random properties GT: [golden] Mersenne-Twister based generators Period: 2 19937-1 High complexity Very good pseudo-random properties Mersenne Twister based generator n CUT
Stimuli generators GA: Accumulator based generators A i+1 = (A i + C) mod 2 n, A 0 = I Low complexity Not the best pseudo-random properties GT: Mersenne-Twister based generators Period: 2 19937-1 High complexity Very good pseudo-random properties Implemented as small test programs to be executed from the CPU. Mersenne Twister based generator n CUT
BASIS patterns and Single Input Change (SIC) tests BASIS patterns BASIS patterns in Smith s alphabet SIC tests applied to CUT
Stimuli generators Stimuli generators GA: Accumulator based generators Three different tactics: Unweighted generators Prob[0] = Prob[1] = 0,5 GT: Mersenne-Twister based generators Weighted generators with one weight set Prob[0] Prob[1] Weighted generators with several weight sets
Weighting schemes Stimuli generators GOAL: We want a generator that has a high probability of creating Good BASIS patterns Good : A BASIS pattern that detects many faults Bad : A BASIS pattern that detects few faults
Stimuli generators Weighting schemes (GA3, GT3) Unweighted generator Source for good and bad BASIS pattern Fault Simulation Count detected faults for each basis pattern v1 v2 v3 v4 v5 v6 v7 v8 detected 0 detected 99 detected 50 detected 7 detected 2 detected 64 detected 100 detected 11
Stimuli generators Unweighted Unweighted generator Source for good and bad BASIS pattern Fault Simulation Count detected faults for each basis pattern v1 v2 v3 v4 v5 v6 v7 v8 detected 0 detected 99 detected 50 detected 7 detected 2 detected 64 detected 100 detected 11
Stimuli generators Weighting schemes (GA3, GT3) What can this information be used for? v1 v2 v3 v4 0 1 1 0 detected 0 *detected 99 *detected 50 detected 7 Check each pin value. Good patterns when this pin is 1.. v5 0 detected 2 v6 1 *detected 64 v7 1 *detected 100 v8 0 detected 11
Weighting schemes I (GA3, GT3) Stimuli generators Basis Pattern S1 S0Ctr S1Ctr 9 3 + Detected new faults for the current Basis Pattern 3 CUT S1 S0Ctr S1Ctr 0 12 + Total number of detected paths for particular input values and inputs Probabilities (weights): p 1 = S1Ctr / (S1Ctr + S0Ctr) p 0 = S0Ctr / (S1Ctr + S0Ctr)
Stimuli generators Weighting schemes I I (GA6, GT6) PDFAtpg extracted 20 000 longest testable paths. Test vector set used for computing weights. I0 I1 I2 I3 I0 I1 I2 I3 T1 T2 T3 T4 P0 S1 S1 S1 S1 S1 P1 S1 S0 S1 P1 XX S1 P0 S1 XX CUT n0 n1 p1 2 1 2 2 3 4 4 4 3/5 4/5 4/6 4/6 Counting rules: S0 increments n0 S1 increments n1 P0, P1 and XX increments both Probability (Weights): p1 = n1/(n1 + n0) p0 = n0/(n1 + n0)
Experiments Experiments EX1: Find the K-longest testable paths in each circuit. EX3/EX4: Comparison of different weighting schemes EX5: Weighted pseudo-random patterns targeting the K-longest testable path-delay faults EX6: Distributed simulation utilizing idle CPU time on 100 machines.
Three phases in each experiment Experiments ATPG Phase: ATPG is used in order to find the 20 000 longest testable paths. Paths used as target fault list during simulation Weight generation phase: Weights are generated Fault simulation phase: 10M single-input-change test patterns were applied
Two questions Experiments We want to use the low complexity accumulator, but is it good enough? Can test time be reduced by using weighted compared to unweighted stimuli?
Ex5 Weighted pseudo-random patterns targeting the 20 000 longest testable path-delay faults Experiments GA: accumulator based. GT: mersenne twister based On average, no significant difference.
Two questions Experiments We want to use the low complexity accumulator, but is it good enough? Accumulator: - Low complexity - Poorer statistical properties YES, Accumulator is good enough (for the tested circuits) Mersenne Twister: - High complexity - Good statistical properties
Target Coverage 86% (%) Fault Coverage 100 90 80 70 60 50 40 30 20 10 0 Experiments Ex5 Weighted and unweighted pseudo-random patterns targeting the 20 000 longest testable path-delay faults c880 0,0E+00 2,5E+06 5,0E+06 7,5E+06 1,0E+07 Applied test vectors GA3 GAU
Ex5 Experiments Target Coverage 86% Fault Coverage 100 90 80 70 60 50 40 30 20 10 0 840K c880 0,0E+00 2,5E+06 5,0E+06 7,5E+06 1,0E+07 Applied test vectors GA3 GAU 10M Reduction in test time: 10000000 840 = 11.9 (Really test volume)
Ex5 Weighted pseudo-random patterns targeting the 20 000 longest testable path-delay faults Experiments
Tools in the Workshop? Questionnaire to IC/ASIC companies in Norway In general, delay testing is in near sight or in the distance, but.. Some are using vendor tools: Tetramax/Primetime Synopsys Encounter Test Architect - Cadence
System example: Synopsys: ATPG for transition delay faults, and path delay faults
Questionnaire I asked 8 companies in Norway on state-of-practice in delay testing (5 answered)
Company Relevant technology (nm) Transition delay testing (tool) PDF testing (tool) Comments on delay fault testing A down to 65 NO NO Delivers only virtual components. Synhesizable. ATPG to verify testability. B 180 and 130 YES, in 130 (SynopsysTetramax) YES, in 130 (Tetramax) Will try to include it in every project in 130 and below. C (1) 180 NO NO Will be used in future when converting to smaller techn. C (2) 130 provision for (Tetramax) NO DFT onboard to support delay testing. Test data analysis will be used to increase/decrease delay test patterns later. D 180 NO NO Not a part of standard back-end flow from our back-end partner in this project. E 180 YES (Cadence Encounter True Test) TBD Have not taped-out our first product yet, so consider all answers as will introduce.
Company Relevant technology (nm) Transition delay testing (tool) PDF testing (tool) Comments on delay fault testing A down to 65 NO NO Delivers only virtual components. Synhesizable. ATPG to verify testability. B 180 and 130 YES, in 130 (SynopsysTetramax) YES, in 130 (Tetramax) Will try to include it in every project in 130 and below. C (1) 180 NO NO Will be used in future when converting to smaller technologies. C (2) 130 provision for (Tetramax) NO DFT onboard to support delay testing. Test data analysis will be used to increase/decrease delay test patterns later. D 180 NO NO Not a part of standard back-end flow from our back-end partner in this project. E 180 YES (Cadence Encounter True Test) TBD Have not taped-out our first product yet, so consider all answers as will introduce.
Conclusion Delay testing methodologies are on the way from the ivory towers of research, and into the workshops doing production testing. 130 nanometer technology may be turning point where delay defects can not be ignored for high quality testing. Tools exist, but will have to improve Test data volume is increasing. Need to deal with that (BIST, compressors, )
Some relevant references [Gj 06] Øystein Gjermundnes, Exploiting Arithmetic BIST for Path Delay Fault Testing, PhD thesis, ISBN 82-471-8256-4 (electronic version), NTNU 2006. Thanks to Øystein for use of some of his material. [KC98] A. Krstic and K. T. Cheng, Delay Fault Testing for VLSI Circuits, Kluwer Ac. Publ., Boston 1998. ISBN 0-7923-8295-1. Comprehensive textbook on delay testing [SLC75] H. D. Schnurmann, E. Lindbloom, R. G. Carpenter, "The Weighted Random Test-Pattern Generator," IEEE Transactions on Computers, vol.c-24, no.7pp. 695-700, July 1975. [GRT96] S. Gupta, J. Rajski, and J. Tyszer. Arithmetic additive generators of pseudo-exhaustive test patterns. IEEE Transactions on Computers, 45(8):939 949, 1996. [Smi85] G. L. Smith. Model for delay faults based upon paths. In Proc. of the International Test Conf., pages 342 349, 1985. [Kap95] B. Kapoor. An efficient method for computing exact path delay fault coverage. In Proc. of the European Design and Test Conf., pages 516 520, 1995. [WW03] W. Qiu and D. M. H. Walker. An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit. In Proc. of the International Test Conf., volume 1, pages 592 601, 2003. [CC93] K. T. Cheng and H. C. Chen. Delay testing for non-robust untestable circuits. In Proc. of the International Test Conf., pages 954 961, 1993. [FS83] H. Fujiwara and T. Shimono. On the acceleration of test generation algorithms. IEEE Transactions on Computers, C- 32(12):1137 1144, 1983.
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