ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1
NMOS Transistor 2
ρ Source channel charge density MOS Regions of Operation inversion layer y Electric field Drain Resistive Region V GT > 0, V small DS ρ channel charge density y Electric field Nonlinear Region Source L Drain V > 0, V = V GT DS GT ρ channel charge density y Saturation Region Source depletion region L- d d Drain V > 0, V V GT DS GT 3
Capacitance Gate Capacitance C G determines the amount of charge to switch gate Several distributed components Large discontinuity as device turns on At saturation capacitance is entirely between gate and source 2 1 X Cgs = Cgso + WLCox 1 3 2 X 2 2 1 Cgd = Cgdo + WLCox 1 3 2 X 2 4
Gate Capacitance n+ source gate p- C GDO n+ drain n+ source V < 0 V > 0, V small GT GT gate p- DS C GDO n+ drain gate C GDO n+ source n+ drain V GT > p- 0, V large DS 5
MOS Regions of Operation Resistive Region For small VDS, FET is a linear resistor Nonlinear Region Charge distribution nonuniform across channel Less charge induced in proximity of drain Saturation Region Channel is pinched off Increase in VDS has little effect Square-law behavior (wrt VGT) Acts like a current source 6
MOS Current-Voltage Equations Resistive Region W I = µ C V V L DS n ox GT DS for VDS << V GT I V = β V V 2 DS n GT DS 2 DS for VDS < V GT Saturation Region I DS = V βn 2 2 GT for VDS V GT
Current-Voltage Characteristics Threshold voltage Depends on equilibrium potential Controlled by inversion in channel Body Effect V T varies with bias between source and body Leads to modulation of V T 8
Body Effect Potential on substrate affects threshold voltage V ( V ) = V + γ (2 φ + V ) (2 φ ) 1/2 1/2 T SB T0 F SB F φ F kt B N a = ln q ni Fermi potential of material γ = ( qn ) 1/2 2 a C ox Body bias coefficient 9
NMOS IV Curves 700 NMOS 600 VGS=1.0 VGS=1.5 VGS=2.0 VGS=2.5 500 400 IDS 300 200 100 0 0 0.5 1 1.5 2 2.5 Vds 10
nmos Devices Enhancement Mode Normally off & requires positive potential on gate Good at passing low voltages Cannot pass full V DD (pinch off) Depletion Mode Normally on (negative threshold voltage) Channel is implanted with positive ions ( V T ) Provides inverter with full output swings 11
N a N d V Tn V Tp λ γ Saturation velocity 1.7 10 5 m/s µ n Electron mobility 400 cm2 /Vs µ p Hole mobility 100 cm2 /Vs V sat V1/2 k n k p C ox C GSO,C GDO C J C JSW R poly R diff Density of acceptor ions in NFET channel 1.0 10 17 Density of donor ions in PFET channel 2.5 10 17 NFET threshold voltage 0.5 V PFET threshold voltage -0.5 V Channel modulation parameter 0.1 Body effect parameter MOS SPICE Parameters Symbol Description Value Units L drawn Device length (drawn) 0.35 µm L eff Device length (effective) 0.25 µm t ox Gate oxide thickness 70 A NFET process transconductance 200 µa/v2 PFET process transconductance 50 µa/v2 Gate oxide capacitance per unit area 5 ff/µm2 Gate source and drain overlap capacitance 0.1 ff/µm Junction capacitance 0.5 ff/µm2 Junction sidewall capacitance 0.2 ff/µm Gate sheet resistance 4 Ω/square Source and drain sheet resistance 4 Ω/square 0.3 cm-3 cm-3 V -1 12
MOS Parasitics Gate R G C GS C GD C GB Source R S Drain C SB C DB Body - Capacitance from gate to other 3 terminals - Diodes to body - Series resistance - Wiring parasitics 13
PMOS IV Curves 0 PMOS -100-200 VGS=-1.0-300 -400-500 -600 VGS=-1.0 VGS=-1.5 VGS=-2.0 VGS=-2.5-700 -2.5-2 -1.5-1 -0.5 0 Vds 14
PMOS Transistor 0 PMOS Field oxide Source Gate Gate oxide Drain -100-200 p+ Channel p+ n+ VGS=-1.0-300 -400 Well p- -500-600 VGS=-1.0 VGS=-1.5 VGS=-2.0 VGS=-2.5-700 -2.5-2 -1.5-1 -0.5 0 Vds - All polarities are reversed from nmos - Hole mobility is lower low transconductance - nmos favored over pmos 15
Complementary MOS GND in V DD out in out n+ p- n+ p- p+ p+ n+ 16
CMOS Advantages Virtually, no DC power consumed No DC path between power and ground Excellent noise margins (V OL =0, V OH =V DD ) Inverter has sharp transfer curve Drawbacks Requires more transistors Process is more complicated pmos size larger to achieve electrical symmetry Latch up 17
Source Coupled Pair V = V1 V2 I = I1 I2 V C V + V 1 2 = 1 2 S I 2 C = = 2 2 2 V 2 2 CT β CT I ( ) 1 = β V + = V + V V + V /4 CT 2 2 V 2 2 I2 = β VCT = β V V /4 CT CT V + V 2 I + I ( ) 2β CT I = V V I 18
Power Dissipation in Static CMOS Gate Switching energy dissipated in 0-1 transition VDD VDD 2 CVDD sw = ( DD C ) = ( DD C ) C = 2 0 0 E V V Idt V V CdV Power dissipation P = E f = CV f 2 sig cy sig DD sig R P In terms of duty factor C P = CV f = CV K f 2 2 DD tog DD D ck R n 19
Bipolar Junction Transistor 20
BJT Operating Principle E B C n b (0) P co n b P eo n bo n b (W) 0 W b I C = qad b n (0) n ( W ) W ' ' b b b b q: electron charge A: Effective area of E-B junction D b : diffusion constant of electrons in base 21
CMOS vs Bipolar Current Collector current inversely proportional to Wb Drain current inversely proportional to L Topology Base width is vertical defined by lithography Channel length is horizontal defined by diffusion Behavior Bipolar current is exponential MOS current obeys square law 22
BJT vs MOS Matching V BEon for bipolar is determined by bandgap V T on MOS is determined by t ox and implant BJTs have superior current drive BJTs switch faster than MOS BJTs dissipate more power BJTs have lower yield BJTs are more costly 23
Gallium Arsenide Transistors Speed High electron mobility Saturation velocity is reached at lower power Substrate Larger bandgap than Si semi insulating SOI, Lower parasitics Optical Properties Direct bandgap LED, lasers Integrate digital and optics on same IC 24
GaAs Limitations Physics Low hole mobility Low thermal conductivity More defects and more fragile Process No oxide more complex process Lower level of integration Cost More expensive Less mature technology 25
RF Front End Technologies Product PA LNA Mixer VCO Filter Switch Technology Today GaAs Si SiGe Si Si Si GaAs Si Si GaAs Technology Future Criterion InP GaAs SiGe PAE, linearity InP GaAs Low power InP GaAs Linearity, 1/f noise InP GaAs MEMS 1/f noise High Q InP GaAs MEMS Isolation, Insertion loss 26
Device Technologies for RF Applications Si Bipolar GaAs MESFET GaAs HBT InP HBT base resistance high - low low transit time high? low low beta-early voltage product low? high high col-subst capacitance high - low low linearity of DC current gain high? low medium turn on voltage 0.8-1.4 0.3 thermal conductivity high? low medium transconductance 50X 1 50X? device matching < 1 mv > 10 mv 1 mv? hysteresis or backgating negligible > 10 mv negligible? device scaling high low medium breakdown voltage < 10 V > 8 V > 10 V low ft (GHz)??? 160 Max resolution (bits) 8 5 8? 27