EFM US Type- 0 W harger History oard Function Title Page EFM & User Interface oard Power Page Rev. escription 00 Prototype version. 0 Initial release version. VUS Voltage Regulator ebug MU ebug Misc. P SHEMTI <Path Name> EFM US Type- 0 W harger P0 esigned: pproved: OM oc No: <age ode> esign reated ate: Monday, pril 0, 0 Title Page ocument number R0 reated ate Monday, pril 0, 0 0 Modified ate Monday, October, 0 of
EFM reakout Pads EFM_P0.[..] US RP_EN US R_EN US R_EN US RP_EN UIF_LE0 US TX UIF_LE US TX G_ G_K R TN_RESET K EFM_P.0 EFM_P. EFM_P. EFM_P. EFM_P. 0U EFM_P.0 EFM_P. EFM_P. EFM_P. EFM_P. 00N 00N U P. P. P. 0 P. P.0 P. P. P. P. P. P. P./ EFMF RST/K VIO P0.0/VREF EP P0./ P0./XTL P0./XTL EFM_P. P0./URT0_TX EFM_P. P0./URT0_RX EFM_P. 0 EFM_P. EFM_P. P0. P0. P.0 EFM_P0. EFM_P0. EFM_P0. EFM_P0. EFM_P0. EFM_P0. EFM_P. P.0 P. P. P. P. P. P. P. 0 EFM_P.0 EFM_P. EFM_P. EFM_P. EFM_P. EFM_P. EFM_P. EFM_P. EFM_P.0 EFM_P. EFM_P. EFM_P. EFM_P. EFM_P. EFM_P. EFM_P.0 EFM_P. EFM_P. EFM_P. EFM_P. EFM_P. EFM_P. EFM_P. EFM_P.0 To reakout Pads US_VUS_SENSE _SENSE REG_S REG_S REG_INT VOM_RX VOM_TX REG_I_SL US RX US RX To reakout Pads EFM_P.[..0] EFM_P.[..0] EFM_P.[..0] EFM_P0.[..] EFM_P.[..0] EFM_P.[..0] EFM_P.[..0] G_K G_ EFM_P0. EFM_P0. EFM_P0. EFM_P0. EFM_P0. EFM_P0. EFM_P.0 EFM_P. EFM_P. R EFM_P. EFM_P. EFM_P. EFM_P. EFM_P. EFM_P.0 EFM_P. EFM_P. EFM_P. EFM_P. EFM_P. EFM_P. EFM_P.0 EFM_P. EFM_P. EFM_P. EFM_P. R US_VUS R R0 0 V 0 J J EFM_P0. EFM_P0. EFM_P0. REG_I_S REG_ENLE Opt. use R-R series resistors to separate _TX/RX from break-out pads in case of signal integrity issues. US TYPE- onnector and Rp Resitors ES Protection iodes LEs Reset utton US_VUS US_VUS US_ R K P US- REEPTLE SHIEL SHIEL SHIEL SHIEL SHIEL SHIEL 0 RX+ RX- VUS SU - + VUS TX- TX+ TX+ TX- VUS + - SU VUS 0 RX- RX+ R K V0HULP0 US_ US_ US_ SP00-0 US RX US TX US RX US TX UIF_LE0 UIF_LE SHEMTI R0 K LE00 MER R0 K LE0 MER R 0 TN00 PTS0 R K Reset button needed for debug-purposes only. EFM US Type- 0 W harger 00N TN_RESET 0 esigned: pproved: OM oc No: <age ode> esign reated ate: Monday, pril 0, 0 EFM & User Interface ocument number R0 reated ate Wednesday, pril, 0 0 Modified ate Monday, October, 0 of
Input Voltage VUS Voltage Regulator US Type- VUS R K 00 00U 0 0U 0 0U 0 0U R00 00 Q00 NTTFSN R0 R R Q0 NTTFSN R L00 U R Q0 NTTFS0N R 0 Q0 NTTFSN R0 R R0 00 0 0U 0 0U 0 0U 0 0U 0 00U R K L0 FMJHS0NT US_VUS _SENSE US_VUS_SENSE R Voltage division: 0K _SENSE = 0.0 * R 0K Voltage division: US_VUS_SENSE = 0.0 * US_VUS U00 VRV LSG P LSG P VRV R0 0N R0 00 NSR00H N R0 0K 0 00N 0P VSW ST HSG SN SP OMP IN VSW ST HSG SP 0 SN F OUT 0 00N 0 NSR00H V R0 0N R0 R 0K R0 0K R 0K REG_ENLE REG_INT REG_I_SL REG_I_S R K R0 K R K V EN INT 0 SL S NP V 0 VRV FET LIN S PRV S THP U N R K U R R0 R REG_S VRV N SHEMTI R R K REG_S EFM US Type- 0 W harger esigned: pproved: OM oc No: <age ode> esign reated ate: Monday, pril 0, 0 VUS Voltage Regulator ocument number R0 0 reated ate Modified ate Tuesday, June, 0 Monday, October, 0 of
Input Voltage onnectors Regulator IN+ L0 IN- M M J U U LMSN00SNL U V0HULP0 V G_VUS 0 0 00 U 0 and 0 are used for selecting board power from the debug US cable or from the V output from the NP. These are both part of debugger circuit, and not needed in a final design. 0 00N R00 0K U00 IN SHN P LPIL-J OUT OUT SET FULT 0 R0 0K R0 0K 0 0U N PJ-00H SHEMTI EFM US Type- 0 W harger esigned: pproved: OM oc No: <age ode> esign reated ate: Monday, pril 0, 0 oard Power ocument number R0 reated ate Wednesday, ecember 0, 0 0 Modified ate Monday, October, 0 of
GMU_RESET ebug MU Power & ecoupling L0 IM0U G_VUS G_V 0 00N 0 U 0 U 0 0N 0 U00 EFMGG0F0 RESETn US_VUS EOUPLE 0 US_VREGI US_VREGO _REG _0 _ IO_0 IO_ IO_ VSS_P 0 U 0 00N 0 00N 0 U ebug MU onnections G_ G_K G_RESET G_PGOO R0 K0 LE00 LUE GMU_LE 00 0P X00 MHz WKEUP 0 0P U00 EFMGG0F0 P0 / GPIO_EMWU0 / I0_S #0/ LEU0_RX #/ PRS_H0 / TIM0_0 #0,, P / MU_LK #0/ I0_SL #0/ PRS_H / TIM0_ #0, P / MU_LK0 #0/ ETM_T0 #/ TIM0_ #0, P / ETM_T #/ LES_LTEX / TIM0_TI0 #0 P / ETM_T #/ LES_LTEX / TIM0_TI #0 P / ETM_T #/ LES_LTEX / LEU_TX #/ TIM0_TI #0 P / ETM_TLK #/ GPIO_EMWU / LEU_RX # P / TIM_0 #0 P / TIM_ #0 P0 / TIM_ #0 P / TIM_ P / LFXTL_P / TIM_0 #/ US0_TX #/ US_LK #0 P / LFXTL_N / TIM_ #/ US0_RX #/ US_S #0 P / 0_OUT0/OPMP_OUT0 / I_S #/ LETIM0_OUT0 #/ TIM_ # P / 0_OUT/OPMP_OUT / I_SL #/ LETIM0_OUT # P / HFXTL_P / LEU0_TX #/ US0_LK #, P / HFXTL_N / LEU0_RX #/ US0_S #, U00 EFMGG0F0 SPI Flash GMU_SPI_MOSI GMU_SPI_SLK GMU_SPI_S G_V R0 0K G_V U0 E SI / SIO0 SO / SIO SLK S# E WP# / SIO RESET# / SIO MXR0F G_V U0 V 00N MXR0F GMU_SPI_MISO VOM_RX VOM_TX OR_I_S OR_I_SL OR_I_WP GMU_US_SENSE GMU_TEST_MOE USRT_TX USRT_RX I0_S I0_SL R0 K 0 0 P0 / MP0_H0 / 0_OUT0LT/OPMP_OUT0LT #0/ I0_S #/ LES_H0 / PNT0_S0IN #/ PRS_H #0/ TIM0_ #/ US0_TX #/ US_TX #0 P / MP0_H / 0_OUT0LT/OPMP_OUT0LT #/ I0_SL #/ LES_H / PNT0_SIN #/ PRS_H #0/ TIM0_ #/ US0_RX #/ US_RX #0 P / MP0_H / 0_OUT0LT/OPMP_OUT0LT #/ LES_H / TIM0_TI0 #/ US_TX P / MP0_H / 0_OUT0LT/OPMP_OUT0LT #/ LES_H / TIM0_TI #/ US_RX P / MP0_H / 0_P0/OPMP_P0 / I_S #0/ LES_H / LETIM0_OUT0 #/ PNT_S0IN / TIM0_TI #/ US_LK P / MP0_H / 0_N0/OPMP_N0 / I_SL #0/ LES_H / LETIM0_OUT #/ PNT_SIN / US_S P / MP0_H / ETM_TLK #/ I0_S #/ LES_H / LEU_TX #0 P / MP0_H / ETM_T0 #/ I0_SL #/ LES_H / LEU_RX #0 P / MP_H0 / LES_H / TIM_0 #/ US0_S # P / MP_H / GPIO_EMWU / LES_H / TIM_ #/ US0_LK # P0 / MP_H / LES_H0 / TIM_ #/ US0_RX # P / MP_H / LES_H / US0_TX # P0 / 0_H0 / 0_OUT0LT/OPMP_OUT0LT #/ 0_OUT/OPMP_OUT #/ PNT_S0IN #0/ US_TX # P / 0_H / 0_OUTLT/OPMP_OUTLT #/ G_SWO #/ PNT_SIN #0/ TIM0_0 #/ US_RX # P / 0_H / G_SWO #/ TIM0_ #/ US_LK #/ US_MPU P / 0_H / 0_N/OPMP_N / ETM_T #0,/ TIM0_ #/ US_S # P / 0_H / 0_P/OPMP_P / ETM_T #0,/ LEU0_TX #0 P / 0_H / 0_OUT/OPMP_OUT #0/ ETM_T #0,/ LEU0_RX #0 P / MP0_O #/ 0_H / 0_P/OPMP_P / ETM_T0 #0/ I0_S #/ LES_LTEX0 / LETIM0_OUT0 #0/ PNT0_S0IN #/ TIM_0 #/ US_RX # P / MP_O #/ 0_H / MU_LK0 #/ 0_N/OPMP_N / ETM_TLK #0/ I0_SL #/ LES_LTEX / LETIM0_OUT #0/ PNT0_SIN #/ TIM_ #/ US_TX # P / U_ / MU_LK # U00 EFMGG0F0 Note: The SPI flash is only available to the debug mcu when the US cable is plugged in! GMU_SPI_MOSI GMU_SPI_MISO GMU_SPI_SLK GMU_SPI_S GMU_TX GMU_RX USRT0_TX USRT0_RX USRT0_LK USRT0_S LEURT0_TX LEURT0_RX 0 PE / PNT_S0IN #/ PRS_H # PE / PNT_SIN # PE0 / OOTLOER_TX / TIM_0 #/ US0_TX #0 PE / OOTLOER_RX / LES_LTEX / TIM_ #/ US0_RX #0 PE / MU_LK #/ I0_S #/ LES_LTEX / TIM_ #/ US0_LK #0/ US0_RX # PE / MP0_O #0/ GPIO_EMWU / I0_SL #/ LES_LTEX / US0_S #0/ US0_TX # PE / LEU0_TX #/ TIM_0 PE / LEU0_RX #/ TIM_ GMU_SWLK GMU_SWIO GMU_SWO GMU_US_M GMU_US_P R00 R0 R R 0 PF0 / G_SWLK #0,,,/ I0_S #/ LETIM0_OUT0 #/ LEU0_TX #/ TIM0_0 #/ US_LK # PF / G_SWIO #0,,,/ GPIO_EMWU / I0_SL #/ LETIM0_OUT #/ LEU0_RX #/ TIM0_ #/ US_S # PF / MP_O #0/ G_SWO #0/ GPIO_EMWU / LEU0_TX #/ TIM0_ # PF / PRS_H #/ TIM0_TI #,/ US_VUSEN PF0 / US_M PF / US_P PF / US_I OR_I_S OR_I_SL oard I EEPROM G_V R0 K R0 K G_V U0 G_V U0 S SL R0 V 0K 0 0 VSS OR_I_WP 00N WP 0 0 ebug MU SW Header GMU_RESET GMU_TX GMU_SWIO P0 0 T00-NL TP00 ootloader Halt pin SHEMTI GMU_RX GMU_SWO esigned: pproved: GMU_SWLK OM oc No: <age ode> esign reated ate: Monday, pril 0, 0 EFM US Type- 0 W harger ebug MU ocument number R0 0 reated ate Modified ate Tuesday, October 0, 0 Monday, October, 0 of
ebug US onnector ebug US able etect Test Points 0 P00 US MIRO- L00 LMGSN G_VUS TPJ TPJ TPJ TPJ TPJ TPJ GMU_SWIO GMU_SWLK GMU_SWO GMU_TX GMU_RX TPJ TPJ TPJ TPJ OR_I_SL OR_I_S OR_I_WP GMU_RESET TPJ0 TPJ0 TPJ G_VUS 00 SP00-0 GMU_US_M GMU_US_P R0 K R0 K GMU_US_SENSE R0 0K R 00K + NX00 - U0 R 0K R 00K G_PGOO U0 n.c. V VEE NX00 00N TPJ TPJ TPJ TPJ TPJ TPJ GMU_TEST_MOE TPJ SHEMTI EFM US Type- 0 W harger esigned: pproved: OM oc No: <age ode> esign reated ate: Monday, pril 0, 0 ebug Misc. ocument number R0 reated ate Thursday, ecember 0, 0 0 Modified ate Monday, October, 0 of