RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero credit. Please submit on time. NO late submission will be accepted. Please prepare your submission in English only. No Chinese submission will be accepted. 1. [14pts] Figure 1a shows a standard CMOS inverter. However, during the process of manufacturing, the circuit was contaminated with a particle and the gate of the PMOS transistor got shorted to GND instead of being connected to the input. The contaminated inverter circuit could be modeled as shown in Figure 1b. Figure 1 a. Find V OH, V OL, and V M for the inverters in Figure 1a and 1b. [8pts] b. For a given NMOS, if we want V M=0.5 V, how do you choose the PMOS size? Using following parameters for hand calculations: [6pts] VDD = 1.0 V, V DSAT = 0.3 V for NMOS, and V DSAT = -0.4 V for PMOS NMOS: V T = 0.17V, k n = 130μA/V 2, λ= 0.75 V -1 PMOS: V T = -0.2V, k p = -100μA/V 2, λ= -0.62 V -1
2. [10pts] Consider the circuit in Figure 2. Calculate the total equivalent capacitance on node X as it charges from 0 to VDD/2. Figure 2 You may use the following capacitance values in your calculations: C db_nmos = 0.06 ff, C db_pmos = 0.10 ff, C gb_nmos = 0.14 ff, C gd_pmos = 0.26 ff, C g1 = 0.16 ff, C g2 = 0.30 ff,
3. [6pts] Figure 3 shows the logic diagram of an And-Or-Invert gate. Estimate the activity factor, α 0->1, for the output F, if p(a=1)=1/2, p(b=1)=1/4, and p(c=1)=1/3. (Hint: you need to first find p(f=1) and p(f=0)) Figure 3
4. [8pts] Design in static CMOS using the least number of devices F =AC+BC+AB.
5. [22pts] For the circuit in Figure 4, you can ignore body effect and channel length modulation. Equivalent resistance R eq (W/L=1) of NMOS and PMOS transistors are R n=10 kω and R p = 25 kω, respectively. Figure 4 Logic Gate Delay. a. What function is implemented by this circuit? [4pts] b. Calculate the worst case low-to-high propagation delay. Assume that all output capacitances are lumped together into a single load capacitance C L = 45 ff. (You may ignore all intermediate/internal capacitances for this part.) [6pts] c. Calculate the fastest case high-to-low propagation delay with C L = 45 ff. [6pts] (You may ignore all intermediate/internal capacitances for this part.) d. What are the input patterns that give the worst case t phl and t plh. State clearly what the initial input patterns are and which input(s) has to make a transition in order to achieve this maximum propagation delay. [6pts] (Consider the effect of the capacitances at the internal nodes for this part.)
6. [18pts] Consider the circuit in figure 5: a. What is the logic function implemented by the CMOS transistor network? Size the NMOS and PMOS devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 4 and PMOS W/L = 8. [6pts] b. What are the input patterns that give the worst case t phl and t plh. State clearly what the initial input patterns are and which input(s) has to make a transition in order to achieve this maximum propagation delay. Consider the effect of the capacitances at the internal nodes. [6pts] c. If P(A=1)=0.5, P(B=1)=0.2, P(C=1)=0.3 and P(D=1)=1, determine the power dissipation in the logic gate. Assume VDD=2.5V, C out=30ff and f clk=250mhz. [6pts] Figure 5.
7. [15pts] Consider the circuit in Figure 6: a. Do the following two circuits implement the same logic function? If yes, what is that logic function? If no, give Boolean expressions for both circuits. [6pts] b. Will these two circuits output resistances always be equal to each other? [3pts] c. Will these two circuits rise and fall times always be equal to each other? Why or why not? [6pts] Figure 6
8. [26pts] Consider the circuit in Figure 7. Assume the inverter switches ideally at VDD/2, neglect body effect, channel length modulation and all parasitic capacitance throughout this problem. a. What is the logic function performed by this circuit? [4pts] b. Explain why this circuit has non-zero static dissipation. [4pts] c. Using only just 1 transistor, design a fix so that there will not be any static power dissipation. Explain how you chose the size of the transistor. [6pts] d. Implement the same circuit using transmission gates. [6pts] e. Replace the pass-transistor network in figure with a pass transistor network that computes the following function: x = ABC at the node x. Assume you have the true and complementary versions of the three inputs A, B and C. [6pts] Figure 7
9. [16pts] Consider the circuit in Figure 8. a. Give the logic function of x and y in terms of A, B, and C. Sketch the waveforms at x and y for the given inputs. Do x and y evaluate to the values you expected from their logic functions? Explain. [8pts] b. Redesign the gates using np-cmos to eliminate any race conditions. Sketch the waveforms at x and y for your new circuit. [8pts] Figure 8
10. [20pts] Consider a conventional 4-stage Domino logic circuit as shown in Figure 9 in which all precharge and evaluate devices are clocked using a common clock φ. Keepers are omitted for simplicity. For this entire problem, assume that the pull down network is simply a single NMOS device, so that each Domino stage consists of a dynamic inverter followed by astatic inverter. Assume that the precharge time, evaluate time, and propagation delay of the static inverter are all T/2. Assume that the transitions are ideal (zero rise/fall times). Figure 9 a. Complete the timing diagram for signals Out1, Out2, Out3 and Out4, when the IN signal goes high before the rising edge of the clock φ. Assume that the clock period is 10 T time units. [8pts] b. Suppose that there are no evaluate switches at the 3 latter stages. Assume that the clock φ is initially in the precharge state (φ=0 with all nodes settled to the correct precharge states), and the block enters the evaluate period (φ=1). Is there a problem during the evaluate period, or is there a benefit? Explain. [6pts] c. Assume that the clock φ is initially in the evaluate state (φ=1), and the block enters the precharge state (φ = 0). Is there a problem, or is there any benefit, if the last three evaluate switches are removed? Explain. [6pts]
11. [12pts] Consider the circuit in Figure 10. a. Give the logic function of x and y in terms of A, B, C, and D. Sketch the waveforms at x and y for the given inputs A=1, B=0, C=1, D=1. Do x and y evaluate to the values you expected from their logic functions? Explain (you may want to double-check your answer using a quick HSPICE simulation). [6pts] b. Redesign the gates using np-cmos. Sketch the waveforms at x and y for your new circuit. [6pts] Figure 10