ECEN474/704: (Analog) VLSI Circuit Design Spring 2016

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1 EEN7/70: (nal) VS icuit Desin Spin 06 ectue 0: Siple OT Sa Pale nal & Mixed-Sinal ente Texas &M Uniesity

2 nnunceents H is due tday H is due Ma 0 Exa is n p 9:0-0:5PM (0 exta inutes) lsed bk w/ ne standad nte sheet 8.5 x fnt & back Bin yu calculat es ateial thuh lectue Peius yeas exa s ae psted n the website f efeence

3 enda & efeences Siple OT Paaetes OT w/ ascde ad & Tail uent Suce efeences azai haptes, 6, Seda/Sith Sectin 8.5.

4 Opps and OTs Opp OT Hih ltae ain Hih input ipedance Vltae suce utput (lw ipedance) Hih ltae ain Hih input ipedance uent suce utput (hih ipedance)

5 Opeatinal Tanscnductance plifie bias V DD M 5 M 6 V i+ M M V i- M M V V ptant Paaetes Diffeential Gain Gain-Bandwidth Pduct n-mde nput ane n-mde Gain n-mde ejectin ati (M) Pwe-Supply ejectin ati (PS) Slew ate 5

6 OT Diffeential Gain V DD bias M 5 M 6 V i+ M M V i- M M V id et V ut i By desin id and V 5 ut i and id id 6 5 ut 6 id V DM id ut 6 6

7 TMU-EEN Fequency espnse Jse Sila-Matinez nside nde V X V x V X 0.5 d X X i d i ut i d i d d M B M d X Manitude X sp X dbp V X 0 0.5X S 0P X / p X V d / p ille factdp dbn dn / X X -7-

8 TMU-EEN Jse Sila-Matinez w Fequency espnse M P M P V x p x O ON OP V V X i d i ut 0.5 d / p X O i d i d -0.5 d d M B M 0 Vut d d x d p d x p -8-

9 TMU-EEN Jse Sila-Matinez Fequency espnse M P M P V x p x O ON OP V V X i d i ut 0.5 d / p X O i d i d -0.5 d d M B M 0 Vut d / 0 0 V V d s d s p p d s s s x d p s s x p x p s x p -9-

10 OT Gain-Bandwidth Pduct (GB) DM 6 The cicuit will hae ples p at the utput nde and p at the "i" nde p 6, p 5 M ssuin the ples ae widely spaced and 6 GB DMdB DM p 6 p dinates 0

11 OT n-mde nput ane n-de input ane set by tansist satuatin cnditins V w-end set by cuent suce satuatin ic V V DST Hih-end set by diffeential pai satuatin V ic V V c V V V V V V GS T DD GS 5 T DD Tp5 Tn n x n x p V x Tn 5 V V ic V V DD V p x n 5 x V Tp5 n V x Tn V Tn

12 OT n-mde Gain [Seda] deally, cn-de petubatins ae suppessed by the diffeential aplifie, i.e. c = 0 Finite cn-de ain exists due t aplifie asyeties and finite cuent suce ipedance Nte tansist nubes ae diffeent f peius slides, as bw fiues f Seda/Sith text

13 OT n-mde Gain [Seda] Mdelin the input tansists as a tanscnductance cuent suce with a paallel utput esistance s ic ic G c i i ic ic

14 OT n-mde Gain [Seda] ic c i G ic c ic c G i G

15 OT n-mde Gain 5 K at Since >> and >> and = [Seda] ic c G i 0 ic ic c i G M ic M

16 OT n-mde Gain & ejectin atin (M) c M 6 T ipe (lwe) cn-de ain, we need a hih cuent ipedance n aplifie fiue-f-eit is the cn-de ejectin ati (M) M 0l0 d c M d 0l0 0l0 6 c 6 6

17 OT Pwe-Supply ejectin atin (PS) 7 d 0 DD d 0 l 0 PS l 0 PS dd d PS [azai]

18 OT Slew ate [azai] 8

19 OT Slew ate [azai] Slew ate 9

20 Siple OT Suay bias V DD M 5 M 6 V i+ M M V i- M M V 8 Output Nise uent in kt 8 nput Nise Vltae in kt V T Output nductance Tanscnductance D Gain 6 GB G G ut G ut Dinant Ple Nn - Dinant Ple 6 Slew ate S p p 6 KPn 6 6 KP M T n 6 KP n n T s6 T n p 0 p

21 OT w/ ascde ad and Tail uent Suce p nput n - Mde ane M whee n - Mde Gain Slew ate Dinant Ple D Gain Tn Tp x p DD ic Tn x n x n x n M M DM V V V V V V S GB M M V i+ V i- V DD V bias M 7 M 8 M 9 M 0 M M M 5 M 6 V BN V BP

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