PRECISION OPERATIONAL AMPLIFIERS

Size: px
Start display at page:

Download "PRECISION OPERATIONAL AMPLIFIERS"

Transcription

1 The is a precision, low drift operational amplifier providing the best features of existing T and ipolar op amps. Implementation of super gain transistors allows reduction of input bias currents by an order of magnitude over earlier devices such as the 308. Offset voltage and drift have also been reduced. lthough bandwidth and slew rate are not as great as T devices, input offset voltage, drift and bias current are inherently lower, particularly over temperature. Power consumption is also much lower, eliminating warm up stabilization time in critical applications. Offset balancing is provided, with the range determined by an external low resistance potentiometer. ompensation is provided internally, but external compensation can be added for improved stability when driving capacitive loads. The precision characteristics of the make this device ideal for applications such as charge integrators, analog memories, electrometers, active filters, light meters and logarithmic amplifiers. ow Input Offset oltage: 00 µ ow Input ias urrent: 7 p ow Input Offset urrent: 0.5 p ow Input Offset oltage rift:.0 µ/ ong Term tability: 0 µ/year igh ommon ode ejection: 30 d PIIO OPTIO PII IOTO TI T 8 IX PTI P 626 epresentative chematic iagram alance ompensation PI OTIO 3.0 p Q9 Q0 7.4 k 7.4 k 7.0 k 7.5 k Q7 Q8 alance Inputs alance Output 4 5 ompensation (Top iew) Q5 Q6 Q7 Q8 Q28.0 k Inputs + Q Q Q2 Q2 Q3 Q4 2.0 k 2.0 k Q3 Q4 6.2 k 80 k Q6 Q25.0 k Q5 30 p 2.0 k Q k.0 k Q20 Q2 Q24 20 k 50 k 362 Q22 Q23.2 k.4 k Q29 Q27 Q3 Q30 Q Output Q33 evice OI IOTIO Operating Temperature ange Package, T = 0 to +70 Plastic IP 2 24 OTOO O I I T

2 , XI TI ating ymbol alue nit Power upply oltage to 40 dc ifferential Input urrent (ote ) II ±0 m Output hort ircuit uration (ote 2) t Indefinite Power issipation (ote 3) P 500 mw Operating unction Temperature T 85 torage Temperature ange Tstg 55 to +25 TI TITI (T = 25, unless otherwise noted [ ote 4 ].) haracteristic ymbol in Typ ax in Typ ax nit Input Offset oltage IO m Tlow to Thigh Input Offset urrent IIO p Tlow to Thigh Input ias urrent II p Tlow to Thigh Input esistance ri 0 0 Ω Input Offset oltage rift IO/ T µ/ Tlow to Thigh Input Offset urrent rift IIO/ T 0 50 ƒ/ Tlow to Thigh Input ias urrent rift II/ T p/ Tlow to Thigh arge ignal oltage ain O /m = ±5, out = ±2, Iout = ±2.0 m Tlow to Thigh (ote 5) 50 5 = ±5, out = ±2, Iout = ±0.5 m Tlow to Thigh ommon ode ejection d = ±5, = ±5, 2.5 4, Tlow to Thigh Power upply ejection P d ±2.5 ± Tlow to Thigh Power upply urrent I m Tlow to Thigh.0.0 Output hort ircuit urrent I ±0 ±0 m T = 50, Output horted to round. The inputs are shunted by back to back diodes for over voltage protection. xcessive current will flow if the input differential voltage is in excess of.0 if no limiting resistance is used. dditionally, a 2.0 kω resistance in each input is suggested to prevent possible latch up initiated by supply reversals. 2. The output is current limited when shorted to ground or any voltages less than the supplies. ontinuous overloads will require package dissipation to be considered and heatsinking should be provided when necessary. 3. evices must be derated based on package thermal resistance (see package outline dimensions). 4. These specifications apply for ( for T low to T high ) and ±2.5 ±20 T low to T high : 0 T +70 for and. 5. out = ±.5, all other conditions unchanged. OTOO O I I T 2 25

3 , igure. Input ias urrent versus ase Temperature igure 2. Input Offset urrent versus ase Temperature I I, IPT I T (p) / = ± / = ± T, TPT ( ) I IO, IPT OT T (p) urve, / = ±20 urve 2, / = ± T, TPT ( ) 2 T IO, TPT OIIT O IPT OT OT ( µ / ) igure 3. Temperature oefficient of Input Offset oltage versus Input Offset oltage / = ±20 t = 25 to IO, IPT OT OT 25 IPT OI ( n/ z ) igure 4. pectral oise ensity / = ±5 = 0 = 00 kω k 0 k 00 k f, QY (z) OO O IIT () igure 5. ommon ode imits versus Temperature Positive ± IO = 0 µ egative , OO O TIO TIO (d) igure 6. ommon ode ejection and lew imit versus requency k 0 k 00 k.0 T, TPT ( ) f, QY (z) / = ±5 IO = 00 µ , OO O W IIT (p-p) 2 26 OTOO O I I T

4 , igure 7. Open oop oltage ain versus upply oltage igure 8. Output aturation versus oad urrent O, OP OOP OT I (d) f 0. z sat =.5 2 (kω) sat, OTPT TTIO OT () T 25 ±2.5 ±5 IO = 0 µ IO = 20 µ (25 ) /, PPY OT (±) I, O T (±m) igure 9. Power upply ejection atio versus requency igure 0. upply urrent versus upply oltage P, POW PPY TIO (d) k 0 k 00 k.0 0 f, QY (z) I, PPY T ( µ ) T = T = T = /, PPY OT (±) O, OT I (d) igure. Open oop oltage ain and Phase versus requency O φ = 0 2. = 000 p 50 0 / = ±5 = 30 kω k 0 k 00 k.0 φ, P (), W T (m/ µ s) igure 2. lew ate versus xternal ompensation apacitor / = 20 k ±20 ± + 20 k k 0 k f, QY (z), XT OPTIO PITO (p) OTOO O I I T 2 27

5 ,.0 k igure 3. losed oop Output Impedance versus requency ZO, OTPT IP ( Ω ) = 000 =.0 / = ±5 Iout = ±.0 m k 0 k 00 k.0 0 f, QY (z) PPITIO IOTIO ue to the extremely low input bias currents of this device, it may be tempting to remove the bias current compensation resistor normally associated with a summing amplifier configuration. irect connection of the inputs to a low impedance source or ground should be avoided when supply voltages greater than approximately 3.0 are used. The potential problem involves reversal of one supply which can cause excessive current to flow in the second supply. Possible destruction of the I could result if the second supply is not current limited to approximately 00 m or if bypass capacitors greater than.0 µ are used in the supply bus. isconnecting one supply will generally cause reversal due to loading of the other supply within the I and in external circuitry. lthough the problem can usually be avoided by placing clamp diodes across the power supplies of each printed circuit board, a careful design will include sufficient resistance in the input leads to limit the current to 0 m if the input leads are pulled to either supply by internal currents. This precaution is not limited only to the. The is capable of resolving picoampere level signals. eakage currents external to the I can severely impair the performance of the device. It is important that high quality insulating materials such as teflon be employed. Proper cleaning to remove fluxes and other residues from printed circuit boards, sockets and the device package are necessary to minimize surface leakage. When operating in high humidity environments or temperatures near 0, a surface coating is suggested to set up a moisture barrier. eakage effects on printed circuit boards can be reduced by encircling the inputs (both sides of pc board) with a conductive guard ring connected to a low impedance potential nearly the same as that of the inputs. uard ring electrical connections for common operational amplifier configurations are illustrated in igure 4. lectrostatic shielding is suggested in high impedance circuits. rror voltages in external circuitry can be generated by thermocouple effects. issimilar metals along with temperature gradients can set up an error voltage ranging in the hundreds of microvolts. ome of the best thermocouples are junctions of dissimilar metals made up of I package pins and printed circuit boards. Problems can be avoided by keeping low level circuitry away from heat generating elements. The is internally compensated, but external compensation can be added to improve stability, particularly when driving capacitive loads. igure 4. uard ing lectrical onnections for ommon mplifier onfigurations Input umming mp (Inverting) 2 oninverting 2 oltage ollower Output Input Output Input Output OTOO O I I T

6 , igure 5. Input Protection for umming (Inverting) mplifier igure 6. Input Protection for a oltage ollower Input 3 0 k 3 0 k Output Input 0 k Output urrent is limited by in the event the input is connected to a low impedance source outside the common mode range of the device. urrent is controlled by 2 if one supply reverses. and 2 do not affect normal operation. Input current is limited by when the input exceeds supply voltage, power supply is turned off, or output is shorted. igure 7. able ootstrapping and Input hields Input Output Input Output n input shield bootstrapped in a voltage follower reduces input capacitance, leakage, and spurious voltages from cable flexing. small capacitor from the input to ground will prevent any instability. In a summing amplifier the input is at virtual ground. Therefore the shield can be grounded. small feedback capacitor will insure stability. igure 8. djusting Input Offset oltage with alance Potentiometer Inputs Output inimum djustment ange (m) ±0.4 ±.0 ±2.0 ±5.0 (Ω).0 k 3.0 k 0 k 00 k Input offset voltage adjustment range is a function of the alance Potentiometer esistance as indicated by the table above. The potentiometer is connected between the two alance pins. OTOO O I I T 2 29

7 Tape and eel Options In rief... otorola offers the convenience of Tape and eel packaging for our growing family of standard integrated circuit products. eels are available to support the requirements of both first and second generation pick and place equipment. The packaging fully conforms to the latest I 48 specification. The antistatic embossed tape provides a secure cavity, sealed with a peel back cover tape. Page Tape and eel onfigurations Tape and eel Information Table nalog PQ Table OTOO O I I T 2

8 Tape and eel onfigurations echanical Polarization OI and icro 8 I Typical P I Typical PI ser irection of eed ser irection of eed P and 2P I Typical ser irection of eed OT 23 (5 Pin) I Typical OT 89 (3 Pin) I Typical OT 89 (5 Pin) I Typical ser irection of eed ser irection of eed ser irection of eed 2 2 OTOO O I I T

9 Tape and eel onfigurations (continued) TY (Preferred) TO 92 eel tyles TY arrier trip dhesive Tape ounded ide arrier trip dhesive Tape lat ide ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ eed eed ounded side of transistor and adhesive tape visible. lat side of transistor and adhesive tape visible. TY P (Preferred) dhesive Tape On Top ide TO 92 mmo Pack tyles TY dhesive Tape On Top ide ounded ide É ÉÉ É eed arrier trip lat ide É eed ÉÉ É arrier trip abel ounded side of transistor and adhesive tape visible. abel lat side of transistor and adhesive tape visible. tyle P ammo pack is equivalent to tyles and of reel pack dependent on feed orientation from box. tyle ammo pack is equivalent to tyle of reel pack dependent on feed orientation from box. TO 92 I adial Tape in an old ox or On eel W2 4 5 W W T T 2 T2 P2 P2 P P OTOO O I I T 2 3

10 Tape and eel Information Table Package Tape Width evices() eel ize evice (mm) per eel (inch) uffix O 8, OP 8 2 2, O 4 6 2, O 6 6 2, O 6, O 8+8 WI 6, O 20 WI 24, O 24 WI 24, O 28 WI 24, O 28 WI 32, icro 8 2 2, P 20 6, P P P P P TO 226 (TO 92)(2) 8 2,000 3,, P, or (mmo Pack) only P 6 2, P OT 23 (5 Pin) 8 3,000 7 T OT 89 (3/5 Pin) 2,000 7 T () inimum order quantity is reel. istributors/o customers may break lots or reels at their option, however broken reels may not be returned. (2) Integrated circuits in TO 226 packages are available in tyes and only, with optional mmo Pack (uffix P or ). The and P configurations are preferred. or ordering information please contact your local otorola emiconductor ales Office. 2 4 OTOO O I I T

11 nalog PQ Table Tape/eel and mmo Pack P OI icro 8 TO 92 P 2P OT 23 (5 Pin) OT 89 (3 Pin) OT 89 (5 Pin) Package Type Package ode PQ ase /reel ase /reel ase /reel ase /reel ase /reel ase /reel ase /reel ase /reel ase /reel ase /reel ase /reel ase /reel ase /mmo Pack ase /reel ase /reel ase /reel ase /reel ase /reel OTOO O I I T 2 5

12 2 6 OTOO O I I T

13 Packaging Information In rief... The packaging availability for each device type is indicated on the individual data sheets and the elector uide. ll of the outline dimensions for the packages are given in this section. The maximum power consumption an integrated circuit can tolerate at a given operating ambient temperature can be found from the equation: T(max) T P(T) = θ(typ) where: P(T) = Power issipation allowable at a given operating ambient temperature. This must be greater than the sum of the products of the supply voltages and supply currents at the worst case operating condition. T(max) = aximum operating unction Temperature as listed in the aximum atings ection. ee individual data sheets for T(max) information. T = aximum desired operating mbient Temperature θ(typ) = Typical Thermal esistance unction-to- mbient OTOO O I I T 3

14 ase Outline imensions P, P, Z IX (TO-226/TO-92) I. IIOI TOI P I Y4.5, OTOI IIO: I. 3. OTO O P YO IIO I OTO. 4. IIO PPI TW P. IIO PPY TW II. IIO I OTO I P YO IIO II. 2 3 TI X X P TIO X X I IIT P , T IX I Y TI T. IIOI TOI P I Y4.5, OTOI IIO: I Y Q P 0.25 (0.00) Y I IIT Q T OTOO O I I T

15 T IX I Q P OPTIO TI. IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO O OT I ITOT () POTIO. IIO II POTIO OT X (.092) XI. 5 5X 0.04 (0.356) T P 5X I IIT Q T, T IX I 5 Q 5X P 0.0 (0.254) T P OPTIO 5X 0.24 (0.60) T W TI. IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO O OT I ITOT () POTIO. IIO II POTIO OT X (.092) XI. I IIT Q W T IX 34 0 I Q TI. IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO O OT I ITOT () POTIO. IIO II POTIO OT X 0.92 (0.043) XI. 5 I IIT Q P (0.04) T Q OTOO O I I T 3 3

16 T, T IX I Q 5 P TI. IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO O OT I ITOT () POTIO. IIO II POTIO OT X 0.92 (0.043) XI. I IIT Q (0.04) T Q T- IX (P) I. IIOI TOI P I Y4.5, OTOI IIO: I TI I IIT P 0.3 (0.005) T T IX (P) I Y P 0.3 (0.005) T TI Z. IIOI TOI P I Y4.5, OTOI IIO: I. I IIT Z OTOO O I I T

17 P,, P, P IX I IIO TO T O W O P. 2. P OTO OPTIO (O O Q O). 3. IIOI TOI P I Y4.5, OT 2 TI 0.3 (0.005) T IIT I , P, -4, P2 IX I WITI 0.3 (0.005) I O T POITIO T TI T XI TI OITIO. 2. IIO TO T O W O P. 3. IIO O OT I O. 4. O O OPTIO. 4 TI I IIT P2,, P, P IX I P 0.25 (0.00) T TI. IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO TO T O W O P. 4. IIO O OT I O. 5. O O OPTIO. I IIT OTOO O I I T 3 5

18 , P, P2, IX (IP 6) I 6 9. IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO TO T O W O P. 4. IIO O OT I O. 5. IT OTIO TW 4 5, TI 8 OT 5 6 P 6 P 0.3 (0.005) T I IIT (0.005) T P IX (IP 6) I O P 3 P 0.25 (0.00) T TI. IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO TO T O W O P. 4. IIO O OT I O POTIO. 5. O O POTIO OT X 0.25 (0.00). 6. O O OPTIO. I IIT P P IX I 24 Q P TI. WITI 0.3 (0.005) I O T POITIO T TI T XI TI OITIO. 2. IIO TO T O W O P. IIT I P Q OTOO O I I T

19 ,,, P IX I POITIO TO O (), WITI 0.25 (0.00) T XI TI OITIO, I TIO TO TI OT. 2. IIO TO T O W O P. 3. IIO O OT I O. 8 TI IIT I P IX I 28. POITIO TO O (), WITI 0.25 (0.00) T XI TI OITIO, I TIO TO TI OT. 2. IIO TO T O W O P. 3. IIO O OT I O IIT I TI P IX 7-03 I POITIO TO O (), WITI 0.25 (0.00) T XI TI OITIO, I TIO TO TI OT. 2. IIO TO T O W O P. 3. IIO O OT I O. 20 TI IIT I OTOO O I I T 3 7

20 , P, P-3 IX (IP 24) I TI P 0.25 (0.00) T 24 P OT 0.25 (0.00) T. OTO OPTIO. 2. IIO TO T O W O P. 3. IIOI TOI P I Y4.5, OTOI IIO: I. I IIT , P, P IX I 20 TI P 0.25 (0.00) T 20 P 0.25 (0.00) T. IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO TO T O W O P. 4. IIO O OT I O. I IIT ,, 2 IX (O-8, OP-8) I IIOI TOI P Y4.5, IIO I IIT. 3. IIO O OT I O POTIO. 4. XI O POTIO 0.5 P I. 5. IIO O OT I O POTIO. OW POTIO 0.27 TOT I X O T IIO T XI TI OITIO. 8 e 0.25 TI 0.0 h X 45 IIT I I X e h OTOO O I I T

21 IX (O-4) I 4 TI P 7 P 7 P 0.25 (0.00) T 0.25 (0.00) X 45. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. IIO O OT I O POTIO. 4. XI O POTIO 0.5 (0.006) P I. 5. IIO O OT I POTIO. OW POTIO 0.27 (0.005) TOT I X O T IIO T XI TI OITIO. IIT I P IX (O-6) I 6 TI P 0.25 (0.00) T P 8 P 0.25 (0.00) X 45. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. IIO O OT I O POTIO. 4. XI O POTIO 0.5 (0.006) P I. 5. IIO O OT I POTIO. OW POTIO 0.27 (0.005) TOT I X O T IIO T XI TI OITIO. IIT I P W, P IX (O-20, O 20) I X (0.25) T 8X 0X P 0.00 (0.25) TI X 45. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. IIO O OT I O POTIO. 4. XI O POTIO 0.50 (0.006) P I. 5. IIO O OT I POTIO. OW POTIO 0.3 (0.005) TOT I X O IIO T XI TI OITIO. IIT I P OTOO O I I T 3 9

22 W IX (O-24, OP (6+4+4)) I 24 TI X 2 24X 0.00 (0.25) T 22X P 0.00 (0.25) X 45. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. IIO O OT I O POTIO. 4. XI O POTIO 0.5 (0.006) P I. 5. IIO O OT I POTIO. OW POTIO 0.3 (0.005) TOT I X O IIO T XI TI OITIO. IIT I P W IX (O-28, OI 28) I X P 0.00 (0.25). IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. IIO O OT I O POTIO. 4. XI O POTIO 0.5 (0.006) P I. 5. IIO O OT I POTIO. OW POTIO 0.3 (0.005) TOT I X O IIO T XI TI OITIO. 28X 0.00 (0.25) T 26X 4 X 45 TI IIT I P W IX (O-6, OP 6, OP-8+8) I X 4X 0.00 (0.25) T 8 8X P TI 0.00 (0.25) X 45. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. IIO O OT I O POTIO. 4. XI O POTIO 0.5 (0.006) P I. 5. IIO O OT I POTIO. OW POTIO 0.3 (0.005) TOT I X O IIO T XI TI OITIO. IIT I P OTOO O I I T

23 IX 75 0 (O 6) I O TI 4 X 0.25 (0.00) T 6 P 0.25 (0.00) X 45 IIOI TOI P I Y4.5, OTOI IIO: IIT. 3 IIO O OT I O POTIO. 4 XI O POTIO 0.5 (0.006) P I. 5 IIO O OT I POTIO. OW POTIO 0.27 (0.005) TOT I X O T IIO T XI TI OITIO. IIT I P W IX 75 0 (OP 6) I O 6 T. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. IIO O OT I O POTIO. 4. XI O POTIO 0.5 (0.006) P I. P 0.00 (0.25) 5. IIO O OT I POTIO. OW POTIO 0.3 (0.005) TOT I 8 X O IIO T XI TI OITIO. 3X 0.00 (0.25) T IIT I X P TI T X OTOO O I I T 3

24 762-0 Plastic edium Power Package (IP-9) I 9 Q TI Y 0.25 (0.00) T 9 W 9 P X 0.25 (0.00) T 0.25 (0.00) T. IIOI TOI P I Y4.5, OTOI IIO: IIT. IIT I Q W X Y IX (P-20) I 20 Y W (0.80) T (0.80) T Z X 0.00 (0.250) T IW. T,, TI W TOP O O XIT PTI OY T O PTI I. 2. IIO, T POITIO TO T T, TI. 3. IIO O OT I O. OW O I 0.00 (0.250) P I. 4. IIOI TOI P I Y4.5, OTOI IIO: I. 6. T P TOP Y T T P OTTO Y P TO 0.02 (0.300). IIO TI T T OTOT XT O T PTI OY XI O O, TI, T IT, T II Y IT TW T TOP OTTO O T PTI OY. 7. IIO O OT I POTIO O ITIO. T POTIO() OT T IIO TO T T (0.940). T ITIO() OT T IIO TO T (0.635). Z (0.80) T (0.80) T (0.00) TI IW 0.00 (0.250) T IW (0.80) T (0.80) T I IIT W X Y Z OTOO O I I T

25 IX (P 28) I Y (0.80) T (0.80) T Z 28 W X IW 0.00 (0.250) T Z (0.80) T (0.80) T (0.80) T IW (0.00) TI (0.80) T 0.00 (0.250) T IW. T,, TI W TOP O O XIT PTI OY T O PTI I. 2. IIO, T POITIO TO T T, TI. 3. IIO O OT I O. OW O I 0.00 (0.250) P I. 4. IIOI TOI P I Y4.5, OTOI IIO: I. 6. T P TOP Y T T P OTTO Y P TO 0.02 (0.300). IIO TI T T OTOT XT O T PTI OY XI O O, TI, T IT, T II Y IT TW T TOP OTTO O T PTI OY. 7. IIO O OT I POTIO O ITIO. T POTIO() OT T IIO TO T T (0.940). T ITIO() OT T IIO TO T (0.635). I IIT W X Y Z OTOO O I I T 3 3

26 IX (P) I Y Z 0.007(0.80) T 0.007(0.80) T X IW 0.00 (0.25) T 44 W 0.007(0.80) T Z 0.00 (0.25) T. T,, TI W TOP O O XIT PTI OY T O PTI I. 2. IIO, T POITIO TO T T, TI. 3. IIO O OT I O. OW O I 0.00 (0.25) P I. 4. IIOI TOI P I Y4.5, OTOI IIO: I (0.80) T 0.007(0.80) T IW (0.0) TI IW 6. T P TOP Y T T P OTTO Y P TO 0.02 (0.300). IIO TI T T OTOT XT O T PTI OY XI O O, TI, T IT, T II Y IT TW T TOP OTTO O T PTI OY. 7. IIO O OT I POTIO O ITIO. T POTIO() OT T IIO TO T T (0.940). T ITIO() OT T IIO TO T (0.635) (0.80) T I IIT W X Y Z IX 803 PIIY 20 0 P (0.005) 0 20 P 0.3 (0.005) T 0.0 (0.004) TI 6 IIOI TOI P I Y4.5, OTOI IIO: IIT. 8 IIO O OT I O POTIO. 9 XI O POTIO 0.5 (0.008) P I. 0 IIO O OT I POTIO. OW POTIO 0.3 (0.006) TOT I X O T IIO T XI TI OITIO. IIT I * 0.488* *PPOXIT 3 4 OTOO O I I T

27 T IX (5-Pin ZIP) I PI 5X Q P PI (0.254) T P Q Y 5X TI (0.60) T. IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO O OT I O O POTIO. 4. IIO O OT I O O POTIO. 5. O O POTIO OT X 0.00 (0.250). 6. IIO O OT I POTIO. OW POTIO (0.076) TOT I X O T IIO. T XI TI OITIO. I IIT Y T IX I P PI 5X 7X 5 Q PI (0.254) T P Y TI 5X (0.60) T. IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO O OT I O O POTIO. 4. IIO O OT I O O POTIO. 5. O O POTIO OT X 0.00 (0.250). 6. T 7. IIO O OT I POTIO. OW POTIO (0.076) TOT I X O T IIO. T XI TI OITIO. I IIT Q Y OTOO O I I T 3 5

28 T IX (TQP 44) I O Z,, Z T T TI (0.008) Z 0.05 (0.002) Z 0.20 (0.008) Z PTI ÇÇÇÇ ÉÉÉÉ TI T (0.008) T Z 0.05 (0.002) T 0.20 (0.008) T Z TIO 0.20 (0.008) T Z W Q X IW Y TI 0.0 (0.004). IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. T I OT T OTTO O I OIIT WIT T W T XIT T PTI OY T T OTTO O T PTI I. 4. T, Z TO TI T T. 5. IIO TO TI T TI. 6. IIO O OT I O POTIO. OW POTIO I 0.25 (0.00) P I. IIO O I O IT TI T T. 7. IIO O OT I POTIO. POTIO OT T IIO TO X (0.02). IIT I Q W X Y OTOO O I I T

29 IX (QP) I (0.008) T,, PI IT 0.20 (0.008) 0.05 (0.002) IW Y 3 P IW Y 0.20 (0.008) 0.05 (0.002) 0.20 (0.008) T PTI ÇÇÇ ÉÉÉ T 0.20 (0.008) T 40X TIO 44 P W Y IW P T 0.0 (0.004). IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. T I OT T OTTO O I OIIT WIT T W T XIT T PTI OY T T OTTO O T PTI I. 4. T, TO TI T T. 5. IIO TO TI T TI. 6. IIO O OT I O POTIO. OW POTIO I 0.25 (0.00) P I. IIO O I O IT TI T T. 7. IIO O OT I POTIO. POTIO OT T IIO TO X (0.02). T IW P 2 2 IIT I W Y OTOO O I I T 3 7

30 IX I O 64 Z ,, Z TI 0.20 (0.008) Z T Z (0.002) 0.20 (0.008) Z T TI P (0.008) (0.002) T 0.20 (0.008) T T Z Z T ÉÉÉ ÇÇ ÉÉÉ ÇÇ ÉÉÉ ÇÇ ÉÉÉ 0.20 (0.008) T Z TIO Y 0.0 (0.004) TI W TI X Q. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. T I OT T OTTO O I OIIT WIT T W T XIT T PTI OY T T OTTO O T PTI I. 4. T, Z TO TI T T. 5. IIO TO TI T TI. 6. IIO O OT I O POTIO. OW POTIO I 0.25 (0.00 ) P I. IIO O I O IT TI T T. 7. IIO O OT I POTIO. POTIO OT T IIO TO X (0.04). IIT I P Q W X Y OTOO O I I T

31 IX (icro 8) I 8. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. IIO O OT I O, POTIO O T. O, POTIO O T OT X 0.5 (0.006) P I. 4. IIO O OT I IT O POTIO. IT O POTIO OT X 0.25 (0.00) P I. PI I TI (0.005) 8 P 0.08 (0.003) T IIT I OTOO O I I T 3 9

32 IX (TQP 52) I TI 0.20 (0.008) 0.05 (0.002) 0.20 (0.008) TI,, (0.008) 0.05 (0.002) 0.20 (0.008) T TI T 0.02 (0.008) TIO 0.0 (0.004) TI T W TI X Q. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. T I OT T OTTO O I OIIT WIT T W T XIT T PTI OY T T OTTO O T PTI I. 4. T, TO TI T T. 5. IIO TO TI T TI. 6. IIO O OT I O POTIO. OW POTIO I 0.25 (0.00) P I. IIO O I O IT TI T T. 7. IIO O OT I POTIO. OW POTIO 0.08 (0.003) TOT I X O T IIO T XI TI OITIO. OT OT O T OW I O T OOT. IIT I Q T W X OTOO O I I T

33 IX I 52 4X 4X TIP 0.20 (0.008) 0.20 (0.008) T X X=,, X IW Y IW Y PTI ÉÉÉ ÉÉÉ ÇÇÇ 0.3 (0.005) T TIO OTT 90 OWI T 4X θ2 0.0 (0.004) T TI 4X θ3 IW (0.002) IW W θ Z θ 2 X 0.25 (0.00). IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. T I OT T OTTO O I OIIT WIT T W T XIT T PTI OY T T OTTO O T PTI I. 4. T, TO TI T T. 5. IIO TO TI T TI. 6. IIO O OT I O POTIO. OW POTIO I 0.25 (0.00) P I. IIO O I O IT TI T T IIO O OT I POTIO. POTIO OT T WIT TO X 0.46 (0.08). II P TW POTIO T O POTIO 0.07 (0.003). IIT I W Z θ θ 0 0 θ2 2 2 θ OTOO O I I T 3 2

34 IX I O IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO TO T O W O P. 4. IIO O OT I O. XI O 0.25 (0.00). TI 2 42 P 0.25 (0.00) T 42 P 0.25 (0.00) T I IIT IX (IP) I O IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO TO T O W O P. 4. IIO O OT I O. XI O 0.25 (0.00) TI P 0.25 (0.00) T 56 P 0.25 (0.00) T I IIT OTOO O I I T

35 , T IX (TQP 32) I TI (0.008) 0.05 (0.002) 0.20 (0.008) P,, TI (0.008) 0.05 (0.002) 0.20 (0.008) T TI 0.20 (0.008) TIO IW OTT 90 OWI TI T 0.0 (0.004) T TI X T Q. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. T I OT T OTTO O I OIIT WIT T W T XIT T PTI OY T T OTTO O T PTI I. 4. T, TO TI T T. 5. IIO TO TI T TI. 6. IIO O OT I O POTIO. OW POTIO I 0.25 (0.00) P I. IIO O I O IT TI T T. 7. IIO O OT I POTIO. OW POTIO 0.08 (0.003) TOT I X O T IIO T XI TI OITIO. OT OT O T OW I O T OOT. IIT I P Q T X OTOO O I I T 3 23

36 T IX (23-Pin ZIP) I 23. IIOI TOI P I Y4.5, OTOI IIO: I. 3. IIO O OT I O O POTIO. 4. IIO O OT I O O POTIO. 5. O O POTIO OT X 0.00 (0.250). 6. IIO O OT I POTIO. OW POTIO (0.076) TOT I X O T IIO T XI TI OITIO. PI P PI 23 23X 0.00 (0.254) T Q Y 23X W TI (0.60) T I IIT P W Y OTOO O I I T

37 T IX (TQP 48) I 48 P 4X (0.008) T Z 9 TI Y ,, Z TI Y 3 24 Z TOP & OTTO 4X (0.008) T Z (0.00) (0.003) TI W X Q T ÇÇÇ ÇÇÇ ÉÉÉ (0.003) T Z TIO. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. T I OT T OTTO O I OIIT WIT T W T XIT T PTI OY T T OTTO O T PTI I. 4. T,, Z TO TI T T. 5. IIO TO TI T TI. 6. IIO O OT I O POTIO. OW POTIO I (0.00) P I. IIO O I O IT TI T T. 7. IIO O OT I POTIO. POTIO OT T IIO TO X (0.04). 8. II O PT TI (0.0003). 9. XT P O O I OPTIO. IIT I I I P I 0.00 I Q W X OTOO O I I T 3 25

38 2T IX I TI 4. IIOI TOI P I Y4.5, OTOI IIO: I. 3. T OTO OPTIO WITI IIO. 4. IIO TI II OTI O TI IIO O OT I O O T POTIO. O T POTIO OT TO X (0.635) XI (0.254) T OPTIO I IIT X 3.75 X P I I I I P 2T IX (2P) I 0.00 (0.254) T OPTIO TI 6. IIOI TOI P I Y4.5, OTOI IIO: I. 3. T OTO OPTIO WITI IIO. 4. IIO TI II OTI O TI IIO O OT I O O T POTIO. O T POTIO OT TO X (0.635) XI. I IIT P I I I I P 3 26 OTOO O I I T

39 T, T IX (TOP 20) I 0.5 (0.006) T 0.5 (0.006) T 2X /2 PI IT 0.00 (0.004) TI X 0.0 (0.004) T ÍÍÍÍ ÍÍÍÍ TIO TI 0.25 (0.00) TI W. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. IIO O OT I O, POTIO O T. O O T OT X 0.5 (0.006) P I. 4. IIO O OT I IT O POTIO. IT O POTIO OT X 0.25 (0.00) P I. 5. IIO O OT I POTIO. OW POTIO 0.08 (0.003) TOT I X O T IIO T XI TI OITIO. 6. TI OW O OY. 7. IIO TO TI T T W. IIT I T IX (TOP 6, TOP 6) I O 0.5 (0.006) T 0.5 (0.006) T PI IT. 2X /2 6X 0.0 (0.004) T ÇÇÇ ÇÇÇ ÉÉÉ TIO 0.25 (0.00) TI. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. IIO O OT I O. POTIO O T. O O T OT X 0.5 (0.006) P I. 4. IIO O OT I IT O POTIO. IT O POTIO OT X 0.25 (0.00) P I. 5. IIO O OT I POTIO. OW POTIO 0.08 (0.003) TOT I X O T IIO T XI TI OITIO. 6. TI OW O OY. 7. IIO TO TI T T W. IIT I (0.004) TI W TI OTOO O I I T 3 27

40 T IX (TOP 4) I O (0.006) T 0.5 (0.006) T 0.0 (0.004) TI 2X /2 PI IT. 4 4X 0.0 (0.004) T (0.00) 7 TI ÇÇÇ ÉÉ TIO TI W IIOI TOI P I Y4.5, OTOI IIO: IIT. 3 IIO O OT I O, POTIO O T. O O T OT X 0.5 (0.006) P I. 4 IIO O OT I IT O POTIO. IT O POTIO OT X 0.25 (0.00) P I. 5 IIO O OT I POTIO. OW POTIO 0.08 (0.003) TOT I X O T IIO T XI TI OITIO. 6 TI OW O OY. 7 IIO TO TI T T W. IIT I OTOO O I I T

41 T IX I O (0.006) T 24X 0.0 (0.004) T 0.5 (0.006) T 2X /2 PI IT IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. IIO O OT I O, POTIO O T. O O T OT X 0.5 (0.006) P I. 4. IIO O OT I IT O POTIO. IT O POTIO OT X 0.25 (0.00) P I. 5. IIO O OT I POTIO. OW POTIO 0.08 (0.003) TOT I X O T IIO T XI TI OITIO. 6. TI OW O OY. 7. IIO TO TI T T W. 0.0 (0.004) TI W IIT I TI ÇÇÇ ÉÉÉ TIO TI 0.25 (0.00) OTOO O I I T 3 29

42 T IX (TOP 8) I O (0.006) T 0.5 (0.006) T 0.0 (0.004) TI PI IT. 2X / x 0.0 (0.004) T TI TI 0.25 (0.00) ÇÇÇ ÉÉ TIO W IIOI TOI P I Y4.5, OTOI IIO: IIT. 3 IIO O OT I O. POTIO O T. O O T OT X 0.5 (0.006) P I. 4 IIO O OT I IT O POTIO. IT O POTIO OT X 0.25 (0.00) P I. 5 IIO O OT I POTIO. OW POTIO 0.08 (0.003) TOT I X O T IIO T XI TI OITIO. 6 TI OW O OY. 7 IIO TO TI T T W. IIT I IX (I 20) I O e 20 0 Z b 0.3 (0.005) (0.004) IW P TI P Q c IIOI TOI P I Y4.5, OTOI IIO: IIT. 3 IIO O OT I O O POTIO T T PTI I. O O POTIO OT X 0.5 (0.006) P I. 4 TI OW O OY. 5 T WIT IIO (b) O OT I POTIO. OW POTIO 0.08 (0.003) TOT I X O T WIT IIO T XI TI OITIO. OT OT O T OW I O T OOT. II P TW POTIO T TO 0.46 ( 0.08). IIT I b c e Q Z OTOO O I I T

43 T IX (TQP 20) I O X (0.008) T Z 20 6 TI Y 5. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. T I OT T OTTO O I OIIT WIT T W T XIT T PTI OY T T OTTO O T PTI I. 4. T,, Z TO TI T T. 5. IIO TO TI T T. 6. IIO O OT I O POTIO. OW POTIO I (0.00) P I. IIO O I O IT TI T T. 7. IIO O OT I POTIO. POTIO OT T IIO TO X (0.04). 8. II O PT TI (0.0003). 9. XT P O O I OPTIO. 5 4X (0.008) T Z 0 Z TI IIT I P Q W X TOP & OTTO (0.003) ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ (0.003) T Z TIO,, Z W TI X Q (0.00) TI Y OTOO O I I T 3 3

44 T IX I O X (0.008) T Z 24 9 TI Y. IIOI TOI P I Y4.5, OTOI IIO: IIT. 3. T I OT T OTTO O I OIIT WIT T W T XIT T PTI OY T T OTTO O T PTI I. 4. T,, Z TO TI T T. 5. IIO TO TI T T. 6. IIO O OT I O POTIO. OW POTIO I (0.00) P I. IIO O I O IT TI T T. 7. IIO O OT I POTIO. POTIO OT T IIO TO X (0.04). 8. II O PT TI (0.0003). 9. XT P O O I OPTIO. 6 4X (0.008) T Z 2 Z 8 3 IIT I P Q W X TI,, Z TOP & OTTO (0.003) ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ P TI Y W TI X Q (0.00) (0.003) T Z TIO 3 32 OTOO O I I T

45 IX 22 0 (OT 23) I O IIO I IIT. 2. ITPT IIO TO P Y4.5, T I TI e e 5X 0.0 IIT I I X e 0.95 e IX 23 0 (OT 89) I O 2. IIO I IIT. 2. ITPT IIO TOI P Y4.5, T I TI. e e 0.0 2X 0.0 IIT I I X e.50 e OTOO O I I T 3 33

LOW NOISE, JFET INPUT OPERATIONAL AMPLIFIERS

LOW NOISE, JFET INPUT OPERATIONAL AMPLIFIERS These low noise T input operational amplifiers combine two state of the art analog technologies on a single monolithic integrated circuit. ach internally compensated operational amplifier has well matched

More information

Amplifiers JFET INPUT OPERATIONAL AMPLIFIERS

Amplifiers JFET INPUT OPERATIONAL AMPLIFIERS These low cost T input operational amplifiers combine two state of the art linear technologies on a single monolithic integrated circuit. ach internally compensated operational amplifier has well matched

More information

OPERATIONAL AMPLIFIER

OPERATIONAL AMPLIFIER The 74 was designed for use as a summing amplifier, integrator, or amplifier with operating characteristics as a function of the external feedback components. o requency ompensation Required hort ircuit

More information

MC33076P2 DUAL HIGH OUTPUT CURRENT OPERATIONAL AMPLIFIER

MC33076P2 DUAL HIGH OUTPUT CURRENT OPERATIONAL AMPLIFIER The 33076 operational amplifier employs bipolar technology with innovative high performance concepts for audio and industrial applications. This device uses high frequency PP input transistors to improve

More information

MC1723C VOLTAGE REGULATOR

MC1723C VOLTAGE REGULATOR The 723 is a positive or negative voltage regulator designed to deliver load current to 50 mdc. Output current capability can be increased to several amperes through use of one or more external pass transistors.

More information

Representative Schematic Diagram. Standard Application ORDERING INFORMATION DEVICE TYPE/NOMINAL VOLTAGE MOTOROLA ANALOG IC DEVICE DATA

Representative Schematic Diagram. Standard Application ORDERING INFORMATION DEVICE TYPE/NOMINAL VOLTAGE MOTOROLA ANALOG IC DEVICE DATA The 7800, eries of positive voltage regulators are inexpensive, easytouse devices suitable for a multitude of applications that require a regulated supply of up to 00 m. ike their higher powered 7800 and

More information

SG3527A PULSE WIDTH MODULATOR CONTROL CIRCUITS

SG3527A PULSE WIDTH MODULATOR CONTROL CIRCUITS The 3525, 3527 pulse width modulator control circuits offer improved performance and lower external parts count when implemented for controlling all types of switching power supplies. The on chip +5. reference

More information

TDA1085C UNIVERSAL MOTOR SPEED CONTROLLER

TDA1085C UNIVERSAL MOTOR SPEED CONTROLLER The T085 is a phase angle triac controller having all the necessary functions for universal motor speed control in washing machines. It operates in closed loop configuration and provides two ramp possibilities.

More information

LM148 Low Power Quad 741 Operational Amplifier

LM148 Low Power Quad 741 Operational Amplifier Low Power Quad 4 Operational mplifier www.fairchildsemi.com Features 4 op amp operating characteristics Low supply current drain. m/amplifier lass output stage no crossover distortion Pin compatible with

More information

DG417/418/419. Precision CMOS Analog Switches. Features Benefits Applications. Description. Functional Block Diagram and Pin Configuration

DG417/418/419. Precision CMOS Analog Switches. Features Benefits Applications. Description. Functional Block Diagram and Pin Configuration G417/418/419 Precision MO Analog witches Features Benefits Applications 1-V Analog ignal Range On-Resistance r (on) : 2 Fast witching Action t ON : 1 ns Ultra Low Power Requirements P :3 nw TTL and MO

More information

8-Input NAND Gate IN74HCT30A TECHNICAL DATA LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE. Rev. 00

8-Input NAND Gate IN74HCT30A TECHNICAL DATA LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE. Rev. 00 TENIL T IN74T3 8-Input NN ate The IN74T3 is high-speed Si-gate MOS device and is pin compatible with low power Schottky TTL (LSTTL). The device provide the 8-input NN function. Outputs irectly Interface

More information

Integrated Silicon Pressure Sensor Altimeter/Barometer Pressure Sensor On-Chip Signal Conditioned, Temperature Compensated and Calibrated

Integrated Silicon Pressure Sensor Altimeter/Barometer Pressure Sensor On-Chip Signal Conditioned, Temperature Compensated and Calibrated reescale emiconductor Technical Data Integrated ilicon Pressure ensor ltimeter/arometer Pressure ensor On-hip ignal onditioned, Temperature ompensated and alibrated The PX4115 series is designed to sense

More information

AOZ6115 High Performance, Low R ON, SPST Analog Switch

AOZ6115 High Performance, Low R ON, SPST Analog Switch OZ6115 High Performance, Low R ON, PT nalog witch General Description The OZ6115 is a high performance single-pole single-throw (PT), low power, TTL-compatible bus switch. The OZ6115 can handle analog

More information

3-TERMINAL 0.1A NEGATIVE VOLTAGE REGULATOR

3-TERMINAL 0.1A NEGATIVE VOLTAGE REGULATOR 3-TERMINAL A NEGATIE OLTAGE REGULATOR FEATURES Output Current Up to 1 No External Components Internal Thermal Overload Protection Internal Short-Circuit Limiting Output oltage of 5, 6, 8, 9, 12, 15, 18

More information

SEMICONDUCTOR TECHNICAL DATA VOLTAGE CONTROLLED MULTIVIBRATOR. Not Recommended for New Designs

SEMICONDUCTOR TECHNICAL DATA VOLTAGE CONTROLLED MULTIVIBRATOR. Not Recommended for New Designs IONUTOR TNI T The 1658 is a voltage controlled multivibrator which provides appropriate level shifting to produce an output compatible with III and 10,000 logic levels. requency control is accomplished

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS ogic Family Specifications The IC06 74HC/HCT/HCU/HCMOS ogic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

AOZ6135 High Performance, Low R ON, 1Ω SPDT Analog Switch

AOZ6135 High Performance, Low R ON, 1Ω SPDT Analog Switch OZ6135 High Performance, Low R ON, 1Ω PDT nalog witch General Description The OZ6135 is a high performance single-pole double-throw (PDT), low power, TTL-compatible bus switch. The OZ6135 can handle analog

More information

General Purpose Transistors

General Purpose Transistors General Purpose Transistors PNP Silicon Moisture Sensitivity Level: 1 ESD Rating Human Body Model: >4000 ESD Rating Machine Model: >400 Pb-Free Packages are Available LB856ALT1G Series 3 MAXIMUM RATINGS

More information

Quad SPST CMOS Analog Switches

Quad SPST CMOS Analog Switches Quad PT MO Analog witches Low On-Resistance: Low Leakage: 8 pa Low Power onsumption:.2 mw Fast witching Action t ON : 1 ns Low harge Injection Q: 1 p G21A/G22 Upgrades TTL/MO-ompatible Logic ingle upply

More information

L4970A 10A SWITCHING REGULATOR

L4970A 10A SWITCHING REGULATOR L4970A 10A SWITCHING REGULATOR 10A OUTPUT CURRENT.1 TO 40 OUTPUT OLTAGE RANGE 0 TO 90 DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REGULA- TION INTERNAL CURRENT LIMITING PRECISE.1 ± 2 ON CHIP REFERENCE

More information

8-Input NAND Gate IN74HC30A TECHNICAL DATA LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE. Rev. 00

8-Input NAND Gate IN74HC30A TECHNICAL DATA LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE. Rev. 00 TENIL T IN743 8-Input NN ate The IN743 is high-speed Si-gate MOS device and is compatible with low power Schottky TTL (LSTTL). The device provide the 8-input NN function. Outputs irectly Interface to MOS,

More information

*1. Attention should be paid to the power dissipation of the package when the output current is large.

*1. Attention should be paid to the power dissipation of the package when the output current is large. S-1313 Series www.ablic.com www.ablicinc.com SUPER LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR ABLIC Inc., 211-216 Rev.2.1_1 The S-1313 Series, developed by using the CMOS technology, is

More information

High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS SEIONDUTOR TENI DT igh Performance Silicon ate OS The 5/7T00 may be used as a level converter for interfacing TT or NOS outputs to high speed OS inputs. The T00 is identical in pinout to the S00. Output

More information

ML ML Digital to Analog Converters with Serial Interface

ML ML Digital to Analog Converters with Serial Interface OS LSI L L Digital to Analog onverters with Serial Interface Legacy Device: otorola/reescale, The L and L are low cost 6 bit D/A converters with serial interface ports to provide communication with OS

More information

Low Drift, Low Power Instrumentation Amplifier AD621

Low Drift, Low Power Instrumentation Amplifier AD621 a FEATURES EASY TO USE Pin-Strappable Gains of 0 and 00 All Errors Specified for Total System Performance Higher Performance than Discrete In Amp Designs Available in -Lead DIP and SOIC Low Power,.3 ma

More information

MAX6325/MAX6341/MAX6350

MAX6325/MAX6341/MAX6350 VILLE 19-123; Rev 1; 1/1 Pin onfiguration 8V TO 36V INPUT TOP VIEW 2.2µF * NR IN TRI REFERENE 2.2µF * I.. IN NR 1 2 3 4 DIP/SO 8 7 6 5 I.. I.. TRI *OPTIONL I.. = INTERNLLY ONNETED; DO NOT USE For pricing,

More information

Dual 4-Input AND Gate

Dual 4-Input AND Gate TENIAL DATA Dual 4-Input AND ate The is high-speed Si-gate MOS device and is pin compatible with low power Schottky TTL (LSTTL). The device provide the Dual 4-input AND function. Outputs Directly Interface

More information

MC74HC08A. Quad 2 Input AND Gate High Performance Silicon Gate CMOS

MC74HC08A. Quad 2 Input AND Gate High Performance Silicon Gate CMOS Quad 2 Input AND Gate igh Performance Silicon Gate CMOS The MC74C08A is identical in pinout to the S08. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible

More information

Lecture 7: Transistors and Amplifiers

Lecture 7: Transistors and Amplifiers Lecture 7: Transistors and Amplifiers Hybrid Transistor Model for small AC : The previous model for a transistor used one parameter (β, the current gain) to describe the transistor. doesn't explain many

More information

PART TOP VIEW. Maxim Integrated Products 1

PART TOP VIEW. Maxim Integrated Products 1 9-96; Rev ; 2/ 45, SPDT Analog Switch in SOT23-8 General Description The is a dual-supply, single-pole/doublethrow (SPDT) analog switch. On-resistance is 45 max and flat (7 max) over the specified signal

More information

BCD-TO-DECIMAL DECODER HIGH-VOLTAGE SILICON-GATE CMOS IW4028B TECHNICAL DATA

BCD-TO-DECIMAL DECODER HIGH-VOLTAGE SILICON-GATE CMOS IW4028B TECHNICAL DATA TECHNICAL DATA BCD-TO-DECIMAL DECODER HIGH-OLTAGE SILICON-GATE CMOS IW4028B The IW4028B types are BCD-to-decimal or binary-tooctal decoders consisting of buffering on all 4 inputs, decoding-logic gates,

More information

Miniature Electronically Trimmable Capacitor V DD. Maxim Integrated Products 1

Miniature Electronically Trimmable Capacitor V DD. Maxim Integrated Products 1 19-1948; Rev 1; 3/01 Miniature Electronically Trimmable Capacitor General Description The is a fine-line (geometry) electronically trimmable capacitor (FLECAP) programmable through a simple digital interface.

More information

PH5504A2NA1. Ambient Light Sensor DESCRIPTION FEATURES APPLICATIONS. R08DS0067EJ0100 Rev.1.00 Nov 05, 2012 DISCONTINUED

PH5504A2NA1. Ambient Light Sensor DESCRIPTION FEATURES APPLICATIONS. R08DS0067EJ0100 Rev.1.00 Nov 05, 2012 DISCONTINUED Ambient Light Sensor DESCRIPTION Data Sheet The is an ambient light sensor with a photo diode and current amplifier. This product has spectral characteristics close to human eye sensitivity and outputs

More information

CD54/74HC30, CD54/74HCT30

CD54/74HC30, CD54/74HCT30 /70, /7T0 ata sheet acquired from arris Semiconductor SS ugust 997 - Revised September 00 igh Speed MOS Logic -Input NN ate [ /Title ( 0, 7 0, 7 T0) /Subject (igh Speed MOS Logic - eatures uffered Inputs

More information

Triple 3-Input NOR Gate

Triple 3-Input NOR Gate TENIAL DATA IN4T2A Triple 3-Input NOR ate The IN4T2A is high-speed Si-gate MOS device and is pin compatible with low power Schottky TTL (LSTTL). The device provide the Triple 3-input NOR function. Outputs

More information

74AUP1G95 TinyLogic Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

74AUP1G95 TinyLogic Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) 74UPG9 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) Features 0.8 V to.6 V V Supply Operation.6 V Over-Voltage Tolerant I/Os at V from 0.8V to.6 V Extremely High Speed

More information

At point G V = = = = = = RB B B. IN RB f

At point G V = = = = = = RB B B. IN RB f Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F

More information

PI5A3158. SOTINY TM Low Voltage Dual SPDT An a log Switch 2:1 Mux/DeMux Bus Switch. Features. Description. Connection Diagram.

PI5A3158. SOTINY TM Low Voltage Dual SPDT An a log Switch 2:1 Mux/DeMux Bus Switch. Features. Description. Connection Diagram. PI53158 OINY M Low Voltage Dual PD n a log witch Features CMO echnology for Bus and nalog pplications Low On-Resistance: 8Ω at 3.0V Wide Range: 1.65V to 5.5V Rail-to-Rail ignal Range Control Input Overvoltage

More information

CD74HC221, CD74HCT221

CD74HC221, CD74HCT221 November 997 SEMIONDUTO D74H22, D74HT22 High Speed MOS Logic Dual Monostable Multivibrator with eset Features Description Overriding ESET Terminates Output Pulse Triggering from the Leading or Trailing

More information

74LVC573 Octal D-type transparent latch (3-State)

74LVC573 Octal D-type transparent latch (3-State) INTEGRATED CIRCUITS 74VC573 Supersedes data of February 1996 IC24 Data andbook 1997 Mar 12 74VC573 FEATURES Wide supply voltage range of 1.2V to 3.6V In accordance with JEDEC standard no. 8-1A Inputs accept

More information

MC74HC00A. Quad 2 Input NAND Gate. High Performance Silicon Gate CMOS

MC74HC00A. Quad 2 Input NAND Gate. High Performance Silicon Gate CMOS MC74C00A Quad 2 Input NAND Gate igh Performance Silicon Gate CMOS The MC74C00A is identical in pinout to the S00. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they

More information

MC MC MC MC145408

MC MC MC MC145408 SEIOUTO TEHIAL ATA Order this document by 0/ EIA E and ITT. These devices are silicon gate OS Is that combine both the transmitter and receiver to fulfill the electrical specifications of EIA Standard

More information

AOZ Ω Low-Voltage Dual-DPDT Analog Switch

AOZ Ω Low-Voltage Dual-DPDT Analog Switch 0.3Ω Low-Voltage Dual-DPDT nalog witch General Description The OZ6274 is a dual Double-Pole, Double-Throw (DPDT) analog switch that is designed to operate from a single 1.65V to 4.3V supply. The OZ6274

More information

70 mv typ. (2.8 V output product, I OUT = 100 ma)

70 mv typ. (2.8 V output product, I OUT = 100 ma) S-1335 Series www.ablicinc.com HIGH RIPPLE-REJECTION SOFT-START FUNCTION CMOS VOLTAGE REGULATOR ABLIC Inc., 212-214 Rev.1.3_2 The S-1335 Series, developed by using the CMOS technology, is a positive voltage

More information

Cal-Chip Electronics, Incorporated TC Series Tantalum Solid Electrolytic Capacitors - Resin Molded Chip Type, Standard Type

Cal-Chip Electronics, Incorporated TC Series Tantalum Solid Electrolytic Capacitors - Resin Molded Chip Type, Standard Type : The T Series is designed for hybrid circuit and low profile printed circuit board applications where inductance is to be minimized, or where substrate space is at a premium. They can be attached to substrates

More information

2/4. Features / Advantages: Applications: Package: TO-263 (D2Pak) Diode for main rectification For single and three phase bridge configurations

2/4. Features / Advantages: Applications: Package: TO-263 (D2Pak) Diode for main rectification For single and three phase bridge configurations DSI3-6S Standard ectifier = 6 M I = 3 F F =.25 Single Diode Part number DSI3-6S Backside: cathode 3 2/4 Features / dvantages: pplications: Package: TO-263 (D2Pak) Planar passivated chips ery low leakage

More information

Quad SPST CMOS Analog Switches

Quad SPST CMOS Analog Switches Quad PT MO Analog witches ERIPTION The G441/442 monolithic quad analog switches are designed to provide high speed, low error switching of analog and audio signals. The G441 has a normally closed function.

More information

N-C hannel E nhancement Mode Field E ffect Transistor. T O-251(l-P AK ) (T A=25 C unles s otherwis e noted) 25 C 70 C IDM P D.

N-C hannel E nhancement Mode Field E ffect Transistor. T O-251(l-P AK ) (T A=25 C unles s otherwis e noted) 25 C 70 C IDM P D. amhop Microelectronics C orp. T U/1955NL N-C hannel E nhancement Mode Field E ffect Transistor rp,12 25 ver1.2 P R OUC T UMMR Y V I R (ON) ( m Ω ) Max 55V 55 @ V G = V 8 @ VG = 4.5V F E T UR E uper high

More information

Low-Power, High-Speed CMOS Analog Switches

Low-Power, High-Speed CMOS Analog Switches New Product G1B/3B/5B Low-Power, High-peed MO Analog witches FEATURE BENEFIT APPLIATION 44-V upply Max Rating 15-V Analog ignal Range On-Resistance r (on) : 23 Low Leakage I (on) : pa Fast witching t ON

More information

Switching Regulators MC33063A SOP

Switching Regulators MC33063A SOP MC0A Features Operation from.0 to 0 Input Low Standby Current Current Limiting Output oltage Adjustable Frequency Operation to 00 khz Pb Free Packages are Available Output Current to. A SOP- 0. 0.0-0.0.0

More information

±1.0% (1.0 V to 1.45 V output product : ±15 mv)

±1.0% (1.0 V to 1.45 V output product : ±15 mv) S-1135 Series www.sii-ic.com HIGH RIPPLE-REJECTION LOW DROPOUT MIDDLE OUTPUT CURRENT CMOS VOLTAGE REGULATOR Seiko Instruments Inc., 28-21 Rev.2._ S-1135 Series, developed using the CMOS technology, is

More information

FEATURES FUNCTIONAL BLOCK DIAGRAM

FEATURES FUNCTIONAL BLOCK DIAGRAM TECHNICAL DATA DC-TO-DC CONVETE CONTOL CICUIT IL0A The IL0A is a monolithic control circuit containing the primary functions required for DC-to-DC converters. These devices consist of an internal temperature

More information

PT5108. High-PSRR 500mA LDO GENERAL DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATIONS. Ripple Rejection vs Frequency. Ripple Rejection (db)

PT5108. High-PSRR 500mA LDO GENERAL DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATIONS. Ripple Rejection vs Frequency. Ripple Rejection (db) GENERAL DESCRIPTION The PT5108 is a low-dropout voltage regulator designed for portable applications that require both low noise performance and board space. Its PSRR at 1kHz is better than 70dB. The PT5108

More information

SERVOSTAR S- and CD-Series Regeneration Requirements

SERVOSTAR S- and CD-Series Regeneration Requirements www.danaherotion.com SEROSTAR S- and CD-Series Regeneration Requirements One of the key (and often overlooked) considerations for servo system sizing is regeneration requirements. An undersized regeneration

More information

74AUP1G59 TinyLogic Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

74AUP1G59 TinyLogic Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) 74UP1G9 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate (Open Drain Output) Features 0.8V to.v V Supply Operation.V Over-Voltage Tolerant I/Os at V from 0.8V to.v Extremely High Speed tpd

More information

MC MC35172 LOW POWER DUAL BIPOLAR OPERATIONAL AMPLIFIERS.. GOOD CONSUMPTION/SPEED RATIO : ONLY 200µA/Amp FOR 2.1MHz, 2V/µs

MC MC35172 LOW POWER DUAL BIPOLAR OPERATIONAL AMPLIFIERS.. GOOD CONSUMPTION/SPEED RATIO : ONLY 200µA/Amp FOR 2.1MHz, 2V/µs MC3372 MC3572 LOW POWER DUAL BIPOLAR OPERATIONAL AMPLIFIERS GOOD CONSUMPTION/SPEED RATIO : ONLY 200µA/Amp FOR 2MHz, 2/µs SINGLE (OR DUAL) SUPPLY OPERATION FROM +4 TO +44 (±2 TO ±22) WIDE INPUT COMMON MODE

More information

74LV373 Octal D-type transparent latch (3-State)

74LV373 Octal D-type transparent latch (3-State) INTEGRATED CIRCUITS 74V373 Supersedes data of 1997 March 04 IC24 Data andbook 1998 Jun 10 74V373 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for ow Voltage applications: 1.0V to 3.6V Accepts

More information

1 pc Charge Injection, 100 pa Leakage, CMOS 5 V/+5 V/+3 V Quad SPST Switches ADG611/ADG612/ADG613

1 pc Charge Injection, 100 pa Leakage, CMOS 5 V/+5 V/+3 V Quad SPST Switches ADG611/ADG612/ADG613 a FEATURE 1 pc Charge Injection 2.7 V to 5.5 V ual upply +2.7 V to +5.5 V ingle upply Automotive Temperature Range 4 C to +125 C 1 pa Max @ 25 C Leakage Currents 85 On-Resistance Rail-to-Rail witching

More information

Octal 3-State Noninverting Transparent Latch

Octal 3-State Noninverting Transparent Latch TECNICAL DATA IN74CT373A Octal 3-State Noninverting Transparent Latch The IN74CT373A may be used as a level converter for interfacing TTL or NMOS outputs to igh-speed CMOS inputs. The IN74CT373A is identical

More information

Class 1, 100 V (DC) (flanged types) Miniature ceramic plate capacitors

Class 1, 100 V (DC) (flanged types) Miniature ceramic plate capacitors FEATURES High-frequency circuits Temperature compensating High stability Space saving. APPLICATIONS In a great variety of electronic circuits, e.g. in filters and tuning circuits where high stability and/or

More information

STS3401. P -C hannel E nhancement Mode MOS FE T. ABS OLUTE MAXIMUM R ATINGS (T A=25 C unless otherwise noted) THE R MAL C HAR AC TE R IS TIC S

STS3401. P -C hannel E nhancement Mode MOS FE T. ABS OLUTE MAXIMUM R ATINGS (T A=25 C unless otherwise noted) THE R MAL C HAR AC TE R IS TIC S T341 P - hannel E nhancement Mode MO FE T P R ODU T UMMR Y V D ID -3V -3 F E T UR E ( m W ) Max R D (ON) 7 @ V = -1V 1 @ V = -4.V uper high dee cell design for low R D (ON ). R ugged and reliable. OT-23

More information

Package Type. IXDD614PI 8-Pin DIP Tube 50 OUT 8-Lead Power SOIC with Exposed Metal Back Tube 100

Package Type. IXDD614PI 8-Pin DIP Tube 50 OUT 8-Lead Power SOIC with Exposed Metal Back Tube 100 IXD_64 4-Ampere Low-Side Ultrafast MOSFET Drivers Features 4A Peak Source/Sink Drive Current Wide Operating Voltage Range: 4.V to V - C to +2 C Extended Operating Temperature Range Logic Input Withstands

More information

SGM7227 High Speed USB 2.0 (480Mbps) DPDT Analog Switch

SGM7227 High Speed USB 2.0 (480Mbps) DPDT Analog Switch GENERAL DECRIPTION The GM7227 is a high-speed, low-power double-pole/ double-throw (DPDT) analog switch that operates from a single 1.8V to 4.3V power supply. GM7227 is designed for the switching of high-speed

More information

Maintenance/ Discontinued

Maintenance/ Discontinued Cs for CD/CD-RM Player AN886SB 4ch. Linear Driver C for CD/CD-RM verview The AN886SB is a 4ch. driver using the power operational amplifier method. t employs the surface mounting type package superior

More information

LC2 MOS 4-/8-Channel High Performance Analog Multiplexers ADG408/ADG409

LC2 MOS 4-/8-Channel High Performance Analog Multiplexers ADG408/ADG409 a FEATURES 44 upply Maximum Ratings to Analog Signal Range Low On Resistance ( max) Low Power (I SUPPLY < 75 A) Fast Switching Break-Before-Make Switching Action Plug-in Replacement for G408/G409 APPLICATIONS

More information

Characteristic Symbol Value Units V GSS

Characteristic Symbol Value Units V GSS NEW PROUCT Features Low On-Resistance: R S(ON) Low Gate Threshold Voltage Low Input Capacitance Fast Switching Speed Low Input/Output Leakage Complementary Pair lso vailable in Lead Free Version Mechanical

More information

S-13R1 Series REVERSE CURRENT PROTECTION CMOS VOLTAGE REGULATOR. Features. Applications. Packages. ABLIC Inc., Rev.1.

S-13R1 Series REVERSE CURRENT PROTECTION CMOS VOLTAGE REGULATOR. Features. Applications. Packages.  ABLIC Inc., Rev.1. www.ablicinc.com REVERSE CURRENT PROTECTION CMOS VOLTAGE REGULATOR ABLIC Inc., 212-214 Rev.1.2_2 The, developed by using the CMOS technology, is a positive voltage regulator IC of 15 ma output current,

More information

ON OFF PART. Pin Configurations/Functional Diagrams/Truth Tables 5 V+ LOGIC

ON OFF PART. Pin Configurations/Functional Diagrams/Truth Tables 5 V+ LOGIC 9-88; Rev ; /7 25Ω SPST Analog Switches in SOT23-6 General Description The are dual-supply single-pole/single-throw (SPST) switches. On-resistance is 25Ω max and flat (2Ω max) over the specified signal

More information

Logic Configuration Part Number Package Type Packing Method Quantity. IX4423N 8-Pin SOIC Tube 100 IX4423NTR 8-Pin SOIC Tape & Reel 2000

Logic Configuration Part Number Package Type Packing Method Quantity. IX4423N 8-Pin SOIC Tube 100 IX4423NTR 8-Pin SOIC Tape & Reel 2000 IX23-IX2-IX25 3-mpere Dual Low-Side Ultrafast MOSFET Drivers Features 3 Peak Output Current Wide Operating Voltage Range:.5V to 35V - C to +25 C Operating Temperature Range Latch-up Protected to 3 Fast

More information

AOZ Ω Low-Voltage Dual SPDT Analog Switch. General Description. Features. Applications AOZ6236

AOZ Ω Low-Voltage Dual SPDT Analog Switch. General Description. Features. Applications AOZ6236 0.35 Ω Low-Voltage Dual PDT nalog witch General Description The OZ6236 is a 0.35 Ω low-voltage Dual ingle Pole Double Throw (PDT) analog switch. The OZ6236 operates from a single 1.65 V to 4.3 V supply.

More information

Chip Photodiode with Right Angle Lens EAPDSV3020A2

Chip Photodiode with Right Angle Lens EAPDSV3020A2 Features Fast response time High photo sensitivity Small junction capacitance Package in 8mm tape in 7 diameter reel Pb free The product itself will remain within RoHS compliant version. Descriptions is

More information

TC74HC4051AP,TC74HC4051AF,TC74HC4051AFT TC74HC4052AP,TC74HC4052AF,TC74HC4052AFT TC74HC4053AP,TC74HC4053AF,TC74HC4053AFN,TC74HC4053AFT

TC74HC4051AP,TC74HC4051AF,TC74HC4051AFT TC74HC4052AP,TC74HC4052AF,TC74HC4052AFT TC74HC4053AP,TC74HC4053AF,TC74HC4053AFN,TC74HC4053AFT T4H40,40P/F/FT,40P/F/FN/FT TOSHI MOS Digital Integrated ircuit Silicon Monolithic T4H40P,T4H40F,T4H40FT T4H40P,T4H40F,T4H40FT T4H40P,T4H40F,T4H40FN,T4H40FT T4H40P/F/FT 8-hannel nalog Multiplexer/Demulitiplexer

More information

MT4106 Series Uni-polar, Hall-Effect

MT4106 Series Uni-polar, Hall-Effect Uni-polar, Hall-Effect Magnetic Position ensors Features and Benefits Bipolar Technology Magnetic Type: Uni-polar Wide Operating Voltage Range: upply Voltage 3.8~30V pecified Operating Temperature Range:

More information

SGM7SZ00 Small Logic Two-Input NAND Gate

SGM7SZ00 Small Logic Two-Input NAND Gate GENERAL DESCRIPTION The SGM7SZ00 is a single two-input NAND gate from SGMICRO s Small Logic series. The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive

More information

Operational Amplifier (Op-Amp) Operational Amplifiers. OP-Amp: Components. Internal Design of LM741

Operational Amplifier (Op-Amp) Operational Amplifiers. OP-Amp: Components. Internal Design of LM741 (Op-Amp) s Prof. Dr. M. Zahurul Haq zahurul@me.buet.ac.bd http://teacher.buet.ac.bd/zahurul/ Department of Mechanical Engineering Bangladesh University of Engineering & Technology ME 475: Mechatronics

More information

Maintenance/ Discontinued

Maintenance/ Discontinued oltage Regulators N7xx/N7xxF Series 3-pin positive output voltage regulator ( type) Overview The N7xx series and the N7xxF series are 3- pin, fixed positive output type monolithic voltage regulators. Stabilized

More information

DG411CY. Pin Configurations/Functional Diagrams/Truth Tables IN2 DG412 IN3 DIP/SO/TSSOP DG412 LOGIC SWITCH OFF SWITCHES SHOWN FOR LOGIC 0 INPUT

DG411CY. Pin Configurations/Functional Diagrams/Truth Tables IN2 DG412 IN3 DIP/SO/TSSOP DG412 LOGIC SWITCH OFF SWITCHES SHOWN FOR LOGIC 0 INPUT 9-728; Rev ; 9/0 Improved, Quad, General escription Maxim s redesigned analog switches now feature low on-resistance matching between switches (Ω max) and guaranteed on-resistance flatness over the signal

More information

2-channel analog multiplexer/demultiplexer. The 74LVC2G53 can handle both analog and digital signals.

2-channel analog multiplexer/demultiplexer. The 74LVC2G53 can handle both analog and digital signals. Rev. 0 0 January 006 Product data sheet. General description. Features The is a high-performance, low-power, low-voltage, i-gate CMO device that provides superior performance to most advanced CMO compatible

More information

UNISONIC TECHNOLOGIES CO., LTD

UNISONIC TECHNOLOGIES CO., LTD U74C563 UNISONIC TECNOOGIES CO., TD OCTA TRANSPARENT D-TYPE ATCES WIT 3-STATE OUTPUTS DESCRIPTION The U74C563 is a octal traparent D-TYPE latches with 3-state outputs. When the latch-enable (E) is high,

More information

Io=500mA LDO with Reset function

Io=500mA LDO with Reset function Io=mA LDO with Reset function GENERAL DESCRIPTION The NJW4116 is a ma output low dropout voltage regulator with reset function monitoring output voltage. Reset Output Hold Time is adjustable by external

More information

Features Lead free as standard RoHS compliant* Leadless Low stored charge

Features Lead free as standard RoHS compliant* Leadless Low stored charge *RoHS OMPLINT 6 Features Lead free as standard RoHS compliant* Leadless Low stored charge pplications ellular phones Ps esktop Ps and notebooks igital cameras MP3 players 85-xxxx products are currently

More information

GENERAL DESCRIPTION The PT5128 is a dual channel low-dropout voltage regulator designed for portable and wireless applications that require high PSRR, low quiescent current and excellent line and load

More information

Quad SPST CMOS Analog Switch

Quad SPST CMOS Analog Switch Quad PT CMO Analog witch HI-201/883 The HI-201/883 is a monolithic device comprised of four independently selectable PT switchers which feature fast switching speeds (185ns typical) combined with low power

More information

The IK642B is a bi-polar integrated circuit designed for the wiper application in the automotive market. It includes wipe, wash and internal mode.

The IK642B is a bi-polar integrated circuit designed for the wiper application in the automotive market. It includes wipe, wash and internal mode. TECHNICAL DATA INTERAL- and WIPE/WASH WIPER CONTROL IC IK642B The IK642B is a bi-polar integrated circuit designed for the wiper application in the automotive market. It includes wipe, wash and internal

More information

SPECIFICATIONS FOR UPEC SMD TYPE WHITE LED

SPECIFICATIONS FOR UPEC SMD TYPE WHITE LED SPEIFIATIONS FOR UPE SMD TYPE WHITE LED MODEL: Features P-L-2 package Wide viewing angle Inter reflector Available on tape and reel ( 8mm Tape ) Package Dimensions Part NO. hip Material Lens olor Source

More information

LMBZ52xxBLG Series. 225 mw SOT 23 Surface Mount LESHAN RADIO COMPANY, LTD. 1/6

LMBZ52xxBLG Series. 225 mw SOT 23 Surface Mount LESHAN RADIO COMPANY, LTD. 1/6 5 mw SOT Surface Mount This series of Zener diodes is offered in the convenient, surface mount plastic SOT package. These devices are designed to provide voltage regulation with minimum space requirement.

More information

MAU100 Series. 1W, Miniature SIP, Single & Dual Output DC/DC Converters MINMAX. Key Features

MAU100 Series. 1W, Miniature SIP, Single & Dual Output DC/DC Converters MINMAX. Key Features W, Miniature SIP, Single & Dual Output DC/DC s Key Features Efficiency up to % 000 Isolation MTBF >,000,000 Hours Low Cost Input,, and Output 3.3,,9,,,{,{9,{ and { Temperature Performance -0] to +] UL

More information

KH600. 1GHz, Differential Input/Output Amplifier. Features. Description. Applications. Typical Application

KH600. 1GHz, Differential Input/Output Amplifier. Features. Description. Applications. Typical Application KH 1GHz, Differential Input/Output Amplifier www.cadeka.com Features DC - 1GHz bandwidth Fixed 1dB (V/V) gain 1Ω (differential) inputs and outputs -7/-dBc nd/3rd HD at MHz ma output current 9V pp into

More information

BOLUTE MXIMUM TING These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the ope

BOLUTE MXIMUM TING These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the ope P0. Buck/Boost/Inverting DCDC ing egulator FETUE upply oltage: Current Limiting Output Current to. djustable Output oltage Operation frequency up to 0KHz Low Quiescent Current Precision % eference vailable

More information

IGBT Designer s Manual

IGBT Designer s Manual IGBT Designer s Manual Data Sheets The IGBT devices listed in this Designer s Manual represent International Rectifier s IGBT line as of August, 994. The data presented in this manual supersedes all previous

More information

Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS

Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS TECNICAL DATA Octal 3-State Noninverting Buffer/Line Driver/Line Receiver igh-performance Silicon-ate CMOS IN74CT244A The IN74CT244A is identical in pinout to the LS/ALS244. The device may be used as a

More information

74F Bit Random Access Memory with 3-STATE Outputs

74F Bit Random Access Memory with 3-STATE Outputs April 1988 Revised July 1999 74F189 64-Bit Random Access Memory with 3-STATE Outputs General Description The F189 is a high-speed 64-bit RAM organized as a 16- word by 4-bit array. Address inputs are buffered

More information

High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS SEIODUTOR TEHI DT High Performance Silicon ate OS The 54/74H02 is identical in pinout to the S02. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with

More information

SGM48753 CMOS Analog Switch

SGM48753 CMOS Analog Switch GENERAL DESCRIPTION The is a CMOS analog IC configured as three single-pole/double-throw (SPDT) switches. This CMOS device can operate from 2.5V to 5.5V single supplies. Each switch can handle rail-to-rail

More information

Top View Bottom View Internal Schematic (Top View)

Top View Bottom View Internal Schematic (Top View) W P M3415FY4Q P-H HM M MF Product ummary B) -16 ) max 39mΩ @ = -4.5 52mΩ @ = -2.5 65mΩ @ = -1.8 escription and pplications max = +25-2.5-2.1-1.8 his MF is designed to minimize the on-state resistance ))

More information

1.5A Buck/Boost/Inverting DC-DC Switching Regulator

1.5A Buck/Boost/Inverting DC-DC Switching Regulator P0. Buck/Boost/Inverting DCDC ing egulator FETUE upply oltage: Current Limiting Output Current to. djustable Output oltage Operation frequency up to 0KHz Low Quiescent Current Precision % eference vailable

More information

CONDITIONS T amb = 25 C; GND = 0V

CONDITIONS T amb = 25 C; GND = 0V Octal -type traparent latch (-State) FATURS is flow-through pinout version of 7ABT7 Inputs and outputs on opposite side of package allow easy interface to microprocessors -State output buffers Common output

More information

Time - timing relays 1 Industrial relays, solid state output, width 22.5 mm

Time - timing relays 1 Industrial relays, solid state output, width 22.5 mm haracteristics Zelio ime - timing relays Industrial relays, solid state output, width. mm Presentation 08 he E9 range of relays is designed for simple, repetitive applications with short and intensive

More information

Dual 4-Input AND Gate

Dual 4-Input AND Gate TENIAL DATA IN42A Dual 4-Input AND ate The IN42A is high-speed Si-gate MOS device and is pin compatible with pullup resistors with low power Schottky TTL (LSTTL). The device provide the Dual 4-input AND

More information

Technical Data Sheet Silicon PIN Photodiode

Technical Data Sheet Silicon PIN Photodiode Technical Data Sheet Silicon PIN Photodiode Features Fast response time High photo sensitivity Small junction capacitance Pb free The product itself will remain within RoHS compliant version. Descriptions

More information