Pluging in values for the parameters from table 6.1 we obtain switching resistance,
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1 Problem 10.1 By Vehid Suljic Using the parameters in Table 6.1 compare the hand-calculated effective digital switching resistance using Eq. (10.6) to the empirically derived values given in table Using equation 10.6, Rn = VDD/[0.5 KPn (W/L) (VDD-Vthn) 2 ] Pluging in values for the parameters from table 6.1 we obtain switching resistance, Rn = 4.7K (L/W) However, empirically derived Rn in table 10.1 is Rn = 15K (L/W) which is very different from hand calculated results above. This is due to the mobility (µ, Kpn = µ Cox ) that is not constant with applied voltage (electric field).
2 Problem 10.5 Indira Priyadarshini. Vemula For the following circuits estimate the delay between the input and the output. Use the 50nm (short channel CMOS)process. Verify the estimates with spice? a) ***PROBLEM 10.5A****.control destroy all run plot vout vin ylimit 0 1.endc.option scale=50n.ic v(vout)=1.tran 10p 500p UIC vin vin 0 dc 0 pulse p 100p M1 vout vin 0 0 NMOS L=1 W=10 C1 vout 0 20f **models included t delay =0.7*R n *C tot =0.7*34K/10*(62.5 af*10+20 Ff) =49.08 ps
3 b) ***PROBLEM 10.5B****.control destroy all run plot vout vin ylimit 0 1.endc.option scale=50n.tran 10p 4n UIC vdd vdd 0 dc 1 vin vin 0 dc 0 pulse p 100p 100p 1n 2n M1 vout vin n1 0 NMOS L=1 W=10 M2 n1 vdd 0 0 NMOS L=10 W=10 C1 vout 0 20f IC=1 R n =3.4K+3.4K =6.8K t delay =0.7*6.8K*(62.5 Af*10+20 ff) =98.17 ps **models included We are doing this problem using short channel process, but here the length of the MOFET is 10 which cause the resistance to increase. This results in increase in time delay when compared to the calculated value.
4 C) t delay =0.7*Rp*C tot =0.7*68K/20(62.5 Af*20*20+20 ff) =107.1 ps ***PROBLEM 10.5c****.control destroy all run plot vout vin.endc.option scale=50n.ic v(vout)=0 v(vin)=1.tran 10p 8n UIC vdd vdd 0 dc 1 vin vin 0 dc 0 pulse p 100p M1 vout vin vdd vdd PMOS L=20 W=20 C1 vout 0 20f **models included We are doing this problem using short channel process, but here the length of the MOFET is 20 which cause the resistance to increase. This results in increase in time delay when compared to the calculated value.
5 d) t delay =0.35*Rp*C ox *l *Rp*C L *l =(0.35*3.4K*1.25Ff*16)+(0.7*3.4K*10Ff*4) =119 ps ***PROBLEM 10.5d****.control destroy all run plot vout vin ylimit 0 1.endc.option scale=50n.tran 10p 12n 5n UIC vdd vdd 0 dc 1 vin vin 0 dc 0 pulse 0 1 5n 100p 100p 5n 10n M1 vin 0 n1 vdd PMOS L=1 W=20 M2 n1 0 n2 vdd PMOS L=1 W=20 M3 n2 0 n3 vdd PMOS L=1 W=20 M4 n3 0 vout vdd PMOS L=1 W=20 C1 vout 0 10f **models included
6 PROBLEM # 11.1 Meshack Pavan.A Estimate the noise margins for the inverters used to generate Fig Solution: - From the graphs in Fig and the text in p11.3, we have V OH = 5V V OL = 0V V IL = 1.8V V IH = 2.1V Therefore, noise margins, NM H = V OH - V IH = = 2.9V NM L = V IL - V OL = = 1.8V Long channel Process For the short channel process, similarly from the graph and text in the book, V OH = 1V V OL = 0V V IL = 400mV V IH = 500mV So, noise margins, NM H = V OH - V IH = = 0.5V = 500mV NM L = V IL - V OL = = 0.4V = 400mV
7 Assignment #10 Vinay Dindi EE510 Due Date-4/12/ ) Design and simulate the DC characteristics of an inverter with Vsp approximately equal to VTHn. Estimate the resulting noise margins for the design. For Vsp~=Vthn, (ßn/ ßp) should be as large as possible. Let (ßn/ ßp)=90 So Wn=30*Wp assuming KPn=KPp and Ln=Lp If Wp=10, then Wn=300. Substituting these values in equation 11.4, we get Vsp=0.32. (Vtn=Vtp=0.28V from Table 6.3) From simulations we obtain Vsp~=0.27V.
8 John Spratt EE 510 Chap 10 HW 4/4/2004 Problem 11.5: Repeat Ex using the long channel process with a 30/10 inverter. Solution: *** Top Level Netlist *** vdd vdd 0 DC 5 Vin vin 0 DC 0 pulse 0 5 1n 0p 0p 1n 2n C1 Vout 0 50fF M1 M2 Vout Vin 0 0 NMOS L=1u W=10u Vout Vin Vdd Vdd PMOS L=1u W=30u Simulation: tphl=69ps tplh=67ps
9 John Spratt EE 510 Chap 10 HW 4/4/2004 Taking into account the output capacitance of the MOS s: tphl=.7*rp*ctot=.7*45k/30*(1.75f*(30+10)+50f)=126ps tplh=.7*rn*ctot=.7*15k/10*(1.75f*(30+10)+50f)=126ps W/O taking into account the output capacitance of the MOS s: tphl=.7*rp*ctot=.7*45k/30*(50f)=52.5ps tplh=.7*rn*ctot=.7*15k/10*(50f)=52.5ps W/O appears to be closer to the sim.
10 Problem 11.6 Steve Bard Estimate the oscillation frequency of an 11-stage ring oscillator using 30/10 inverters in the long-channel CMOS process. Compare your hand calculations to the simulation results. Solution: The frequency is about 250 MHz when calculated by hand. When simulated on SPICE, the frequency is higher, reaching 495 MHz. The hand calculations are shown below, and the SPICE simulation is shown on the next page. f rosc = n ( t + t ) PHL 1 PLH t + t = PHL TOT PLH ( R n R p ) C TOT ( C C ) 5 C = + 2 oxp oxn R R n p L = 15 k W L = 45 k W 15 k = = 1.5k k = = 1.5k 30 C C oxp oxn = 1.75 ff W L = 52.5 ff = 1.75 ff W L = 17.5 ff 5 C TOT = ( 52.5 ff ff ) = ff ( k + 1.5k) (175 ff) ps t PHL + t PLH = = f rosc = 250MHz ps ( )
11 From the SPICE simulation, the frequency = 1/T = 1 / 2.02 ns = 495 MHz. *** Problem 11.6 ***.control destroy all run plot vout.endc.option scale=1u.tran.1n 6.5n uic vdd vdd 0 DC 5 R1 vout 0 1MEG **********D********G*******S*******B**** M1 vout1 vout 0 0 NMOS L=1 W=10 M2 vout1 vout vdd vdd PMOS L=1 W=30 M3 vout2 vout1 0 0 NMOS L=1 W=10 M4 vout2 vout1 vdd vdd PMOS L=1 W=30 M5 vout3 vout2 0 0 NMOS L=1 W=10 M6 vout3 vout2 vdd vdd PMOS L=1 W=30 M7 vout4 vout3 0 0 NMOS L=1 W=10 M8 vout4 vout3 vdd vdd PMOS L=1 W=30 M9 vout5 vout4 0 0 NMOS L=1 W=10 M10 vout5 vout4 vdd vdd PMOS L=1 W=30 M11 vout6 vout5 0 0 NMOS L=1 W=10 M12 vout6 vout5 vdd vdd PMOS L=1 W=30 M13 vout7 vout6 0 0 NMOS L=1 W=10 M14 vout7 vout6 vdd vdd PMOS L=1 W=30 M15 vout8 vout7 0 0 NMOS L=1 W=10 M16 vout8 vout7 vdd vdd PMOS L=1 W=30 M17 vout9 vout8 0 0 NMOS L=1 W=10 M18 vout9 vout8 vdd vdd PMOS L=1 W=30 M19 vout10 vout9 0 0 NMOS L=1 W=10 M20 vout10 vout9 vdd vdd PMOS L=1 W=30 M21 vout vout NMOS L=1 W=10 M22 vout vout10 vdd vdd PMOS L=1 W=30.MODEL NMOS NMOS LEVEL = 3.MODEL PMOS PMOS LEVEL = 3.end
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