1. Introduction. 2. Coarse-Grain MTCMOS Layout

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1 Coarse-Gra MTCMOS Sleep Trassor Szg Usg Delay Budgeg Ehsa Pabaza ad Massoud Pedram Uversy of Souher Calfora {pabaz, Absrac Power gag s oe of he mos effecve echques reducg he sadby leaage curre of VLS crcus. hs paper we roduce a ew approach for sleep rassor szg whch mmzes he oal sleep rassor wdh for a coarse-gra mul-hreshold CMOS crcu assumg a gve sadard cell ad sleep rassor placeme. Frs, he crcu s decomposed o a se of modules, each coag he se of logc cells ha are closes o a sleep rassor cell. Nex gve a upper boud o he overall crcu speed degradao, he global mg slac s dsrbued amog dffere clusers usg a delay-budgeg. The slac dsrbuo resul s he used o sze he sleep rassors such ha he oal sleep rassor wdh s mmzed whle accoug for he parasc ressaces of he vrual groud e. esuls show ha he proposed szg algorhm produces sleep rassor szes ha are 40% smaller ha hose produced by prevous approaches. 1. roduco Mul-hreshold CMOS (MTCMOS echology provdes low leaage ad hgh performace operao by ulzg hgh speed, low V rassors for logc cells ad low leaage, hgh V devces as sleep rassors. Sleep rassors dscoec logc cells from he power supply ad/or groud o reduce he leaage he sleep mode. There s a performace degradao assocaed wh he sleep rassor sero. Ths s due o he -drop across he MTCMOS cells he acve mode of operao. For a fxed placeme, he amou of he performace degradao depeds o he sze of he MTCMOS swch cells. The larger he sleep rassors are, he lower he performace degradao s. However, he amou of he power cosumpo wll crease wh he sze of he sleep rassors. Therefore, here s a rade-off bewee he amou of he performace degradao ad he power cosumpo of he sleep rassors a MTCMOS crcu. Ths maes MTCMOS cell szg oe of he mos mpora ssues he coarse-gra MTCMOS desg flows. some applcaos performace s oo crcal ad he desger cao afford ay performace degradao due o MTCMOS. [1] auhors propose o separae mg crcal sadard cells from he o-crcal oes by placg hem dffere rows ad by dog he power gag oly for he o-crcal sadard cell rows. They have show ha a hgh leaage savg ca be acheved whle losg a small amou of performace. hs paper, we assume ha MTCMOS s appled o all sadard cell rows. Furhermore, o ral sharg s assumed for he eghbor rows. There have bee several wors addressg sleep rassor szg for MTCMOS crcus [2]-[8]. [3] cells sde he crcu are clusered such ha her swchg curre profles are muually exclusve. [4] cells he crcu are clusered usg b-pacg or se parog o reduce oal sleep rassor wdh. [5] vrual ral roug s employed o use a dsrbued sleep rassor ewor (DSTN order o reduce he oal sleep rassor sze. [6] ad [7], he auhors propose algorhms o calculae he drop volages a dsrbued sleep rassor ewor ad use ha szg he sleep rassors. Mos of he cluserg-based sleep rassor szg algorhms, propose specal ype of crcu cluserg o reduce he oal sleep rassor wdh. order o mpleme hese approaches, logc cells sde he same cluser eed o be placed close ogeher; however, sce mos of he sae of he ar dusral flows use mg-drve placeme, MTCMOS crcu cluserg wll resul performace degradao. O he oher had DSTN-based sleep rassor szg approaches do o use he oal avalable slac opmally. Therefore, hey ed o oversze he sleep rassors [5]-[7]. hs paper, we prese a delaybudgeg algorhm o sze he sleep rassors a crcu. We assume ha he placeme of he logc cells ad sleep rassor cells are ow ad gve. We he propose a delay-budgeg algorhm o opmally use he oal avalable slac ad sze he sleep rassors opmally. The remader of hs paper s orgazed as follows. Seco 2 als abou he coarse-gra MTCMOS layou syle. Seco 3 descrbes he proposed szg algorhm whle seco 4 shows he resuls obaed by applyg he szg algorhm. Seco 5 cocludes he paper. 2. Coarse-Gra MTCMOS Layou Fgure 1 shows a ypcal sadard cell row a coarse-gra MTCMOS desg whch comprses of sadard cells ad a MTCMOS sleep rassor (whch s also cluded he cell lbrary as a sadard cell. There are wo ypes of coarsegra MTCMOS swches: headers ad fooers. A fooer cell bascally cosss of a NMOS sleep rassor whch s used o dscoec he rue V SS (TV SS e from he vrual V SS (VV SS ral. A header cell, however, cosss of a PMOS sleep rassor used o dscoec he rue V DD (TV DD e from he vrual V DD (VV DD ral. From here o wherever we al abou MTCMOS swch cells, or sleep rassors, fooer cells are eded. Dscussos abou fooer cells, wh obvous modfcaos, are also applcable o header cells. SLEEPB TV SS VDD VV SS Fgure 1: Poro of a ypcal cell row a coarse-gra MTCMOS crcu, also showg a sleep rassor.

2 To mae he coarse-gra MTCMOS flow beer adaped o he ASC desg flow, MTCMOS swch cells have o be reaed as regular sadard cells by he CAD ools. Ths requres hese cells o be desged smlar o he regular sadard cells. More precsely, all he MTCMOS swch cells have o clude power ad groud rals ha are alged wh he correspodg rals of oher sadard cells. addo, he swch cells mus also have he same hegh as ay oher lbrary cell. Fgure 2 shows ypcal layou of coarse-gra header ad fooer cells. ca be see from he fgure ha boh header ad fooer cells have separae V SS ad V DD rals smlar o all he oher sadard cells. SLEEP V DD TV DD V SS SLEEPB V DD TV SS V SS Fgure 2: Typcal layou syles of coarse-gra MTCMOS swches: (lef header, (rgh fooer. The V DD ral he fooer cell s o coeced o ayhg sde he cell; coras, he V SS ral s coeced o he TV SS p hrough a NMOS rassor. The V SS ral of each fooer cell wll be coeced o he V SS ral of he row ha hs fooer cell belogs o. The TV SS p, o he oher had, wll be coeced o he rue groud mesh whch wll be roued a separae meal layer, e.g., M4. Therefore, he V SS ral (V SS e of he fooer cell becomes par of he VV SS e of he cell row afer he fooer cell s sered o he row. Each MTCMOS swch cell coas a pu p ad a oupu p whch are used for cell characerzao. The pu ps for he header ad fooer cells are SLEEP ad SLEEPB (SLEEP, respecvely. These ps are he corol ps o ur he swch ON ad OFF. The oupu of he fooer cell s V SS, whle he pu s he TV SS. MTCMOS swch cells ca be placed may dffere fashos amog he cells a crcu. Fgure 3 shows he colum-alged sleep rassor placeme syle. Module 1 of row 1 Module 2 of row 1 row ad o have hem alged vercally oe uder he oher as we raverse dffere cell rows. The swch cell placeme problem may be formulaed ad solved as a opmzao problem by self; however, we assume here ha he placeme of he logc ad MTCMOS swch cells s fxed ad gve. We prese a algorhm o opmally sze he sleep rassors for he gve placeme. 3. Sleep Trassor Szg wh Delay Budgeg The oo of a module assocaed wh each sleep rassor s explaed wh he help of Fgure 3. A module s defed based o he exsg cell placeme ad he locao of he TV SS les (or aleravely, he sleep rassor cell ha les udereah hs le over he sadard cell layou. parcular, module (r, deoes he module ha s formed aroud he h sleep rassor he r h row of he sadard cell layou. The cells belogg o hs module are hose ha are he r h row ad are close dsace o he h sleep rassor ha row. We gore he VV SS ral ressace bewee he cells sde each such module. The VV SS odes of dffere modules are coeced hrough he VV SS ral, whose ressace s ae o accou by cosderg a ressor bewee he VV SS odes of wo adjace modules as show Fgure 4 by ad r. hs fgure, ( ad M ( r, s( r, r VSS ( r, 1 V SS ( r, ( deoe, respecvely, he dschargg curre of module M (r, ad he curre flowg hrough he sleep rassor correspodg o hs module as a fuco of me. Noe for he res of hs paper, each row s cosdered separaely from he oher rows he crcu; herefore, he dex r ca be elmaed for smplcy. For example, M represes he h module of a ypcal row he crcu. M (r, -1 M (r, M (r, +1 M (r,-1 W s(r,-1 s (r,-1 r VSS(r,-1 M (r, W s(r, r VSS(r, s (r, M (r,+1 W s(r,+1 s (r,+1 VV SS V DD VV SS TV SS TV SS TV SS Fgure 3: Colum-alged sleep-rassor placeme. The dashed boxes represe MTCMOS swch cells. All he oher sadard cells are assumed o be placed he bla area bewee swch cells. The TV SS mesh les are also show he fgure. They wll be used for roug he TV SS ps varous swch cells. Because of s smple power/groud ewor roug sraegy, s desrable o uformly dsrbue he swch cells o each sadard cell Fgure 4. Sleep rassors, he correspodg modules, ad parasc model of he VV SS ral. Durg he acve operao, sleep rassors wor he lear mode, ad each sleep rassor may be replaced by s equvale lear rego ressor. For he h sleep rassor, of a ypcal row, he value of hs ressor s calculaed as: 1 Ws s = µ ( Cox VDD VH L Curre sae-of-he-ar sleep rassor szg algorhms [6]-[7] mmze he oal sleep rassor wdh subjec o a maxmum volage drop o he vrual ode of each MTCMOS swch cell. hese approaches, he DC ose cosra for he vrual ode of a MTCMOS swch s somehow relaed o he olerable delay crease he crcu.

3 fac, oe of hese approaches al abou selecg he drop cosras opmally. The mos rval way ha s used s o uformly slow dow all he modules whch resuls a sgle drop cosra for all modules. realy, usg a sgle maxmum volage drop value o all vrual odes s over cosrag he problem ad deed avodable. sead, oe would le o se he DC ose cosra for he vrual ode of each MTCMOS swch based o he mmum olerable delay crease (.e., he posve mg slac for ay logc cell he correspodg module. The volage drop allocao o he vrual odes of he MTCMOS swches should hus be closely relaed o he mg slac allocao o dvdual cells he crcu. he ex seco, we provde a example o show ha for a specfed maxmum delay pealy for he whole crcu, he maer whch he posve mg slac s dsrbued amog dffere modules he crcu grealy affecs he sleep rassor szg soluo. Solvg hs delay budgeg problem ad combg wh sleep rassor szg s precsely he corbuo of he prese paper Bacgroud ad Movaoal Example Cosder a logc cell locaed he h module, M, of a ypcal row of a CMOS crcu. Le d deoe he 50% propagao delay of hs cell. To a frs order, we have: CV L DD d ( VDD VL α (1 where C L deoes he load capacace of hs cell, V L s he hreshold volage of low-v devces he cell, ad α s he velocy saurao dex, whch models he shor chael effec [9]. Suppose hs cell s placed module M he MTCMOS crcu. Le d deoe he propagao delay of hs cell he MTCMOS crcu. Aga we have: CV L DD d ( VDD v VL α (2 where v s he volage of he VV SS ode assocaed wh module M, he module ha hs cell belogs o. Usg Taylor seres expaso, he delay crease s calculaed as [8]: v d = d d d (3 VDD VL ca be see ha he degree of he delay degradao rao (DD,.e., d/d, for each cell s drecly proporoal o he volage drop a he VV SS ode of he module ha hs cell belogs o. order o acheve a fxed gve DD value for a crcu, s eough o have a se of cosras guaraeeg ha oe of he v volages exceed a fxed volage value, V -max. Ths s he approach ha mos of he coveoal mehods use o oba he volage drop cosras for dffere modules. We show ha he volage drop cosras obaed usg hs approach are o he opmal values. The bes way o expla hs observao s wh he ad of a example. Cosder he crcu show Fgure 5. The crcu cosss of four verers ad wo sleep rassors modeled as ressors he fgure. Each verer drves a FO4 load. We dvde hs crcu o wo modules, M 1 ad M 2. Module M 1 comprses of he frs wo verers,.e., verers wh sze 1 ad 4 whle module M 2 cosss of he las wo verers,.e., verers wh sze 16 ad 64. V N V A V OUT C L =FO4 Fgure 5. A verer cha wh four verers ad wo modules. Sleep rassors are replaced by ressors. Oe sleep rassor s used per module he MTCMOS crcu. Whe 1 = 2 =0, usg a 65m CMOS process echology dec, he oal V N -V OUT low-o-low propagao delay s 103ps. Table 1 shows he propagao delay share ad he pea dscharge curre value for each module he ormal operao mode (as opposed o he sleep mode. Table 1. Propagao delay ad pea curre values for he wo modules of Fgure 5. Module Module Delay (pco sec Module Pea Curre (ma M M We assume ha afer serg sleep rassors a maxmum DD of 10% s accepable, whch gves us a oal posve mg slac of 10.3ps. Ths slac ca be dsrbued bewee he wo modules may dffere ways. Depedg o how hs slac s dsrbued bewee he wo modules, dffere maxmum volage drop cosras ad dffere oal sleep rassor wdhs are obaed. Table 2 shows some of hese choces. ca be see ha how precsely he oal slac s dsrbued bewee he wo modules wll have a large mpac o he oal sleep rassor sze (whch s proporoal o summao of verse ressace values. Table 2. Toal sleep rassor coducace as a fuco of he mg slac dsrbuo for wo modules. Module Toal Sleep Tx -1 Crcu Delay Delay essace (Ω -1 (ps (ps (Ω T CMOS M1 = =0 T M2 =57 2 =0 T M1 = = T M2 = =9 T M1 = =330 MTCMOS T M2 = =2 T M1 = = T M2 = =25 The frs row he MTCMOS seco he able correspods o he uformly dsrbued slac bewee boh modules,.e., -1 boh modules have he same DD of 10%. hs case value s Ω -1. The secod row he MTCMOS seco correspods o he case whe mos of he oal avalable slac (approxmaely 80% s gve o M 1 ad he res (20% s gve o M 2. hs case -1 value s Ω -1 whch s much more ha he frs case. Fally he hrd row he MTCMOS seco correspods o he case whe oly 20% of he oal avalable slac s gve o M 1, ad mos of he oal

4 avalable slac s reserved for M 2. Ths case resuls he mmum -1 value, whch s Ω -1. Ths example clearly shows ha slowg dow all he modules a crcu uformly,.e., wh he same DD, wll o resul he mmum oal sleep rassor wdh soluo. The problem saeme has o be formulaed such a way ha he oal avalable slac due o he maxmum allowed DD s dsrbued amog dffere modules opmally whle beg aware of he dscharge curre of dffere modules. uvely, we should slow dow modules wh large amou of dschargg curre more ha he oes wh smaller amou of dschargg curre, curre-aware opmzao. hs paper we frs formulae he sleep rassor szg problem as a delay-budgeg problem. The we prese a curre-aware szg algorhm o fd he opmum soluo Problem Formulao Cosder a combaoal crcu. The mg cosras for he crcu are gve as a pu arrval me A for each prmary pu P, ad as a requred arrval me a each prmary oupu PO. We le a ad r deoe he oupu arrval ad requred mes of cell C ad d deoe he propagao delay of hs cell. Kowg he prmary pu arrval mes, we ca calculae arrval me a he oupu of each cell as he summao of he maxmum pu arrval mes of he cell ad he cell propagao delay. Smlarly, requred me ca be calculaed owg he requred me for he prmary oupus ad he propagao delays of dffere cells he crcu. The slac a each ode s: s = r a (4 Afer serg he MTCMOS cells ad mposg he ew requred mes for he prmary oupus, all he arrval ad requred mes for dffere odes he crcu wll chage. We show arrval me, requred me ad slac for he oupu of C he MTCMOS crcu by a,, r s, respecvely. Thus: s = r a (5 The propagao delay of each cell wll also chage. We show delay of C he MTCMOS crcu by d where: d = d + d (6 Now suppose C s placed module M he MTCMOS crcu. From (3 we have: d = δ dwhere: v δ = (7 VDD VL The arrval me for C he MTCMOS crcu, a, s: { } = max + fas of C a a d (8 From (6 ad (7, he arrval mes he MTCMOS crcu ca be calculaed erms of he VV SS ode volages of dffere modules he MTCMOS crcu. Thus, arrval mes he MTCMOS crcu, a s, ca be wre erms of v s. equred me of he oupu of C MTCMOS crcu s: r = m{ } rfaous of C d (9 The delay-budgeg cosras ca be wre as follows: s = r a 0; 1 CELL_NUM (10 Where a ad r are calculaed from (8 ad (9 whle CELL_NUM deoes he oal umber of he cells (odes he crcu. Sce he propagao delay values for each cell he MTCMOS case are o ow ad hey deped o he v values of dffere modules, ad sce (8 ad (9 clude max{.} ad m{.} operaos, he complexy of opmzg a objecve fuco o he doma defed by hese cosras s hgh. To smplfy he problem, we may cosder oly he crcal mg pahs whe formulag he problem cosras,.e., we ge rd of he m ad max operaors (8 ad (9. However, he poeal weaess of hs approach s ha he crcal pahs he CMOS crcu are o ecessarly he crcal pahs he MTCMOS crcu [2]. Foruaely, hs dffculy ca be addressed by ag o accou he K mos crcal pahs he CMOS crcu o buld he se of cosras for he opmzao problem. The delay degradao of a gve pah π he crcu due o applyg power gag ca be wre as he summao of he delay degradaos of all he cells ha pah. The delay degradao for ay cell C he crcu ca be calculaed from (3 assumg ha C belogs o M. Noe as far as delay degradao of C s cocered, v (3, or (7, ca be calculaed erms of as follows: max C C, m max Where s flowg hrough max C C m, max = s s v (11 s he maxmum value of he curre durg he me wdow ha cell C s swchg,.e., [ C m, C max]. The delay degradao of a gve pah π ca be calculaed usg (6, (7 ad (11 [8]: C π C π max C C m, max s θ( C sθ ( C dπ = d = d V V DD L (12 where he summao s ae over all cells pah π. C represes a cell π, ad θ(c s he dex of he module ha cell C belogs o; e.g., f C s M, he θ(c =. Based o wha we have dscussed so far, he delay-budgeg based szg problem ca be formulaed as follows: Mmze M = 1 1 s s.. : 1. dπ DD_MAX; 1 K 2. s ( VVSS_MAX; 1,1 s M j N where: C C max m, max s s dπ = d ; 1,1 K j N C V π DD VL, j: s ( 0 j = s ( 0 ad N 1 j = + s ( ( ( ( 1 s 1 j s 1 s 1 j s s s s + + s ( ( = M + + r r r r VSS 1 VSS VSS 1 VSS Fgure 6. Delay-budgeg based sleep rassor szg problem.

5 Fgure 6, he cloc cycle s dvded o N equal me ervals ad j deoes he begg me of he j h erval. M ( s he swchg curre of module M a me j. These equaos mplcly cosruc he maxmum curre waveform hrough each sleep rassor a N mg saces a cloc cycle whle cosderg he mg wdows durg whch a logc cell ca chage s oupu value. The equao correspodg o s ( calculao Fgure 6 s obaed by wrg he KCL equaos for dffere odes of he VV SS ral,.e., hs equao accous for dffere curre flow pahs he vrual groud e hrough adjace sleep rassors. The frs se of he cosras are he crcal pah cosras, whle he secod se of cosras capure he maxmum allowed volage drop o he VV SS ral Algorhm hs seco we descrbe a curre-aware szg algorhm (c.f. Seco 3.1 whch solves he sleep rassor szg problem preseed 3.2. We ca show ha he frs se of he cosras Fgure 6 ca be wre as a se of lear equaos erms of varables,, as follows: M as DD_MAX; 1 K (13 = 1 where a s 0 f module does o le o he h crcal pah; oherwse, s calculaed by collecg all he coeffces correspodg o d π. Defo 1: A ay gve sep of he szg algorhm, he mos crcal module (MCM s he module wh he maxmum delay corbuo o he K mos crcal pahs,.e., MCM = arg max a (14 M K = 1 Defo 2: A ay sep of he algorhm he bes caddae module (BCM s defed as he module whose sleep rassor upszg by a cera perceage wll resul he larges delay mproveme for usasfed pahs. Lemma 1: BCM s he MCM over he pahs ha do o mee he delay cosra,.e.: s ({ π 1, DD_MAX } BCM = MCM K d π > (15 Proofs are sragh-forward ad omed for brevy. Noe ha BCM s o uque ad here ca exs more ha oe BCM a ay sep of he algorhm. Defo 3: Leas-cos BCM (LBCM s defed as he BCM whose sleep rassor upszg wll resul he mmum crease he objecve fuco Fgure 6. f here s oly oe BCM, he we have LBCM=BCM. Lemma 2: LBCM ca be foud as: K a M = BCM = 1 dπ > DD_MAX LBCM = arg m (16 Lemma 2 maes he szg algorhm be aware of he dschargg curre of he module (curre-aware algorhm. From he dscusso preseed above, we propose he followg sleep rassor szg algorhm. A he begg we use a algorhm smlar o he oe preseed [7], Slp_alze, order o sasfy he secod se of he cosras Fgure 6 (.e., he vrual groud volage upper boud. The resuled values wll ypcally be oo large o mee he frs se of cosras Fgure 6 (.e., he mg cosras. They are hus fed o he ma sleep rassor szg algorhm, Slp_Szg, whch wll eravely sze up he sleep rassors ul all he mg cosras are me. Algorhm: Slp_alze( M, VVSS_MAX 1: /*alzg varables*/ 2: for =1 o M do 3: s = ; MAX 4: ed for 5: calculae s ( ad v ( j = s ( s for all, j ; 6: whle (v ( j > VVSS_MAX for some or j do 7: M m =FdMModule{VVSS_MAX - v ( j }; 8: s = VVSS _ MAX ( m s for all j; m j 9: updae s ( ad v ( j = s ( s for all, j; 10: ed whle 11: reur for all ; Fgure 7. alzg opmzao varables ad sasfyg he secod se of cosras. A each erao sep, he Slp_Szg algorhm checs f all he cosras are sasfed. f here s ay usasfed cosra, he algorhm searches for he LBCM ad reduces he correspodg ressace value by α%, ad updaes s ( ad v ( j values, ad passes hem o he ex erao. Slp_Szg algorhm sops whe all he cosras are sasfed. Ths algorhm s descrbed deal Fgure 8. Algorhm: Slp_Szg( s-al, M, VVSS_MAX 1: calculae s ( ad v ( j = s ( al s for all, j ; 2: whle (m_slac < 0 3: fd LBCM ad m=lbcm; 4: s = m s α ; m sm 5: updae s ( ad v ( j = s ( s for all, j; 6: m_slac = ; 7: for =1 o K, j=1 o N 8: f ( d π DD_MAX< m_slac 9: m_slac = d π DD_MAX; 10: ed f 11: ed for 12: ed whle 13: reur( for all ; Fgure 8. Curre-aware sleep rassor szg algorhm by delay budgeg. 4. esuls SCAS-85 bechmar crcus have bee used hs paper. We use SS o geerae opmzed gae level elss. All he bechmar crcus are frs opmzed usg scrp.rugged SS. We use a 65m echology lbrary o perform mg-

6 drve echology mappg. Oupu formao of SS s passed o our szg algorhm wre MATLAB. Placeme of he sleep rassors s fxed, ad we use colum-based placeme descrbed seco 2. A maxmum DD of 10% has bee used he smulaos (DD_MAX=10%. The ral ressace bewee each par of module s assumed o be 0.1 VSS r = Ω for all values. The maxmum umber of he crcal pahs cosdered hs paper, K Fgure 8, s 100, ad α = 0.1 Fgure 8. order o esmae dschargg curre for each module, we use recagular curre model used [8]. Table 3 shows he oal sleep rassor wdh us of λ for he SCAS-85 bechmar crcus where λ s he mmum feaure sze, 32.5m hs paper. We have also compared he resuls of our delay-budgeg algorhm wh he proposed algorhm [6] ad TP algorhm [7]. Table 3 also shows resuls for hese wo algorhms, ad he savg ha s acheved by he delay-budgeg algorhm compared o hese wo approaches. Table 3. Toal sleep rassor sze us of λ. DD_MAX=10%, K=100, α=0.1. Toal sleep # of Fooers TX wdh (λ Crcu # of cells [6] C sym C C C C C Avg. 2.0 Toal sleep TX wdh (λ Proposed Proposed TP [7] Proposed vs. [6] (% vs. [7] (% order o compare he resuls of he proposed delaybudgeg algorhm wh he TP algorhm [7], we mplemeed he TP algorhm. our mplemeao of hs algorhm, we pced he fxed drop cosras for all he modules such ha all he modules would slow dow by 10%. However, he proposed delay-budgeg algorhm dsrbues he gve 10% slac opmally amog he modules ad acheves smaller oal sleep rassor wdh. order o approxmae he resuls of he algorhm proposed [6], we used he oal sleep rassor wdh obaed from our mplemeao of [7] ad esmae he oal sleep rassor wdh [6] usg he daa gve Table 1 of [7]. As s see from he able, he proposed approach saves more ha 40% of he oal sleep rassor area compared o [6] ad [7]. 5. Coclusos We roduced a ew approach for mmzg he oal sleep rassor wdh for a coarse-gra MTCMOS crcu assumg a gve sadard cell ad sleep rassor placeme. Our algorhm aes a maxmum allowed crcu slowdow facor ad produces he szes of varous sleep rassors he sadard cell layou whle cosderg he DC parascs of he vrual groud e. We showed ha he problem ca be formulaed as a szg wh delay budgeg problem ad solved effcely usg a heursc szg algorhm whch mplcly performs maxmum curre calculao hrough sleep rassors whle accoug for dffere curre flow pahs he vrual groud e hrough adjace sleep rassors. Ths echque uses a leas 40% less oal sleep rassor wdh compared o oher approaches. Acowledgeme - Ths research was suppored par by he Naoal Scece Foudao uder gra o The auhors would le o ha he sraegc echology group LS Corporao for her valuable dscussos ad commes. efereces [1] A.Sahaur, A.Pull, L.Be, A.Mac, E.Mac, M.Poco, Tmg-drve row-based power gag, Proc. l Symp. o Low Power Elecrocs ad Desg, pp , [2] J. Kao, A. Chadraasa, ad D. Aoads, Trassor szg ssues ad ool for mul hreshold CMOS echology, Proc. Desg Auomao Coferece, pp , [3] J. Kao, S. Nareda ad A. Chadraasa, MTCMOS herarchcal szg based o muual exclusve dscharge paers, Proc. Desg Auomao Coferece, pp , [4] Mohab As, S. Areb, ad M. Elmasry, Desg ad opmzao of mulhreshold CMOS (MTCMOS crcus, EEE Tras. o CAD of egraed Crcus ad Sysems, pp , Ocober [5] C. Log, L. He, Dsrbued sleep rassor ewor for power reduco, EEE Tras. o VLS Sysems, Volume: 12, No. 9, pp , Sepember [6] D. S. Chou, S. H. Che, S. C. Chag, ad C. Yeh, Tmg drve power gag, Proc. of he Desg Auomao Coferece, pp , [7] D. S. Chou, D. Jua, Y. Che, ad S. Chag, Fe-graed sleep rassor szg algorhm for leaage power mmzao, Proc. Desg Auomao Coferece, pp , [8] A. amalgam, B. Zhag, A. Devga ad D. Pa, Sleep rassor szg usg mg crcaly ad emporal curres, Proc. Asa Souh Pacfc Desg Auomao Coferece, pp , [9] T. Saura ad A. Newo, Alpha-power law MOSFET model ad s applcaos o CMOS verer delay ad oher formulas, EEE J. Sold-Sae Crcus, vol. 25, pp , Apr