ECEN 4827/5827 Supplementary Notes. 1. Review: Active Devices in Microelectronic Circuits

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1 ECEN 4827/5827 Supplementary Notes 1. eiew: Actie Deices in Microelectronic Circuits c 2005 Dragan Maksimoić Department of Electrical and Computer Engineering Uniersity of Colorado, Boulder The purpose of this part of the notes is to briefly reiew some of the prerequisite course materials related to characteristics of actie deice in microelectronic circuits. We summarize dc, largesignal and smallsignal (incremental) models of two major types of actie deices used in analog, digital and mixedmode integrated circuits: metaloxidesemiconductor fieldeffect transistors (MOSFET), and bipolar junction transistors (BJT). Seeral examples are used to illustrate approaches to analysis of DC, and AC (smallsignal) properties of electronic circuits at the deice leel. 1

2 D D D i D NMOS PMOS G G S (a) S D B B G G S (b) S D G DS GS S (c) S SG G SD i D D G G (d) Figure 1: Symbols currently in use for enhancementmode MOS transistors: (a) symbols of MOS transistor as 4terminal deices; (b) symbols of MOS transistors with the substrate (B)shorted to the source (S) terminal; (c) symbols of MOS transistors with implied (default) connections of the substrate (B) terminal; (d) symbols commonly used in digital circuits where source (S) and drain (D) terminals are not specified. 1 Metaloxidesemiconductor fieldeffect transistor (MOSFET) Prior to reading this section, it is useful to reiew suggested reference textbooks on CMOS technology, and physics of nchannle (NMOS) and pchannel (PMOS) deices. Various symbols for enhancementmode NMOS and PMOS deices are shown in Fig. 1. On an integrated circuit, MOS transistor is a 4terminal deice, as indicated by the symbol in Fig. 1(a). In a standard, psubstrate CMOS technology, an nchannel (NMOS) deice is built on a ptype substrate (B terminal). The ntype source (S) and drain (D) regions are the deice output terminals. The gate (G) is isolated from the substrate by a thin layer of oxide. A pchannel (PMOS) deice is built with ptype source and drain regions in an nwell, which seres as an ntype substrate (B), Depending on the oltage applied between the gate (G) and source (S) terminals, a conducting channel can be established between the drain (D) and the source (S). If the substrate terminal (B) is shorted to the source (S) terminal, the MOS transistor can be considered a 3terminal deice, and the symbols in Fig. 1(b) are in use. If the substrate terminal (B) is connected to a default oltage rail (negatie supply rail for psubstrate, positie supply rail for nwells), the MOS transistor can be considered a 3terminal deice, and the symbols in Fig. 1(c) are in use. Finally, in digital CMOS circuits, where the distinction between the source (S) and drain (D) terminals is not important, the symbols in Fig. 1(d) are commonly used. 1.1 Dc characteristics and operating modes (i.e. operating regions) Typical DC outputplane i D ( DS ) characteristics for an NMOS deice are shown in Fig. 2. These characteristics are obtained by PSpice simulation of the circuit shown in Fig. 2. 2

3 15mA MOS output characteristics (2N6782, mos.cir) i_d VGS=5V 10mA VGS=4.5V 3 2 VGS=4V 1 5mA VGS=3.5V 2 GS 0 i D DS 0mA 1 VGS=3V VGS < Vt Vt=2V K=1.5mA/V^2 _DS 2N6782 5mA 1.0V 0.0V 1.0V 2.0V 3.0V 4.0V 5.0V id(m1) VDS Figure 2: Dc characteristics of an nchannel MOS transistor (2N6782), as obtained by PSpice simulation (mos.cir). Boundary i D = KDS 2 between saturation (region 2) and triode (region 3) modes is also shown. Glossary Threshold oltage: V t For an NMOS deice, gatetosubstrate oltage greater than the threshold V tn = V tp = V t causes formation of an inersion layer of free electrons (conducting channel) in the ptype substrate. The threshold oltage V t is positie for enhancementmode deices in a standard CMOS technology, typically between 0.5V and 1.5V. If the gatetosubstrate oltage at a certain point between source and drain is greater than the threshold oltage, we say that the channel is on at that point. Otherwise, the channel is off. Note that for NMOS deices the threshold oltage V tn is positie, while for PMOS deice the threshold oltage V tp is negatie. A depletionmode NMOS deice has a builtin conducting ntype layer in the p substrate between the drain and the source, so that it takes a negatie gatetosubstrate oltage to turn the channel off. For a depletionmode nchannel MOSFET, V t is negatie, but all other characteristics are the same as for the enhancementmode deices. Conductance parameter: K The conductance parameter K is proportional to the channel width W, inersely proportional to the channel length L, and proportional to the gatetochannel capacitance per unit area C ox, K = W µc ox, (1) L 2 where µ is the carrier mobility (electron mobility µ n for nchannel deices, hole mobility 3

4 GD GD SG NMOS 3 triode GS DG Vt PMOS Vt DG 3 triode 1 Vt 2 GS 1 Vt 2 SG cutoff saturation cutoff saturation Figure 3: Operating modes of an NMOS and a PMOS transistor. µ p for pchannel deices). Summary of dc characteristics For DS > 0 (NMOS deices), or SD > 0 (PMOS deices), the MOSFET can operate in one of the three main operating modes: cutoff, saturation or triode, depending the whether the channel is on or off on the source (S) and the drain (D) ends. Fig. 3 shows the operating modes in the GD s. GS plane for NMOS and PMOS deices. The summary here is for an NMOS deice with V tn = V t > cutoff (region 1 in Fig. 2): GS <V t, GD <V t, the channel is off at both the source (S) and drain (D) ends. Consequently, i D = 0 and the deice is cut off. 2. saturation/actie (region 2 in Fig. 2): GS >V t, GD <V t, the channel is on at the source end, off at the drain end. The drain current is nearly independent of the draintosource oltage. This operating mode is similar to the actie mode for the bipolar transistors. In the saturation/actie mode, the steadystate characteristics of an NMOS transistor are described by: i D = K( GS V t ) 2 (1 DS /V A ) K( GS V t ) 2 (2) The parameter V A is used to model the nonzero slope of the dc characteristics in the saturation region. In many cases, we can assume that V A, i.e., that the drain current i D in the saturation mode is independent of the oltage DS. In saturation, if GS >V t, the drain current has quadratic dependence on the gatetosource oltage GS, as shown in Fig. 4. Because the drain (output) current can be controlled by the gatetosource (input) oltage the MOS transistor can be used to build arious signalamplification circuits. 4

5 15mA MOS i_d(_gs) and gm (2N6782, mosgm.cir) 10mA 5mA ID Q VGS 0A 0V 1.0V 2.0V 3.0V 4.0V 5.0V id(m1) VGS Figure 4: Inputtooutput characteristic i D ( GS ) for the NMOS transistor 2N6782 operating in saturation, as obtained by PSpice simulation (mosgm.cir). The box around the DC operating point Q (V GS,I D ) is blown up in Fig triode (region 3 in Fig. 2): GS >V t, GD >V t, the channel is on at both the source end and the drain end. In the triode mode, i D depends strongly on both GS and DS. The steadystate characteristics are gien by: [ ] i D = K 2( GS V t ) DS DS 2. (3) If DS is much smaller than GS, we hae that GD GS so that the channel is equally on at both the source and the drain ends. As shown in Fig. 2, the i D ( DS ) characteristics close to the origin are close to straight lines. Between the drain and the source, the deice behaes as a linear resistor whose resistance can be changed by the oltage applied to the gate. For an enhancement mode PMOS, V t < 0. The discussion aboe for an NMOS transistor applies to PMOS transistors if GS is replaced by SG, GD is replaced with DG, DS is replaced by SD and V t is replaced by V t = V tp. For example, a PMOS transistor operates in the triode mode if SG > V tp and DG > V tp. In the triode mode, the drain current i D, with the polarity shown in Fig. 1(c), is gien by: [ ] i D = K 2( SG V tp ) SD SD 2. (4) The DC gate current is ery close to zero, and can be neglected for all operating modes because the gate is electrically isolated from the channel by a thin layer of silicon oxide. If DS < 0 (NMOS deices), or SD < 0 (PMOS deices) in a threeterminal MOSFET with the substrate shorted to the source, the substratetodrain junction becomes forward 5

6 biased as soon as DS exceeds seeral tens of a olt. The deice characteristic is ery similar to the characteristic of a PN diode, as shown in the part of the characteristics in Fig. 2 for DS < 0. If the draintosource oltage exceeds a breakdown oltage V DSS, the drain current increases quickly with DS. The excess current or the excess oltage may cause the deice to fail. Circuits are normally designed so that the deice neer enters the breakdown region. 1.2 Smallsignal (incremental) model at low frequencies MOS transistor, as most other semiconductor deices, has a number of operating modes described by nonlinear equations. A common approach to hand analysis of signal processing circuits is to find the DC operating point using deice largesignal characteristics, and then linearize the characteristics around the DC bias operating point in order to examine what happens with signals that ary around the DC bias point. Mathematically, linearization of the deice characteristics amounts to taking a Taylor expansion of the deice nonlinear characteristic at a DC bias operating point and retaining only the first term in the expansion. For example, Fig. 4 shows the nonlinear i D ( GS ) characteristic of an NMOS transistor operating in saturation. Suppose that DC bias oltages and currents at the DC bias operating point Q are V GS, I D and V DS. Assume that the total oltage GS has the dc component V GS and a signal component gs = V GS, As a result, the total drain current i D can also be written as: GS = V GS gs. (5) i D = I D i d, (6) where I D is the DC bias drain current, and i d is the signal component of the drain current. The relation between the signal components i d and gs is approximately linear if the amplitudes of i d and gs are relatiely small, which is why the analysis based on linearization of deice characteristics around a DC operating point is called the smallsignal analysis. In general, to find signal components of all oltages and current in a gien circuit, we use a smallsignal model circuit obtained by remoing the DC bias and replacing all deices with their linearized (incremental) smallsignal models. In this section, we describe deriation of the smallsignal model for a MOS transistor operating in the saturation mode. The same procedure can be followed to find the smallsignal models in other operating modes, or for other deices. Applications of smallsignal deice models are discussed further in Section 4. If the MOS transistor operates in saturation at a DC bias operating point (V DS,I D ), the smallsignal (incremental) model of Fig. 6 is obtained, where the parameters are obtained by taking partial deriaties of Eq. 2 and ealuating the partial deriaties at the DC bias operating point: g m = i D =2K(V GS V t )=2 KI D, (7) GS 6

7 MOS i_d(_gs) and gm (2N6782, mosgm.cir) 5.0mA nonlinear deice characteristic 4.0mA 3.0mA ID DC operating point Q linearized characteristic gm = slope 2.0mA VGS id(m1) 3.2V 3.4V 3.6V 3.8V 4.0V VGS Figure 5: Linearization of the MOS i D ( GS ) characteristic to obtain the transconductance g m. G gs g m gs rds D S S Figure 6: The smallsignal model of the MOS transistor operated in the saturation region. The model is exactly the same for both NMOS and PMOS deices. The parameter g m is called the transconductance and is equal to the slope of the i D ( GS ) characteristic at the DC bias point Q, as shown in Fig. 5, which is a blow up of Fig. 4 around the point Q. Similarly, the incremental output resistance is obtained as: r ds = r o = 1 ( ) 1 id = = V A. (8) g ds DS I D Note that two symbols, r ds or r o are used interchangeably to represent the deice incremental output resistance. Seeral general comments about the deice smallsignal models can be made here: Smallsignal models are linear, which allows all tools of linear system analysis to be applied in order to examine and design signal processing electronic circuits. Circuit characteristics such as gain, output resistance, etc. can be obtained using the smallsignal analysis. 7

8 Parameter(s) in the smallsignal models depend on the location of the DC operating point, i.e. on the DC bias. For example, see how the MOS transconductance or the MOS incremental output resistance depend on the DC bias current I D in Eqs. 7 and 8. To obtain the smallsignal model of a circuit, one first needs to sole for the circuit DC oltages and currents in order to obtain correct parameter alues in the deice smallsignal models. Then, each deice in the circuit is simply replaced by its smallsignal model. The dc oltage sources are shortcircuited, while the dc current sources are opencircuited, because the ariations (signal components) of dc oltages are equal to zero. Signal sources remain in the smallsignal model unaltered, as long as the assumptions of the smallsignal modeling remain alid. Smallsignal modeling inoles linearization, i.e. neglecting all higherorder terms in the Taylor expansion of the actual nonlinear characteristics of the deice. Therefore, all results obtained from a smallsignal circuit model are approximate. The smallsignal model is exact only for infinitely small oltage/current ariations around the DC operating point. How small should the signals around the DC operating point be so that the results obtain from the smallsignal model are sufficiently accurate? The answer depends on what you mean by sufficiently accurate. In the design process, acceptable errors are usually much larger than what one might expect. The deice parameters, to start with, are known only within some tolerances. In practice, smallsignal models are commonly applied een if ariations around the DC operating point are comparable to DC alues at the DC operating point, proided that the deice does not leae the operating mode where the model is deried. For example, the smallsignal MOSFET model cannot be applied if the GS oltage ariation takes the deice from saturation to cutoff or triode, because the deice characteristics change dramatically from one mode to another. As long as the MOSFET stays in the saturation mode, the results obtained from the smallsignal model deried for the saturation mode are meaningful. Once a hand design is completed based on approximate models, tools such as computer simulation and prototyping are aailable for final performance erification. 2 Bipolar junction transistor (BJT) Before reading this section, it is a good idea to reiew the bipolar junction transistor IC technology and physics of BJT s from any of the suggested reference textbooks. 2.1 Dc characteristics and operating modes/regions The BJT symbols for the npn and the pnp deices are shown in Fig. 7. Typical dc characteristics for the npn deice are shown in Fig. 8. The characteristics are shown in the output plane, I C s. V CE, for a range of base currents I B. Glossary forward current gain: β = i C /i B 8

9 i C C i B B CE BE E NPN E EB i EC B B C i C PNP Figure 7: Symbols for the NPN and PNP bipolar junction transistors. 10mA BJT output characteristics (2N3904, bjt.cir) IC IB=50uA 8mA IB=40uA 6mA IB=30uA 4mA 3 2 IB=20uA i C ib BE CE 2mA 0mA VCES 1 IB=10uA IB=0 VCE 1.0V 0V 1.0V 2.0V 3.0V 4.0V 5.0V ic(q1) ce Figure 8: Dc characteristics of an npn bipolar transistor (2N3904), as obtained by PSpice simulation (bjt.cir). 9

10 For integrated npn transistors at room temperature, in a standard bipolar technology, the current gain β in the actie mode is typically between 100 and 300. The range of dc collector currents where the current gain has the highest alue is between about 10µA and1maforadeicewith5µm 2 emitter area. A larger deice can be designed to maintain the high current gain at higher collector currents. The current gain increases with temperature. (common base) current gain: α = i C /i E, Since α = β β1,andβ 1, α 1 in the actie mode. saturation oltage: V CES When the BJT operates in saturation (region 3 in Fig. 8), the dc characteristics are steep, and the oltage between the collector C and the emitter E is nearly constant. In a simplified DC model for the saturation mode, CE V CES 0.2V is assumed constant. Early oltage: V A This is the parameter that quantifies the finite slope of the transistor characteristics in the actie mode (region 2 in Fig. 8). V A is V for npn deices in a standard bipolar process. Breakdown oltage: BV CEO Collectortoemitter oltage equal to or higher than BV CEO causes breakdown of the deice and results in a steep increase in the collector current (not shown in Fig. 8). The breakdown oltage is 50V for a standard bipolar process. There is a ariety of bipolar processes with different breakdown oltages. Summary of BJT dc characteristics For the purpose of hand analysis, it is appropriate to identify the distinct operating modes and the corresponding simplified models of bipolar transistors. For CE > 0 (for npn), ( EC > 0 (for pnp)), the bipolar transistor can operate in one of the three main operating modes, as shown in Figs. 8 and 9: 1. cutoff (region 1 in Fig. 8): both the BE junction and the BC junction are reersebiased (off); 2. actie region (region 2 in Fig. 8): the BE junction is forwardbiased, and the BC junction is reersebiased. If a BJT operates in the actie mode, its characteristics are described by: ( i C = I CO (e BE/V T 1) 1 ) CE, (9) V A ( i C = βi B 1 ) CE. (10) V A 10

11 BC BE NPN BC 3 saturation EB CB PNP CB 3 saturation 1 BE EB cutoff actie cutoff actie Figure 9: Operating modes of an NPN and a PNP bipolar transistor. The characteristics in the actie mode can be approximated by: i C = I CO e BE/V T, (11) i C = βi B. (12) Since the BE junction is forward biased in the actie mode, the basetoemitter oltage can be found using one of the following two approximations: (a) (accurate, but nonlinear:) BE V T ln(i C /I CO ), or (b) (simple:) BE V BE =0.7V. 3. saturation (region 3 in Fig. 8): both the BE junction and the BC junction are forwardbiased. If a BJT operates in saturation, V CE V CES, (13) i C <βi B. (14) In the summary of BJT dc characteristics, eerything holds for pnp transistors, except that reference polarities of the deice oltages and currents are reersed, as indicated in Figs. 7 and Smallsignal (incremental) model at low frequencies If the BJT operates in the actie mode, at a DC operating point (V CE,I C ), the smallsignal (incremental) model is shown in Fig. 10. The parameters in the model depend on the DC bias operating point as follows: g m = i C BE = I C V T, (15) 11

12 B C be r pi g m be rce E E Figure 10: Smallsignal model of the BJT operating in the actie mode. r π = 1 g be = BE i B = BE i C r ce = 1 g ce = CE i C i C = β, (16) i B g m = V A I C. (17) The partial deriaties are ealuated at the dc operating point (V CE,I C ). 3 Operating modes: the key to soling microelectronic circuits at DC An essential component of electronic circuit design is to ensure that all deices operate in the operating modes best suited for the application. For example, transistors in amplifier stages are usually biased to operate in the actie mode (BJTs) and saturation (MOSFETs). Deices in logic gates are usually forced to operate in either cutoff (fully off) region or fully on (saturation for BJTs, triode for FETs). Because the deice characteristics are so much different depending on the operating mode, the first step in understanding any electronic circuit at the deice leel is to determine the deice operating modes and the corresponding DC bias solution. A summary of largesignal DC characteristics can be found in Section 1.1 for MOSFETs, and Section 2.1 for bipolar transistors. Finding correct operating modes is discussed in this section with reference to seeral examples of circuits with bipolar transistors. These examples are taken from actual circuit diagrams of more complicated integrated circuits. In the examples of Fig. 11, the objectie is to determine the operating modes of all transistors and to find the DC bias solution. We assume that all deices hae identical characteristics, that V CC >> V BE, V BE > V CES,andβ>>1. The solutions are as follows: a) The BE junction is forward biased from V CC through. Therefore, V B = V BE and I B = (V CC V BE )/. The deice Q is either in the actie mode or in saturation. Assume that the deice is in saturation. Then, V C = V CES, but this is impossible because V C = V CC. Therefore, Q is in the actie mode and I C = βi B. b) The EB junction is shorted by the resistor, and therefore reerse biased. I B =0,and V B = V CC. The CB junction is therefore reersebiased by V CC,andQ is cutoff, I C =0. c) As in a), V B = V BE and I B =(V CC V BE )/. Again Q is in the actie mode or saturated. Assume that Q is saturated. Then, V C = V CES,andI C =(V CC V CES )/. 12

13 VCC VCC VCC IB VB VC Q IC VB Q IC IB VC Q IC (a) (b) (c) VCC I Q1 VCC 2(IB) Q2 VC2 IC2 I Q1 VCC L IC2 VC2 Q2 I Q1 Q2 IC2 VC2=VC4 L 1 Q3 Q4 (d) (e) 1 (f) Figure 11: Examples of finding correct operating modes of bipolar transistors. 13

14 Since I C = V CC V CES <β V CC V BE = βi B, (18) the deice is indeed saturated, i.e., the initial assumption has been erified. d) The CB junction of Q 1 is shorted and the EB junction of Q 1 is forward biased from V CC through. Therefore, Q 1 is in the actie region. The deice with the base shorted to the collector is said to be diode connected. It behaes as a twoterminal pn diode. The EB junction of Q 2 is forward biased by exactly the same oltage as the EB junction of Q 1. Therefore, I B1 = I B2 = I B,andQ 2 is either in the actie mode or in saturation. The current I is gien by I = V CC V BE = I C1 2I B. (19) So, we can sole for the collector current of Q 1, I C1 = I 12/β I. (20) If Q 2 is actie, I C2 = βi B = I C1 I, and the oltage across the load L is L I C2 L I. As long as the deice is actie, the load current is constant and set by I, for any alue of the load resistance L. This is why the configuration (d), known as the current mirror is frequently used in integrated circuits as a current source. The condition for Q 2 to operate in the actie mode is that the CB junction of Q 2 is reerse biased, which is the case for V C2 up to V CC V CES. So, the current mirror operates as a current source for load resistances up to: L < Lmax = V CC V CES I (21) For L > Lmax, Q 2 is saturated, and I C2 =(V CC V CES )/ L is less than I. e) This is the current mirror with npn transistors. We hae exactly the same conclusions as in d), except that I C2 <I because the oltage drop across 1 in the emitter of Q 2 reduces the BE forwardbias oltage BE2 with respect to BE1. To sole for I we can still apply the approximation BE V BE =0.7V, I = V CC V BE, (22) but to sole for I C2, this approximation is inadequate because it would imply that I C2 = 0. Instead, since the solution depends on the difference between two forwardbiased BE junctions, we need to use a more accurate exponential description of the deice characteristic. From: BE1 = BE2 1 I C2 (23) we hae V T ln I I CO = V T ln I C2 I CO 1 I C2 (24) 14

15 or V T ln I = 1 I C2, (25) I C2 which can be soled numerically for any gien set of parameters. Note that for 1 =0 we get I C2 = I as in the current mirror d). f) This example combines the examples d) and e). Q 1 and Q 3 are diodeconnected deices in the actie mode, with I =(V CC 2 V BE )/. Assuming that Q 4 is actie, I C2 <I, as found in e). Assuming that Q 2 is actie, I C2 = I, which gies a contradiction. Therefore Q 2 must be saturated with I C2 <I = βi B2, which confirms the saturation of Q 2. Finally, we hae: V C2 = V C4 = V CC V CES. You should try soling the examples again if all npn transistors are replaced with NMOS deices and all pnp transistors are replaced with PMOS deices. Assume that all MOSFETs hae the same V t <V CC and K. 4 Applications of smallsignal (incremental) deice models As discussed in Section 3, the purpose of dc biasing is to ensure that all deices are in the desired operating modes. The dc solution gies all steadystate dc oltages and currents. It is then of interest to predict the circuit response to timearying (ac) inputs. This can be accomplished using the deice largesignal nonlinear models. Unfortunately, for designoriented hand analysis this approach usually yields intractable results, and little useful information. Instead, we simplify the task by linearizing the nonlinear deice characteristics around the dc operating point. See the deriation of smallsignal models for MOSFETS in Section 1.2 and BJTs in Section 2.2. The smallsignal analysis can be applied to obtain results such as: Inputtooutput transfer function that shows how the signal propagates through the circuit. For example, we may want to determine the oltage gain of an operational amplifier in order to predict how the finite oltage gain affects some opamp application. As another example, the smallsignal analysis can be used to predict noise margins for a logic gate. This example is discussed in Section 4.1. Input or output impedance that allows us to predict interactions among arious parts of a larger circuit, input sensors, and output loads. For example, it is of interest to determine how large is the output resistance of a current source, i.e., how close the current source is to the ideal infinite output resistance. In general, the smallsignal analysis results show how the quantity of interest (gain, impedance, or something else) depends on: 1. the deice parameters, and 2. the dc operating point. 15

16 VDD 5.0V 4.0V 3.0V CMOS inerter: inputtooutput characteristic (cmos.cir) 1 2 (1.00,5.00) (2.125,4.59) VIL (2.48,3.48) M2 Vtn=Vtp=1V VDD=5V 3 I O 2.0V (2.51,1.51) M1 1.0V (2.875,0.41) VIH 5 0V 0V 1.0V 2.0V 3.0V 4.0V 5.0V (out) Vin 4 (4.00,0.00) Figure 12: CMOS inerter and the O ( I ) inputtooutput characteristic. The deice parameters are: V tn = V tp =1V,K n = K p =30µA/V 2, V A = 50V, V DD = 5V. As a result of the smallsignal analysis, we can modify the design (change components, circuit configuration, or dc bias) in order to meet the specifications. As an introduction to smallsignal analysis, we consider the example of finding the noise margins for a simple CMOS digital logic gate an inerter. 4.1 Example: using smallsignal analysis to determine the noise margins for acmosinerter The CMOS inerter and its largesignal inputtooutput characteristic are shown in Fig. 12. Depending on the operating mode of the two deices, the inputtooutput characteristic has 5 distinct segments. In segment 1, I is less than the NMOS threshold oltage, I <V tn, so that M1 is cutoff. Since SG2 is greater than the PMOS threshold oltage V tp, and since the drain current of M2 is zero, M2 is in the triode mode. The output oltage is O = V DD. In segment 2, I >V tn so that M1 moes from cutoff to saturation. The output oltage starts to drop as the current through M1 and M2 increases. M2 stays in the triode mode as long as DG2 > V tp, i.e., as long as O I > V tp. In segment 3, both M1 and M2 are in saturation. A small change in the input oltage causes a large change in the output oltage. In other words, the (negatie) smallsignal gain of the inerter in this segment is ery large. M1 stays in saturation as long as GD1 <V tn, i.e., as long as I O <V tn. In segment 4, M1 is in the triode mode, and M2 is in saturation, as long as V SG2 > V tp, i.e., as long as I <V DD V tp. In segment 5, M2 is cutoff, M1 is in the triode mode, and O =0. 16

17 In the segments 2, 3, and 4, closedform expressions for O ( I ) can be obtained by soling i D1 = i D2 using the deice largesignal nonlinear characteristics described in Section 1.1. Based on the characteristic of Fig. 12, the circuit in Fig. 12 can be used as a logic inerter: a logic LOW input leel (close to zero) results in a logic HIGH output leel (close to the supply oltage V DD ), and ice ersa. The maximum input oltage that still corresponds to the logic LOW leel is defined as the input oltage V IL such the slope of the O ( I ) characteristic at I = V IL is equal to 1. Similarly, the minimum input oltage that still corresponds to the logic HIGH leel is defined as the input oltage V IH such that the slope of the O ( I ) characteristic at I = V IH is also equal to 1. Consider a logic gate with the dc oltage I at the input, and a small noise oltage around this dc alue. This logic gate is assumed to be in a chain of other similar logic gates. If I is inside the allowed ranges, i.e., if I <V IL,or I >V IH, the output noise signal due to the input is smaller in magnitude than the input noise signal. Therefore, as long as I <V IL or I >V IH, reliable logic leels can be maintained in the chain of logic gates. If the input oltage I is in the forbidden region V IL < I <V IH, the noise is amplified, which may result in erroneous logic leels in the subsequent logic gates. This is why V IL and V IH, where the smallsignal oltage gain of the gate is equal to 1, hae been selected as the noise margin limits. The noise margins for reliable operation of a logic gate show how far an input oltage leel can be from the nominal output oltage leel, NM L = V IL V OL (26) NM H = V OH V IH (27) In the CMOS inerter, the nominal output oltage leels are V OL = 0 (LOW) and V OH = V DD (HIGH). We can apply smallsignal analysis to determine V IL, V IH and therefore the noise margins for the CMOS gate of Fig. 12. For simplicity, we assume that K n = K p = K and V tn = V tp = V t. Let us first determine V IH in the segment (4) of the O ( I ) characteristic. Since we know that M1 is in the triode mode, we start with the deice largesignal deice characteristic [ ] i D1 = K 2( GS1 V t ) DS1 DS1 2, (28) and derie the deice smallsignal parameters following the approach described in Section 1.2. We assume that the total drain current i D1 consists of the dc alue I D1 and a small ac signal component i d1, i D1 = I D1 i d1. (29) We are interested in the response for the small ac signal only, which can be obtained by retaining only the firstorder terms in the Taylor expansion of the largesignal characteristic: i d1 = i D GS gs1 i D DS ds1 (30) 17

18 i G1=G2 g mt1 i S2 (M2 in saturation) g m2 i D1=D2 rdst1 o S1 (M1 in triode) Figure 13: The smallsignal model of the CMOS inerter in segment 4 of the O ( I )dccharacteristic. where the partial deriaties are computed at the dc operating point gien by I D1, V GS1 and V DS1. The expression for smallsignal components can be written in terms of circuit parameters as: i d1 = g mt gs1 1 ds1 (31) r dst where: g mt = i D =2KV DS1, (32) GS 1 = i D =2K(V GS1 V t V DS1 ). (33) r dst DS Note the subscript t used to distinguish the smallsignal parameters in the triode mode from the smallsignal parameters g m and r ds deried earlier for the MOS transistor in saturation (Eqs. (7) and (8)). In the segment 4, we know that M2 operates in saturation, and so the model of Fig. 6 and the parameters in Eqs. (7) and (8) can be applied. With V A, r ds. The complete smallsignal model of the CMOS inerter in segment 4 of the O ( I ) characteristic is shown in Fig. 13. From the model, the boundary V IH can be determined from the condition that the smallsignal gain is equal to 1: o = (g m2 g mt1 )r dst1 = 1. (34) i We ealuate the smallsignal parameters at the point V GS1 = I, V SG2 = V DD I, V DS1 = O, V DD I V t O = I V t O, (35) which yields O = I V DD 2. (36) 18

19 Finally, V IH is found at the intersection of the characteristic O ( I ) and the straight line gien by Eq. (36): O (V IH )=V IH V DD 2, (37) To sole for V IH, we make use of the expression O ( I ) for the dc transfer function of the inerter in segment 4 of the characteristic. The solution to Eq. (37) is: V IH = V DD 2 V DD 2V t 8. (38) Similarly, one can find the expression for V IL in segment 2 of the O ( I ) characteristic, V IL = V DD 2 V DD 2V t 8. (39) For numerical alues: V tn = V tp = 1V, and V DD =5V,wehaeV IL =2.125V, V IH =2.875V, NM L = NM H =2.125V. 4.2 Smallsignal analysis techniques In this section we discuss how the smallsignal deice models can be applied efficiently so that the results for more complex circuits can be obtained with minimum of (usually messy) algebra. For now, we assume lowfrequency signals so that the lowfrequency deice models can be applied. For efficient smallsignal analysis, we rely on the following techniques: 1. prior knowledge of the incremental resistances seen looking into the deice terminals; 2. prior knowledge of the final results for simple, frequently repeated circuits; 3. approximations based on known parameter relations, and applied before, and during the analysis, not after messy (and probably wrong) final results are obtained. 4. usual circuitanalysis shortcuts (oltage and current diiders, parallel and series impedance combinations, Theenin and Norton equialents). The incremental resistances seen at the deice terminals can be determined just once, and then used as needed. Consider an arbitrary circuit shown in the lefthand side of Fig. 14. An arrow is used to indicate the port where we seek the incremental resistance (or impedance in general) seen between the port terminals. In general, the incremental resistance seen at a gien circuit port can be determined by the smallsignal analysis where a test source (oltage t or current i t ) is placed at the port and the response (current i t or oltage t ) is found. The incremental resistance x seen at the port is then found as x = t /i t. 4.3 MOS incremental resistances Fig. 15 shows the incremental resistances looking into the gate (G), source (S) and drain (D) terminals of a MOS transistor operating in saturation. We assume that the dc bias has been soled, and that the dc sources hae been remoed to obtain the smallsignal model. External resistances G, D, S are equialent incremental resistances of the circuitry around the MOS 19

20 VDD x circuit => i t t x = t/it smallsignal model of the circuit Figure 14: Finding the resistance x seen when looking into a circuit port. transistor. An nchannel deice is indicated, but the same results are obtained for a pchannel deice. In this section, the symbol r ds is used to represent the deice incremental output resistance. Note that the symbol r o is also in common use, r o = r ds. The circuits used to sole for the resistances are shown in Fig. 15(a,b,c) esistance seen looking into the gate, g From Fig. 15(a), g (40) by inspection. At low frequencies, MOS gate is a ery high resistance node esistance seen looking into the drain, d To sole for d, we put a test current source i t and find the oltage t that the current source creates at the drain, as shown in Fig. 15(b): But, so that: t = S i t (i t g m gs )r ds. (41) gs = g s =0 S i t, (42) t = S i t i t (1 g m S )r ds, (43) and d = t = r ds (1g m r ds ) S. (44) i t You may try to derie the same result using a oltage test source. Special cases and approximations The product g m r ds is always much greater than 1, and so a somewhat simpler expression for d is obtained: d r ds (1 g m S ). (45) 20

21 G G d s (c) smallsignal model to find (b) smallsignal model to find S S S D D D G G G t t t ds ds ds r r r gs gs gs m m m g g g g (a) smallsignal model to find G g S S S s d D D D t t t i i i Figure 15: Incremental resistances seen when looking into the gate (a), drain (b), and source (c) of a MOS transistor. 21

22 If, in addition, g m S >> 1, d becomes: d g m r ds S (46) Note that for S > 0, d can be much greater than either S or r ds. If S = 0, i.e., if the source is at ac ground, the resistance seen looking into the deice drain is just the deice output resistance r ds, d = r ds = V A I D. (47) In the last expression, r ds is shown as a function of the deice parameter V A and the deice dc operating current I D. In any case, een for S = 0, the resistance d is relatiely large. In other words, when the deice operates in saturation, the drain current is almost independent of the draintosource oltage esistance seen looking into the source, s To sole for s, we put a test oltage source t and find the resulting current i t, as shown in Fig. 15(c): i t = g m gs t d. (48) r ds Using d = D i t, (49) and gs = t, (50) we obtain: i t = g m t t D i t, (51) r ds which can be soled for s, s = t = r ds D. (52) i t 1g m r ds You may try to derie the same result using a test current source. Special cases and approximations As for d, we can use the fact that g m r ds >> 1 for the deice, so that s becomes: s r ds D = 1 D. (53) g m r ds g m g m r ds The deice output resistance r ds is frequently much larger than the resistance D seen in the drain of the deice. If r ds >> D, we hae the simplest result for s, s 1 g m = 1 2K(V GS V t ) = 1 2, (54) KI D which can be used in most applications. In the last expression, we explicitly use the fact that g m depends on the deice parameters, K and V t, and the dc operating current I D. Wheneer D <r ds, the resistance seen looking into the source is in the order of 1/g m, which is relatiely low. 22

23 C B c b E e 4.4 BJT incremental resistances Figure 16: Incremental resistances of the BJT. As for the MOS deices, we can determine the incremental resistances for the BJT. You may try to derie the results that are listed here with reference to Fig. 16. In this section, the symbol r ce is used to represent the deice incremental output resistance. Note that the symbol r o is also in common use, r o = r ce. Using g m r ce >> 1, we obtain the resistance b seen looking into the base: b = r π (1β) E r π β E. (55) If E =0, b = r π. The resistance c seen looking into the collector is: ] β E c = r ce [1. (56) E r π B If E >> r π and E >> B, c βr ce. (57) If E =0, c = r ce = V A /I C.Inanycase, c is relatiely high. Using g m r ce >> 1, we obtain the resistance e seen looking into the emitter: e = B r π 1β. (58) If B << r π, the simplest result for e is obtained: e r π β = 1 = 1. (59) g m I C /V T 23

24 In general, e is relatiely small. Smallsignal analysis of more complex structures will make frequent use of the incremental deice resistances deried in this section. 5 A Design Example The deiceleel design example in this section illustrates how basic singletransistor amplifier stages can be combined together to meet a set of design specifications. We make use of the MOSFET largesignal and smallsignal characteristics summarized in Section 1, and the smallsignal analysis techniques discussed in Section 4. For discussion about configurations and properties of the basic singletransistor amplifier stages (common source, commondrain, and commongate), refer to the suggested reference textbooks. Design Specifications A magnetic pickup can be represented as an ac oltage source g < 10mV in series with a g = 100kΩ resistance. It is desired to design a CMOS amplifier for the pickup according to the following specifications: 1. the DC output oltage is V O = 0V; 2. the smallsignal oltage gain is A o = o / g = 10; 3. the DC bias current through g must be equal to zero. 4. the amplifier output resistance is out 1kΩ; To design the amplifier, the following components are aailable: 1. 2 discrete resistors, and 1 large capacitor (C ); 2. n and pchannel enhancementmode MOS deices; 3. two dc oltage sources, V DD = V SS = 10V, connected in series to obtain the ±10V supply around the ground. All transistors hae the same parameters: V tn = V tp = V t =1V,V A = 100V, and K n = K p = K =20µA/V 2 for W/L = 1. The deice conductance parameter K is directly proportional to the channel width W to length L ratio. For each deice, the ratio W/L can be selected to scale K. It is not necessary that all deices hae the same K. A solution consists of finding a suitable circuit configuration, and finding all deice parameters (W/L of all MOSFETs, and resistances of all resistors) to meet the specifications. Solution The first step in the design is to choose a circuit configuration based on the design specifications. Since the required gain is A o > 1, the amplifier should include at least one commonsource (CS) stage. Since the gain of a CS stage is negatie, two CS stages can be used to obtain the oerall gain A o > 0. The capacitor can be used either for injecting the ac signal to the input of 24

25 VDD = 10V (W/L)2,3,5,7 = 1 (W/L)1 = 6.25 (W/L)4,6 = 25 VG 2 V1 I1 Q1 I2 Q3 Q2 V mA I3 900k I Q4 20uA Vg g C 20uA I1 Q5 Q6 I3 Vo Q7 VSS = 10V Figure 17: One possible solution to the design problem. the amplifier without disturbing the dc bias at the input, or to boost the gain of a CS stage by shorting the source to ac ground. Since both positie and negatie supplies are aailable, the input can easily be dc biased at 0 olts, so that the pickup can be connected directly to the input, without the capacitor in series. Instead, the aailable capacitor can be used to boost the gain of a CS stage by shorting the source to ac ground. The second CS stage can also be designed to satisfy the outputresistance specification. Alternatiely, we may use a commondrain (CD, or sourcefollower) stage at the output, to meet the specified outputresistance, and also to obtain the zero output dc bias without additional discrete resistors. The amplifier stages can be biased using current mirrors. Based on the aboe considerations, a possible amplifier circuit is shown in Fig. 17. The input side of the current mirrors, Q 7, is dc biased from the dc supplies through 1. The currentmirror outputs, Q 5 and Q 6, sere as current sources to dc bias the input CS stage built around Q 1, and the output CD stage built around Q 4. Q 6 is also the actie load for Q 4. 2 is the load for the first CS stage. The output 1 of the first CS stage is the input to the second CS stage consisting of Q 2 and Q 3. The sourcetogate of Q 2 is dc biased by the oltage drop 2 I 1 across 2. The diodeconnected deice Q 3 is the load for Q 2, and at the same time it proides the dc bias V 2 at the gate of Q 4 so that the output dc oltage V O can be adjusted to zero by selecting V GS3 = V GS4. In the paper design, it is conenient to neglect the effects of finite V A on the dc bias solution, and on the smallsignal results. Once the design is completed, the approximations can be erified. Also, we assume that all deices are biased to operate in saturation, which should be erified once the design is completed. A set of dc bias relations, and smallsignal results can now be written for the circuit of 25

26 Fig. 17: 1 = V DD V SS V GS7 I, (60) I 2 O = V 2 V GS4 = K 3 The smallsignal oltage gain can be found as: A o = ( ) (2 )( ) ( o 1 o = ( g m1 2 ) g g I 1 = K 5 K 7 I, (61) I 3 = K 6 I, K 7 (62) I 2 = K 2 ( 2 I 1 V t ) 2, (63) V 2 = I 2 V t, K 3 (64) 1 2 I 3 K 4, (65) g m2 g m3 ) (1), (66) while the output resistance is: For all deices the transconductance: out 1 g m4. (67) g m =2K(V GS V t )=2 KI D (68) is ealuated at the appropriate dc operating point. Once the circuit configuration has been decided, and the necessary analytical results hae been determined, we proceed to determine the parameter alues in order to meet the design specifications. The set of design specifications is not sufficient to uniquely determine all parameter alues. Additional design considerations, depending on the application, may include: 1. minimization of the total deice area; for a gien channel length L, we attempt to minimize the ratios W/L for the deices; 2. minimization of the quiescent power consumption; we attempt to minimize dc bias currents; 3. ability to handle largeamplitude ac signals without distortion; we attempt to dc bias the amplifier so that the dc operating point is as far away from the operatingmode boundaries (triode or cutoff) as possible; 4. frequencyresponse and transientresponse specifications. 26

27 None of these additional constraints hae been specified in this design problem, so that we hae some freedom in selecting the alues. Consider first the outputresistance requirement. From Eqs. (67) and (68), we hae: 1 out = 2 =1kΩ. (69) K 4 I 3 Select I 3 =0.5mA, as a compromise between large power consumption and large deice size. As a result, K 4 = 500µA/V 2,and (W/L) 4 = K 4 =25. (70) K Note how a relatiely large deice and a relatiely large dc bias current are needed to meet the small output resistance requirement. For Q 2, Q 3, Q 5 and Q 7, we select the minimumsize deices, (W/L) 2,3,5,7 =1,biasedat K I = I 1 = I 2 = I 3 = 0.5mA =20µA. (71) K 4 25 To get I 3 =0.5mA, we also select K 6 = K 4, i.e., (W/L) 6 =(W/L) 4 = 25. The dc gatetosource oltage for all deices aboe is: I V GS 2,3,4,5,6,7 = V t K = V t I 3 K 4 =2V. (72) From Eq. (60), we hae 1 = 900kΩ, and from Eq. (63), we hae 2 = 100kΩ. Also, V O = V GS3 V GS4 = 0V, as required. Since K 2 = K 3 = K, andq 2, Q 3 hae the same dc bias current I 2 = I =20µA, the smallsignal gain from 1 to 2 is 2 / 1 = g m2 /g m3 = 1. Therefore, the gain requirement from Eq. 66 becomes A o = g m1 2 =10, (73) which yields: A o =2 K 1 I 1 2 =10, (74) ( ) 2 Ao 1 K 1 = = 125µA/V 2. (75) 2 2 I 1 Therefore, (W/L) 1 = K 1 =6.25. (76) K To erify the assumption that r ds is sufficiently large, we hae (r ds ) 1,2,3,5,7 = V A /20µA = 5MΩ >> 2 = 100kΩ > 1/g m,and(r ds ) 4,6 = V A /0.5mA = 200kΩ >> 1/g m =1kΩ. Some loss in the gain because of the finite r ds can be easily compensated for by rounding (W/L) 1 up. We proceed to confirm that that all deices are in saturation at the dc bias operating point. For the specified amplitude of the input signal, g 10mV, it is also easy to confirm that all deices remain in saturation for all time when the ac input is applied to the input. The ac oltages at 1, 2 and o are within ±100mV around the dc bias. As an excercise, run PSpice simulations of the circuit in Fig. 17 to erify that it meets all design specifications. 27

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