Design of Sparse Filters for Channel Shortening

Transcription

1 Journal of Signal Processing Systems manuscript No. (will be inserted by the editor) Design of Sparse Filters for Channel Shortening Aditya Chopra Brian L. Evans Received: / Accepted: Abstract Channel shortening equalizers are used in acoustics to reduce reverberation, in error control decoding to reduce complexity, and in communication receivers to reduce inter-symbol interference. The cascade of a channel and channel shortening equalizer ideally produces an overall impulse response that has most of its energy compacted into fewer adjacent samples. Once designed, channel shortening equalizers filter the received signal on a per-sample basis and need to be adapted or re-designed if the channel impulse response changes significantly. In this paper, we evaluate sparse filters as channel shortening equalizers. Unlike conventional dense filters, sparse filters have a small number of non-contiguous non-zero coefficients. Our contributions include (1) proposing optimal and sub-optimal low complexity algorithms for sparse shortening filter design, and (2) evaluating impulse response energy compaction vs. design and implementation stage computational complexity tradeoffs for the proposed algorithms. We apply the proposed equalizer design procedures to(1) asymmetric digital subscriber line channels and (2) underwater acoustic communication channels. Our simulation results utilize measured channel impulse responses and show that sparse filters are able to achieve the same channel energy compaction with half as many coefficients as dense filters. Keywords channel shortening sparse filters time-domain equalizers discrete multi-tone modulation reverberant channels This research was supported by an equipment donation from Intel Corporation. Aditya Chopra The University of Texas at Austin, Austin, TX Tel.: aditya@mail.utexas.edu Brian L. Evans The University of Texas at Austin, Austin, TX Tel.: bevans@ece.utexas.edu

2 2 1 Introduction In many discrete-time signal processing systems, the distortion caused by signals passing through the environment is modelled as a discrete-time finite impulse response (FIR) filter, typically referred to as a channel. An important property of the channel is its delay spread, defined as the duration in time (or samples for discrete-time systems) within which most of the channel impulse response energy is contained. This delay spread may be caused by the inherent frequency selectivity of the communication medium or by multipath propagation of the signal through the medium. In many signal processing and communication applications, a large delay spread in the channel causes impairments in analyzing signals that have passed through this channel. For example, a large delay spread manifests as reverberation in acoustic channels [1], causes inter-symbol interference (ISI) in communication systems [2] and increases complexity of sequence estimators such as the Viterbi decoder [3]. The goal of channel shortening is to design an equalizer to reduce the delay spread of the channel impulse response. As an example, Figure 1 shows the impulse response of a typical asymmetric digital subscriber line (ADSL) channel and the combined impulse response of this channel and a time-domain shortening equalizer. The shortened impulse response shows clear compaction of energy into fewer samples compared to the original channel impulse response. Channel shortening equalizers have shown significant improvement in data rate performance of discrete multitone modulation (DMT) receivers [4, 5, 6] ISI reduction in underwater acoustic communication systems [7, 8]. Figure 2 shows an example of a typical measured underwater channel with a direct path and multiple echoes. Conventional channel shortening equalizers are designed as dense FIR filters with contiguous non-zero coefficients and attempt to optimize some metric of shortening performance [9]. The channel shortening design tradeoff arises from the fact that a longer equalizer typically has better shortening performance at the cost of increased complexity of the filter implementation [6]. In this paper, we propose a new approach to channel shortening using sparse filters which have non-contiguous filter taps[10]. By obviating the need for arithmetic operations corresponding to zero-valued coefficients, sparse filters with a large delay spread have the same runtime computational complexity as a dense FIR filter with equal number of non-zero taps. Sparse filters can also translate to fewer circuit components compared to dense FIR filters, consequently reducing area or power consumption. In [11], linear algorithms are proposed to design sparsest filters that satisfy the required frequency domain constraints. Sparse filters are also used to design minimum mean square error (MMSE) equalizers for underwater channels in [12]. The key behind sparse filter design is to find the most effective tap positions for non-zero coefficients. Prior work contains several high complexity[10, 13] and sub-optimum low complexity [12] methods for finding these tap locations for MMSE equalization. In this article, we apply sparse filter design to channel shortening which does not follow the MMSE formulation of conventional equalizer design.

3 Channel amplitude Original channel impulse response Shortened channel impulse response Delay (samples) Fig. 1 ADSL Carrier Serving Area Loop 1 channel model impulse response before and after shortening This article is an extension to results first published in [14], in which we proposed using sparse filters as channel shortening equalizers. In[14], we design optimal sparse filters, proposed a low complexity solution to channel shortening, and applied our results to ADSL communication channels. In this article, we propose another low complexity method of sparse filter design using two-tap filter cascades[15], evaluate the shortening performance of channel shortening on measured underwater wireless channels, and study the impact of design parameters on channel shortening performance of sparse filters. The rest of this paper is organized as follows. Section 2 illustrates the system model of the channel shortening block placed in the receiver. Section 3 summarizes the conventional method of shortening equalizer design using dense FIR filters. Section 4 introduces the notion of sparse filters and extends the conventional equalizer design problem to sparse filter solutions. Section 5 details the two proposed low complexity sub-optimal filter design solutions. Section 6 compares the design and runtime computational complexity of the proposed algorithms. Section 7 lists the simulation parameters and shows the simulation performance of the different shortening equalizers. The conclusions of this study and key take-aways are provided in Section 8. 2 System Model We consider a digital signal processing system with a analog-to-digital (A/D) converter sensing the environment at a sample rate of R samples per second. The A/D converter can be the front end of a wired or wireless communication

4 Direct Path Echo Channel amplitude Reverberation Underwater acoustic channel impulse response Delay (samples) Fig. 2 Time domain impulse response of an underwater communication system showing the direct path and echo. receiver or a microphone that is sensing acoustic signals. A separate source is transmitting signals of interest which travel through a medium between the source and receiver. The channel between source and receiver is modelled as a FIR filter. The receiver operates in one of two modes: 1) training or 2) runtime. In training mode, the source transmits a known signal or a training sequence, which is captured by the receiver and used to estimate the time-domain impulse response of the channel and subsequently design channel shortening equalizers. In order to maintain a low training time, it is important that the channel shortening equalizer design requires as few computations as possible. During runtime mode, an unknown signal is transmitted by the source and shortening equalizers at the receiver filter incoming samples in order to reduce the effective delay spread of the channel. In the runtime mode, the extent to which the shortening equalizer can reduce the channel delay spread determines the amount of impairment caused due inter-symbol interference or reverberation. A well designed shortening equalizer will improve the operating performance of the receiver by reducing such impairments caused by a large channel delay spread. 3 Channel Shortening Filter Design Consider the time-domain impulse response of a channel represented by a vector h of N h equi-spaced sample values. The objective of channel shortening is to compact channel response energy inside a window N s samples in length

5 5 and starting at sample. This window is also referred to as the shortening window. Ideally, our goal is to design a FIR filter such that the convolution of the channel and this filter contains zero energy in its impulse response outside the shortening window. However, due to constraints such as finite length of the shortening filter, this objective is usually not satisfied. An approach first used by Melsa [16] designs the shortening equalizer in order to maximize a metric known as the shortening signal-to-noise ratio (SSNR). SSNR is defined as the ratio of energy inside the shortening window to the energy outside the shortening window of the shortened channel impulse response. A higher SSNR value indicates that the interference causing energy of the channel outside the shortening window is insignificant compared to the energy of the channel inside the window and our shortened channel response is closer to the ideal. The goal of using shortening equalizers in high-speed communication receiversis to removeisi in orderto maximize datarate [4] orminimize bit-error rate [17]. Although maximizing SSNR is not necessarily equivalent to maximizing data rate [4] or minimizing the channel delay spread [18], it makes the shortening equalizer design problem mathematically tractable and efficient to implement. It has been shown through simulations that SSNR maximization provides close to the same data-rate and bit-error rate performance compared to shortening filter design methods that explicitly attempt to maximize data rate or minimize bit-error rate [4, 19]. Shortening equalizer design using SSNR maximization can be considered as a favorable trade-off between shortening performance and implementation tractability. The rest of this article focuses solely on the SSNR maximization approach to channel shortening equalizer design. The impulse response of the shortened channel, denoted by the vector h short, is the convolution of the original channel response h and the L tap shortening equalizer w. This can be expressed as h short = h w = Hw (1) wherehisthe N h +L 1 LToeplitzconvolutionmatrix[20]correspondingto thechannelh.h short canbedecomposedintoitscomponentsh in andh out that are inside and outside of the shortening window, respectively. Mathematically, these components can be expressed as h in =h short(, +1,, +Ns 1) (2) h out =h short(,, 1, +Ns,, ) (3) where the shortening window is N s samples in length starting from sample. To design the optimum SSNR filter we need to design shortening equalizers for each value of Z + and perform an exhaustive search to select the equalizer candidate with the best shortening performance. In order to keep computational complexity in check, we first estimate a sub-optimal delay [21] and then solve for the SSNR maximizing equalizer once. The heuristic

6 6 used to estimate the sub-optimal value is given as +N s = max h in (u) 2. (4) Z + u= Here Z + denotes the set of non-negative integers. Henceforth, the value of in (4) would be implicitly assumed in the notation h in and h out. The energy of the shortened channel impulse response inside and outside the shortening window can then be expressed as E S = h in H h in (5) E I = h out H h out, (6) respectively. By combining (5) and (1), we can express the impulse response energy inside and outside the shortening window as and E S = w H H H in H inw (7) E I = w H H H out H outw, (8) respectively. Here H in is the sub-matrix formed by the to +N s 1 rowsof H and H out is the sub-matrix formed by removing H in from H. This process is similar to the construction of h in and h out from h, as shown in (2). Using (7) and (8), the output SSNR ofthe shortenedchannelresponsecan be written as SSNR = E S E I (9) = wh H H in H inw w H H H out H outw = wh Aw w H Bw where A = H H win H win and B = H H wall H wall. Thus, SSNR maximizing filter design can be expressed as (10) (11) w opt = arg max w R L w H Aw w H Bw. (12) The optimization problem in (12) can be solved [16] using the generalized eigenvalue solution [20] as w opt = ( A ) H qmin (13) where q min is the eigenvectorcorresponding to the minimum eigenvalue of the matrix C, where C is given by C = ( A ) 1B ( A ) H (14)

7 7 The SSNR-optimal solution is based on the assumption that matrix A is positivedefinite andhas acholeskydecomposition A, wherea = A A H. In order to avoid A from being singular, Yin [22] provides an objective function to minimize w H Bw while satisfying the constraint w H Aw = 1. In this case, the assumption is that B is positive definite since a Cholesky decomposition on B is required. Either method requires a Cholesky decomposition, eigendecomposition, and matrix inversion of an L L matrix in order to design the optimum shortening equalizer solution w opt. 4 Optimal Sparse Filter Design for Channel Shortening In the channel shortening filter design method discussed in Section 3 an implicit constraint on the filter coefficient optimization process is that the filter taps are placed in a contiguous manner. The filter length parameter L, dictates the computational complexity of filter design and implementation. This parameter allows the designer to adjust the tradeoff between channel shortening performance and implementation complexity. In this section we relax the constraint on the non-zero filter taps being contiguously placed and instead constrain the total number of non-zero taps of the shortening filter (L). Consequently, the delay spread of the filter is greater than L and is limited by a parameter M, which is the maximum allowable delay spread of the sparse filter solution. The sparse filter may have a delay spread less than M if the coefficients at the end of its impulse response are zero. 4.1 Sparse channel shortening filter design problem By removing the contiguous filter coefficient constraint in (12), the sparse channel shortening filter design problem can then be expressed as w opt = w H Aw max w R M; w 0 =L w H Bw (15) where. 0 indicates the zero-order norm of a vector. The zero-order norm is not a true vector norm and commonly defined as w 0 = lim p 0 ( M 1 m=0 w p ) 1 p (16) The zero-order norm of a vector precisely corresponds to the number of nonzero elements in the vector, consequently w 0 = L places a constraint on the number of non-zero taps of the filter. The following sub-section details the optimum solution to this problem achieved via an exhaustive search through the design space.

8 8 4.2 Exhaustive search method The optimum solution to (15) can be attained by jointly optimizing over the location of the taps and the tap coefficients during filter design. In the optimum method, the SSNR maximizing shortening filter is designed for all candidates where i = 1,2,..., ( M 1 L 1) indexes all possible locations where nonzero taps can be placed in a L tap equalizers with length less than M. Thus w sparse i M L elements of w sparse i are forced to value 0. The set of all the possible tap locations that satisfy the constraints w R M, w 0 = L is denoted as S, where S = ( M 1 L 1) and each element si S in some way represents the location of the non-zero taps in w sparse i. One way to represent the set S is to decompose sparse vectors as w sparse = sw non zero. (17) If the delay values of non-zero taps are {d 1,d 2,,d L }, then s i is a M L matrix whose elements are given as { 1 if dq = p s(p,q) = (18) 0 otherwise Thus, each element s i S is a matrix that represents the non-zero tap locations of the corresponding sparse filter w sparse i and there are ( M 1 L 1) such matrices for all possible combinations of tap locations with the first non-zero tap fixed at delay = 1. Consider an example scenario where M = 5 and L = 2. A possible sparse filter w sparse = [w w 2 0] T can be expressed using (17) where w non zero = [w 1 w 2 ] T and s = (19) 0 0 Thus the optimization problem related to sparse shortening equalizer design can be derived by starting with (15), given as w opt = w H Aw max w R M, w 0 =L w H Bw (20) We can rewritethe sparsefilter constraintin (15) asthe searchspace S defined earlier. This yields the following optimization w opt = max i=1,, S w sparseh i Aw sparse w sparse i i H Bw sparse (21) where we propose to maximize the shortening SNR by designing the filter candidate for all possible indices i. Combining (21) and (17) yields w opt = max i=1,, S w non zero H i s H i As i w non zero i w non zero i H s H i Bs i w non zero i (22)

9 9 where the matrices s H i, A, B and s i can be combined. This gives us w opt = w H A i w max w R L;i=1,, S w H B i w (23) where A i = s H i As i (24) B i = s H i Bs i (25) Heres i isam Lmatrixisgivenby(19).Theequalizerdesignisequivalent to performing S independent SSNR maximizations using (13). This method jointly optimizes the locations of the non-zero taps and the filter coefficients. The exhaustive search solution yields the globally optimum shortening filter within the constraints of the problem. The computational complexity cost of using this approach is very high since ( M 1 L 1) individual optimizations are being performed to design the shortening filter. Each individual optimization involves a Cholesky decomposition, eigenvalue decomposition and inversion of a L L matrix. The computational complexity required in the design of the exhaustive search algorithm is given in Table 1. 5 Sub-optimal Sparse Filter Design for Channel Shortening In Section 3, the optimal solution to sparse shortening equalizer design jointly optimizes the tap delay locations of the non-zero filter coefficients and the coefficient values. The dramatic increase in design computations using the SSNR maximizing method is a consequence of performing an exhaustive search to determine locations to place a limited number of non-zero taps in a long filter. It is easy to see from Figure 8 that sparse equalizers with as few as 8 non-zero taps and a maximum delay twice as long, are impractical to implement using the optimal exhaustive search algorithm. To reduce the number of computations required for filter design, we propose to separate the evaluation of tap delay values and filter coefficients. It may be easier to determine potentially good delay values to place non-zero taps and while such an equalizer may not be the SSNR-optimal solution, a minor loss in SSNR performance is justified by the ease of implementation. Given the location of non-zero filter taps, the SSNR maximizing filter coefficients can be evaluated as w opt = max w R L w H A i w w H B i w (26) where i indicates the index corresponding to the non-zero tap delay locations as per the formulation in Section 4.2. Evaluating the optimal locations for the non-zero taps is a considerably harder problem to solve and we propose two sub-optimal approaches to determine tap delay values that may potentially maximize the SSNR.

10 Maximal weight tap selection The first heuristic method of tap-selection is the maximal weight algorithm where we design a length M dense filter and choose the strongest L taps in terms of magnitude as the tap delay locations for the sparse non-zero filter coefficients. The intuition to this approach being that the strongest dense filter coefficients account for the major chunk of energy compaction carried out by the filter. The location of these strongest taps can then be used to design the sparse filter using (13). Algorithm 1 shows the steps in the maximal weight design procedure. This approach necessitates the design of one M tap dense equalizer and one L tap sparse equalizer, thereby greatly reducing the computations needed compared to an exhaustive search. The maximal weight algorithm has been used previously in wireless receiver design for CDMA communication systems[23]. The application of this algorithm in [23] was to invert wireless channels and we can apply the same framework to our SSNR maximizing formulation for channel shortening. The computational complexity required in the design of the maximal weight algorithm is given in Table 1. Algorithm 1 Maximal weight sparse filter design algorithm Estimate channel impulse response vector h Design M tap dense optimal filter using (12) for i = 1 to L do d i = {d : h[d] h[k] k = {1,,M}/{d 1,,d i 1 } end for Evaluate s i using {d 1,,d L } in (19) Design L tap sparse filter using (23) 5.2 Cascaded design method The divide-and-conquer approach to shortening equalizer design, first proposed in [24] divides a large filter design into multiple short two-tap filter design problems. In this approach channel shortening is performed by a cascade of L two-tap filters. The architecture of this cascaded channel shortening equalizer is illustrated in Figure 4 and can be compared to the conventional dense equalizer in Figure 3. Each of the two-tap filters in the cascaded design is normalized such that the first filter coefficient is unity, allowing each cascade to be parametrized by a single scalar value. The combined FIR filter yielding from L two-tap cascades has L+1coefficients with the first coefficient equal to 1.0 and requires L multiplication operations per sample. The channel shortening equalizer formed by the cascade of L stages can be expressed as w casc = w 1 w 2 w L (27)

11 11 The k th two-tap filter w k is designed to maximize the SSNR of the original channel convolved with the k 1 filters that were designed in prior iterations. We denote this interim channel by the vector h k k [0,L]. Note that h 0 is the same as the original channel h. The SSNR maximization problem at the k th iteration can be written as w k = arg max w R 2 w H A k 1 w w H B k 1 w (28) where A k 1 and B k 1 arethe signal and ISI matricesof the channel convolved with w 1, w 2 upto w k 1. The initial values are A 0 = A and B 0 = B, respectively. Note that A k and B k are all symmetric 2 2 matrices. These can be expressed as [ ] a1,k a A k = 2,k (29) a 2,k a 3,k [ ] b1,k b B k = 2,k (30) b 2,k b 3,k We can also rewrite w k,opt as w k,opt = [1 w k,opt ] (31) where w k,opt is the second coefficient ofthe two-tap filter cascade.we can then optimize w k,opt by substituting (31) and (29) in (28). Upon simplification, this substitution yields the following maximization problem where γ k (w) is expressed as w k,opt = argmax w R γ k(w) (32) γ k (w) = a 1,k 1 +2a 2,k 1 w+a 3,k 1 w 2 b 1,k 1 +2b 2,k 1 w+b 3,k 1 w 2 (33) = N s+ 1 u=0 h 2 [u]w 2 +2h[u]h[u 1]w+h 2 [u 1] u=n s h 2 [u]w 2 +2h[u]h[u 1]w+h 2 [u 1] (34) Here h[u] is the channel impulse response at tap delay u. The optimum value of the second equalizer tap at each stage can be analytically solved by maximizing the ratio of two quadratic polynomials. By differentiating γ k (w) with respect to w and setting the derivative to zero, we get (a 3,k 1 b 2,k 1 b 3,k 1 a 2,k 1 )w 2 k,opt (a 1,k 1 b 3,k 1 b 1,k 1 a 3,k 1 )w k,opt + (a 2,k 1 b 1,k 1 b 1,k 1 a 2,k 1 ) = 0 (35)

12 12 Both roots of (35) are real [25] and the root w k,opt with higher SSNR is chosen as the coefficient of the two-tap cascade. The cascaded design algorithm is a suboptimal greedy approach to equalizer design that tries to maximize the SSNR at each iteration. The complexity savings arise due to the fact that the computational requirement of designing L two-tap equalizers is significantly lower compared to designing a single SSNR optimal L tap equalizer. However, since the design of L two-tap equalizers is carried out in a greedy iterative manner, the resulting sparse equalizer may not be the global optimum SSNR maximizing filter. The cascaded design method has been proposed as a low complexity sub-optimal alternative to SSNR maximizing channel shortening equalizers[25]. To extend this divide and conquer approach to sparse shortening equalizer design, we remove the constraint that the two taps of each filter w k are contiguous and the resultant combination of L two-tap sparse filters would yield a sparse filter with delay spread greater than L. By the virtue of search space expansion the sparse filter design will yield a shortening equalizer with SSNR performance no worse than the dense cascaded design approach. Similar to the construction of the dense two-tap cascade in (31), the sparse two-tap cascade can be written as w k,opt = [1 0 dk w k,opt ] T (36) where 0 dk is a vector containing d k zeros. Note that the sparse cascade is parametrized by a real scalar w k,opt which indicates the tap coefficient and a non-negative integer d k which indicates the delay between the two taps of the cascade. By substituting (36) in (12) we get w k,opt = arg max w R,d Z + γ k (w,d) (37) Notice that the optimization in (37) is based on two parameters w and d, as opposed to (32) which optimizes only one scalar. γ k (w,d) is expressed as γ k (w,d) = L CP u=0 h 2 [u]w 2 +2h[u]h[u d 1]w+h 2 [u d 1] u=l CP h 2 [u]w 2 +2h[u]h[u d 1]w+h 2 [u d 1] (38) and the optimum value of w for each candidate d can be evaluated by evaluating the root of the derivative similar to (35). An exhaustive search over possible delay candidates d yields the global optimum without significantly increasing complexity. The maximum possible delay of the two-tap sparse cascade can be fixed as a design parameter C. The design algorithm is given in Algorithm 2. Note that the sparse filter resulting from the combination of L two-tap cascades will have greater than or equal to L non-zero taps and a delay spread between L and CL.

13 13 input Z -1 Z -1 Z -1 w 1 w 2 + w 3 w L + + output Fig. 3 Block implementation diagram for a conventional dense FIR filter with L taps. w 0, w 1,...,w L are the L tap values of the filter. The cascaded approach to sparse filter design requires C quadratic root evaluations for each of the L two-tap sparse filters and L convolutions of the channel vector with a two-tap filter, yielding a total computational complexity providedin Table1.It isimportant tonotethat the resultantcombinationofl sparse two-tap cascades will have greater than or equal to L filter coefficients, yet implementing the filter using the block diagram from Figure 5 will still require L per-sample multiplications and addition operations during runtime. The cascaded design algorithm is deemed sub-optimal due to its greedy iterative approach to maximizing SSNR. However, it is important to understand that the L cascade sparse filter with L non-zero coefficients (L L) is sub-optimal to an exhaustive search sparse filter with L non-zero coefficients. L cascade sparse filters cannot be deemed sub-optimal with respect to L tap sparse filters since they attempt to solve different optimization problems. We can appropriately compare the SSNR performance of a L tap dense filter, a L non-zero tap sparse filter, and a L cascade sparse filter because each requires L per-sample multiplication and addition operations during signal filtering. Algorithm 2 Cascaded sparse filter design algorithm Estimate channel impulse response vector h d 1 = 0 h c = h w casc = 1 w 2tap = 1 ρ j,max = 0 for i = 1 to L do for j = 1 to C do d 2 = j Evaluate s i using {d 1,d 2 } in (19) Design 2 tap sparse filter w j using (23) with output SSNR = ρ j if ρ j ρ j,max then ρ j,max = ρ j w 2tap = w j end if end for w casc = w 2tap w casc end for

14 14 input + + output + Z -1 Z -1 Z -1 w 1 cascade Fig. 4 Block implementation diagram for a cascaded design dense FIR filter with L cascades. w i indicates the multiplicative factor for the i th cascade. w 2 w L input + + output + Z -d 1 Z -d 2 Z -d L w 1 cascade Fig. 5 Block implementation diagram for a cascaded design sparse FIR filter with L cascades.w i and d i indicate the multiplicative factor and tap delay, respectively, for the i th cascade. w 2 w L 6 Computational Complexity Analysis From the system model in Section 2, the computations related to channel shortening are performed in two stages: 1) training and 2) data transmission. In order to compare the various proposed channel shortening equalizer design techniques, the combined computations from these two stages form the quantitative metric of computational complexity. The design complexity is the computations needed to evaluate the desired filter coefficients after estimating the channel impulse response vector. Algorithms 1 and 2 show the steps performed by each of the proposed design algorithms. Using the computational requirements of common matrix operations [20], the overall complexity cost of each design algorithm can be evaluated. The runtime computational complexity for each filter is simply dictated by the number of non-zero coefficients in the filter, regardless of coefficient sparsity. Table 1 shows the complexity in terms of multiplications and additions during the design and data transmission stages. As an example, we apply our channel shortening algorithms in an ADSL communication system with sampling rate R = MHz. Due to the computations being performed on a per-sample basis during runtime, the runtime computational complexity overshadows the design stage complexity. Table 2 shows the design and one second of runtime computational complexity costs for different combinations of filter length and design algorithms. The complexity cost here is defined as the number of multiplications required. Table 2 lists the multiplications needed for design and 1 second of runtime for the various

15 15 Table 1 Computations required by channel shortening during design and runtime stages. The channel estimate is a N h length vector. The exhaustive search and maximal weight equalizers have L non-zero taps and a maximum allowable tap delay of M. The cascaded equalizer has L two-tap cascades and a maximum allowable delay of C per cascade. The sampling rate is R samples per second and the runtime computational complexity is calculated for T seconds of filtering. Design Algorithm Additions Multiplications Sq. Root Dense (Optimal) 24L 3 +(N h +24)L 2 +21L 24L 3 +(N h +24)L 2 +24L L Sparse (Exhaustive N h M 2 +(24L 3 +24L 2 + Search) 21L) ( N M 1) h M (L 3 + L 2 + L) ( M 1) L 1 L 1 Sparse (Maximal 24(M 3 + L 3 ) + 21(M + 24(M 3 + L 3 ) + 24(M + Weight) L)+(N h + 24)(M 2 + L 2 ) L)+(N h + 24)(M 2 + L 2 ) Dense (Cascaded) (2N h +7)L (2N h +7)LN h L Sparse (Cascaded) (2N h +7)CL (2N h +7)CL CL Runtime LRT LRT L ( M 1 L 1 ) (L+M) Table 2 Complexity cost as number of multiplications during design and 1 minute of data transmission for different combinations of design type and non-zero taps/two-tap cascades. L is the number of non-zero taps for the dense, exhaustive search and maximal-weight filter design algorithm and it is the number of two-tap sparse cascades for the cascaded design algorithm. We use a single parameter L to represent the number of non-zero taps or sparse cascades, as in either case the resultant filter requires L runtime multiplications per filtered sample. The maximum allowable equalizer delay (M) for exhaustive search and maximal weight algorithms is 12, maximum delay of two-tap sparse filter in cascaded design (C) is 6, channel impulse response length (N h ) is 256, and sampling rate is MHz. Non-zero taps Design Design Design+runtime /cascades method complexity complexity L = 8 dense (100%) L = 6 exhaustive (91.25%) L = 6 max. wt (75.42%) L = 6 cascade (74.98%) L = 4 exhaustive (52.00%) L = 4 max. wt (50.41%) L = 4 cascade (49.98%) filter design algorithms and clearly shows that the number of non-zero filter taps has a greater impact on the overall complexity cost than the choice of design algorithm, even after only 1 second of runtime has elapsed. Typical ADSL systems operate for much longer before re-training. By computing the design and runtime computational complexity values in Table 1, we can decide which channel shortening filter design algorithm produces the best tradeoff between shortening performance and computational complexity. 7 Simulation Results In this section, we discuss the performance of our proposed channel shortening design methods in wireline ADSL and underwater acoustic communication scenarios. For wireline channel simulations, we use the time-domain impulse

16 16 Table 3 System Parameters used in numerical simulations Parameter Value (ADSL) Value (Underwater) Sampling Rate 2.208MHz 50kHz Channel Estimate Length 128 samples 256 samples (N h ) Shortening Window (N s) 32 samples 32 samples Channel Model ADSL Carrier Serving Area Loops 1-6 Field channel measurements [26] Measured ADSL channels 1,2 [4] response from Carrier Serving Area Loop channel models as well as measured ADSL channels provided by Applied Signal Technologies [6]. For underwater acoustic simulations, we use field channel impulse response measurements available in [26]. Table 3 shows the channel shortening design parameters used in our simulations for both the wireline and underwater channels. 7.1 ADSL communication channels Figures 6 and 7 show the output SSNR performance of the proposed equalizer design methods alongside the dense equalizer design using the CSA Loop and measured ADSL channel impulse responses, respectively. These figures show that the sparse equalizer designed with 4 non-zero taps using exhaustive search matches the output performance of the dense equalizer with more than 8 taps. Furthermore, the low complexity maximal weight design approach yields almost similar shortening performance compared to the exhaustive search algorithm. Table 2 shows that the overall complexity cost of the 4 tap sparse filter is lower than that of a conventional equalizer with twice as many taps. The cascaded design approach is not particularly suited to the wireline channel scenario and its SSNR performance is poorer than the dense equalizer. In Figure 7, the SSNR performance of sparse equalizers designed using the exhaustive search algorithm with the CSA Loop channels is plotted for different values of parameter M. From Section 4, parameter M defines the maximum possible delay spread of the sparse filter and is a key parameter in the SSNR performance vs. computational complexity tradeoff. Increasing M yields a larger search space for sparse filter design and consequently improves the SSNR performance of the resultant filter, yet the size of the search space also increases combinatoriallyas ( M 1 L 1). From Figure 7 we can see that a large value for M proves beneficial when the number of non-zero taps is low and as the number of non-zero taps increases, the increase in design computational complexityfrom choosingalargevalue ofm does not offeranyssnr improvement. Figure 8 shows the computational complexity of the exhaustive search algorithm varying with the number of non-zero filter taps and the choice of parameter M. The computational complexity is defined as the design time multiplications and for the purpose of normalization, it is divided by the computational complexity of a dense filter with the same number of non-zero taps.

17 17 Output SSNR [db] Dense Optimal Sparse Exh. Search 15 Sparse Max. Weight Sparse Cascaded Number of per sample runtime multiplications Fig. 6 Output SSNR performance of channel shortening filters for ADSL CSA Loop 1-6 and measured ADSL channels vs number of per-sample runtime multiplications. Per-sample runtime multiplications are equal to the number of non-zero filter coefficients or sparse cascades depending upon the choice of filter design algorithm. M = 10 in the exhaustive search and maximum weight design algorithms and C = 8 in the cascaded sparse filter design algorithms. Figure 9 shows the SSNR performance of the maximal weight algorithm for different values of M. Figure 10 shows the normalized computational complexity of the maximal weight algorithm varying with the number of non-zero filter taps and the choice of parameter M. The output SSNR performance vs. computational complexity tradeoff for CSA Loop models is indicated in Figure 11. The design and one second of runtime multiplications are used as a measure of computational complexity. Due to high complexity requirements during runtime, the overall computations spent on channel shortening largely depend on the number of non-zero filter taps and the choice of design algorithm plays a minor role. Thus, from the performance vs. overall complexity tradeoff viewpoint, it is beneficial to choose a high complexity design algorithm that yields fewer non-zero taps in the resultant filter while maintaining an acceptable SSNR. In the wireline case, the sparse filter design with maximal weight heuristic algorithm provides the best performance vs. design computational complexity tradeoff. 7.2 Underwater communication channels The underwater channel field measurements were provided by Applied Research Laboratories at The University of Texas at Austin [26] and the system parameters for channel shortening simulations are provided in Table 3. Under-

18 Output Shortening SNR (db) Dense M = 10 M = 15 M = 20 M = 2L Non zero filter taps Fig. 7 Output SSNR performance vs. number of non-zero equalizer taps (L) using the exhaustive search design method on ADSL CSA Loop 1-6 and measured ADSL channels. M is the maximum allowable tap delay M = 10 M = 15 M = 20 M = 2L Normalized Computations Non zero filter taps Fig. 8 Normalized computational complexity of exhaustive search algorithm vs. number of non-zero filter taps (L). Normalized computational complexity is defined as the ratio of computations required for sparse filter design to computations required for dense filter design with equal number of non-zero taps. M is the maximum allowed delay spread of the sparse filter. water channels have a typical multipath nature with echo and reverberation resulting in a very large delay spread. This makes shortening equalizer design

19 Output Shortening SNR (db) Dense M = 10 M = M = 20 M = 2L Non zero filter taps Fig. 9 Output SSNR performance vs. number of non-zero equalizer taps (L) using the maximal weight design method on ADSL CSA Loop 1-6 and measured ADSL channels. M is the maximum allowable tap delay M = 10 M = 15 M = 20 M = 2L Normalized Computations Non zero filter taps Fig. 10 Normalized computational complexity of maximal weight algorithm vs. number of non-zero filter taps (L). Normalized computational complexity is defined as the ratio of computations required for sparse filter design to computations required for dense filter design with equal number of non-zero taps. M is the maximum allowed delay spread of the sparse filter. difficult since the energy of the channel is present in multiple short bursts spread out over a large delay window. In such a scenario, many of the dense

20 Output Shortening SNR (db) Dense (L=8) Sparse Cascaded (L=4, C=6) Sparse Optimal (L=4, M=10) Sparse Maximum Weight (L=4, M=10) Number of design and 1 second of runtime multiplications x 10 7 Fig. 11 Scatter plot showing shortening SNR performance vs. computational complexity tradeoff using different channel shortening filter design methods for ADSL CSA Loop channel models and measured ADSL channels. Computational complexity is defined as the multiplications required during filter design and 1 second of runtime at R = MHz. equalizer taps provide little contribution to the shortening performance of the overall equalizer. A sparse equalizer should intuitively be able to provide most of the SSNR performance of a dense equalizer at a fraction of the taps. However, a the maximum allowable delay spread needs to be very large, which can be a problem with the design algorithms that requires performing an exhaustive search over ( M 1 L 1) candidates. Fortunately, the cascaded design algorithm can achieve a large delay spread with sufficiently low complexity at the cost of SSNR sub-optimality. Figure 12 shows the performance of the sparse equalizer design methods in the presence of measured underwater channel models. It is interesting to note that the cascaded design method provides better SSNR performance than the exhaustive search. We mentioned in Section 4 that the exhaustive search is the optimal algorithm to find a sparse filter with L taps within a maximum delay of M. Therefore, at first glance the results might seem contradictory. However, the cascaded design algorithm is subtly different in that it is constrained to L two-tap filter cascades while the exhaustive search algorithm is constrained to L non-zero filter coefficients. For example, a filter designed with L cascades and maximum allowable delay spread of CL may have L non-zero taps with L L CL. This cascaded filter may have better shortening performance compared to a exhaustive search sparse filter with L non-zero taps and M = CL. However, the cascaded sparse filter is still SSNR sub-optimal compared to the exhaustive search sparse filter with L non-zero taps and M = CL. The exhaustive search algorithm is the optimal solution to (15)

21 Output SSNR [db] Dense Optimal Sparse Exh. Search Sparse Max. Weight Sparse Cascaded Number of per sample runtime multiplications Fig. 12 Output SSNR performance of channel shortening filter design method for measured undewater channel vs per-sample runtime multiplication operations. Per-sample runtime multiplications are equal to the number of filter coefficients in the dense filter design method orthe numberoftwo-tap sparsecascades inthe cascaded sparsefilterdesign method. M = 10 in the exhaustive search and maximum weight design algorithms and C = 8 in the cascaded sparse filter design algorithms. and Figure 12 does not contradict this. The performance comparison is still reasonable since the actual number of per-sample multiply and add operations are equal to L for all the candidates. Thus, inspite of it sub-optimality, the cascaded method is able to outperform the exhaustive search algorithm. The computational complexity of the sparse cascaded design algorithm for different values of C is shown in Figure 14. Figure 12 shows the performance of the cascaded equalizer for different values of parameter C. Note that the complexity of the equalizer increases linearly with C. The shortening performance vs. design computational complexity tradeoff for measured underwater channels is shown in Figure 15. Note that we only consider design stage multiplications to measure computational complexity. The cascaded sparse filter design algorithm exhibits the best tradeoff between shortening performance and computational complexity, before taking into account the considerable runtime computation savings provided by sparseness of the shortening filter. 8 Conclusions In this article, we have extended our analysis of channel shortening equalizer design using sparse filters first published in [14]. In[14], we proposed two methods of sparse filter design for channel shortening and studied their performance in ADSL communication channels. We extend our analysis of channel shorten-

22 Output Shortening SNR (db) Dense C = 1 2 C = 4 C = 8 C = Number of per sample runtime multiplications Fig. 13 Output SSNR performance vs. number of per-sample multiplications using the sparse cascaded design method in the measured underwater channel model. Per-sample runtime multiplications are equal to the number of filter coefficients in the dense filter design method or the number of two-tap sparse cascades in the cascaded sparse filter design method. C is the maximum allowable tap delay for each cascade C = 1 C = 4 C = 8 C = 12 Normalized Computations Number of two tap cascades Fig. 14 Normalized computational complexity of sparse cascaded design algorithm vs. number of cascades (L). Normalized computational complexity is defined as the ratio of computations required for sparse filter design with L cascades to computations required for dense filter design with L non-zero taps. C is the maximum allowed delay spread of each two-tap cascade.

23 Dense (L=8) Sparse Cascaded (L=6, C=6) Sparse Optimal (L=6, M=10) Sparse Maximum Weight (L=6, M=10) Output Shortening SNR (db) Number of design multiplications Fig. 15 Scatter plot showing shortening SNR performance vs. computational complexity tradeoff using different channel shortening filter design methods for measured underwater channels [26] ing equalizer design to underwater communications and propose another low complexity method of shortening equalizer design. The use of sparse filters as channel shortening equalizers provides a designer with the ability to reduce the computations spent on filtering operations while maintaining an acceptable level of communication system performance. We simulated channel shortening on ADSL and underwater communication channels. In the ADSL channels sparse equalizers were able to maintain the same level shortening performance with half as many non-zero taps as dense equalizers. Similarly, in underwater communication channels sparse equalizers were able to improve shortening performance using half as many two-tap filter cascades. This improvement in shortening performance by using sparse filters is achieved at the cost of increased design computational complexity compared to conventional dense channel shortening equalizers. We also show that the number of computations required for filtering an incoming signal far outweighs the computations required to design said filter. Thus, increased computations spent on sparse filter design are quickly amortized by the reduction in computations during filtering. For optimal sparse equalizer design, the increase in design computations may be significantly high for large filter length and delay spread, to the point of being impractical to achieve using current generation hardware. We are able to mitigate most of this design computational complexity by proposing two low complexity sub-optimal design algorithms which suffer a marginally low shortening performance loss, making them the ideal choice in the shortening performance vs. computational complexity tradeoff.

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