IR2106/IR21064 IR2107/IR21074 HIGH AND LOW SIDE DRIVER
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- Kathryn Hoover
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1 Features Floating channel designed for bootstrap operation Fully operational to +00V Tolerant to negative transient voltage dv/dt immune Gate drive supply range from 0 to 0V Undervoltage lockout for both channels chmitt triggered input logic Matched propagation delay for both channels Logic and power ground +/- V offset. Lower di/dt gate driver for better noise immunity Outputs in phase with inputs (I0/I0) Outputs out of phase with inputs (I0/I0) Description The I0/I0/I0/I0 are high voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 00 volts. Typical Connection Preliminary Data Sheet No. PD0J HIGH AND W SIDE DIVE Product Summary V OFFSET I O +/- V OUT t on/off (typ.) Delay matching Packages Lead SOIC Lead PDIP I0/I0 I0/I0 00V max. 0 ma / 0 ma 0-0V 0 ns 0 ns Lead SOIC Lead PDIP up to 00V / / TO AD up to 00V I0/I0 I0/I0 / / TO AD S S
2 I0/I0/I0/I0 Absolute Maximum atings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units High side floating absolute voltage -0. High side floating supply offset voltage V High side floating output voltage Low side and logic fixed supply voltage -0. V Low side output voltage V IN Logic input voltage ( & - I0/I0) ( & - I0/I0) S S Logic ground (I0/I0 only) d /dt Allowable offset supply voltage transient 0 V/ns P D Package power T A + C ( lead PDIP).0 ( lead SOIC) 0. ( lead PDIP). W ( lead SOIC).0 th JA Thermal resistance, junction to ambient ( lead PDIP) ( lead SOIC) 00 ( lead PDIP) C/W ( lead SOIC) 0 T J Junction temperature 0 T S Storage temperature -0 0 C T L Lead temperature (soldering, 0 seconds) 00 ecommended Operating Conditions The Input/Output logic timing diagram is shown in figure. For proper operation the device should be used within the recommended conditions. The and S offset rating are tested with all supplies biased at V differential. Symbol Definition Min. Max. Units VB High side floating supply absolute voltage High side floating supply offset voltage Note 00 V High side floating output voltage Low side and logic fixed supply voltage 0 0 V Low side output voltage 0 V V IN Logic input voltage ( & - I0/I0) ( & - I0/I0) S S Logic ground (I0/I0 only) - T A Ambient temperature -0 C V Note : Logic operational for of - to +00V. Logic state held for of -V to -S.
3 Dynamic Electrical Characteristics IAS (, S ) = V, S =, C L = 000 pf, T A = C. I0/I0/I0/I0 Symbol Definition Min. Typ. Max. Units Test Conditions ton Turn-on propagation delay 0 0 = 0V toff Turn-off propagation delay 0 0 = 0V or 00V MT Delay matching, HS & LS turn-on/off 0 0 nsec tr Turn-on rise time 0 0 = 0V tf Turn-off fall time 0 0 = 0V Static Electrical Characteristics IAS (, S ) = V, S = and T A = C unless otherwise specified. The V IL, V IH and I IN parameters are referenced to S / and are applicable to the respective input leads: and (I0/I0) and and (I0/I0). The V O, I O and on parameters are referenced to and are applicable to the respective output leads: and. Symbol Definition Min. Typ. Max. Units Test Conditions V IH Logic input voltage (I0/I0) Logic 0 input voltage (I0/I0) V IL Logic 0 input voltage (I0/I0) Logic input voltage (I0/I0). 0. V = 0V to 0V = 0V to 0V V OH High level output voltage, IAS - V O 0.. I O = 0 ma V OL Low level output voltage, V O I O = 0 ma I LK Offset supply leakage current 0 = = 00V I QBS Quiescent S supply current V IN = 0V or V I QCC Quiescent supply current ma V IN = 0V or V I IN+ Logic input bias current 0 µa V IN = V (I0()) V IN = 0V (I0()) I IN- Logic 0 input bias current V IN = 0V (I0()) V IN = V (I0()) + and S supply undervoltage positive going S+ threshold - and S supply undervoltage negative going S- threshold V H Hysteresis SH I O+ Output high short circuit pulsed current 0 00 V O = 0V, PW 0 µs I O- Output low short circuit pulsed current 0 0 ma V O = V, PW 0 µs
4 I0/I0/I0/I0 Functional Block Diagram 0 DELAY VCC VS VB FILTE HV E S Q GENEATO / / 0 DELAY VCC VS VB FILTE HV E S Q GENEATO / /
5 I0/I0/I0/I0 0 DELAY VCC VS VB FILTE HV E S Q GENEATO / / +V +V 0 DELAY VCC VS VB FILTE HV E S Q GENEATO / / +V +V
6 I0/I0/I0/I0 Lead Definitions Symbol Description Logic input for high side gate driver output (), in phase (I0/I0) Logic input for high side gate driver output (), out of phase (I0/I0) Logic input for low side gate driver output (), in phase (I0/I0) Logic input for low side gate driver output (), out of phase (I0/I0) Logic Ground (I0 and I0 only) High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return Lead Assignments Lead PDIP Lead SOIC I0 I0S Lead PDIP Lead SOIC I0 I0S
7 I0/I0/I0/I0 Lead PDIP Lead SOIC I0 I0S Lead PDIP Lead SOIC I0 I0S
8 I0/I0/I0/I0 Lead PDIP Lead SOIC
9 I0/I0/I0/I0 Lead PDIP Lead SOIC (narrow body)
10 I0/I0/I0/I0 0% 0% 0% 0% t on t r t off 90% 90% t f Figure. Input/Output Timing Diagram 0% 0% 0% 0% Figure. Switching Time Waveform Definitions 0% 0% 0% MT MT 90% Figure. Delay Matching Waveform Definitions 0 I WOLD HEADQUATES: Kansas St., El Segundo, California 90 Tel: (0) -0 I EUOPEAN EGIONAL CENTE: 9/ Godstone d., Whyteleafe, Surrey C 0BL, United Kingdom Tel: ++ (0) I JAPAN: K&H Bldg., F, 0- Nishi-Ikebukuro -Chome, Toshima-Ku, Tokyo, Japan -00 Tel: 9 00 I NG KONG: Unit 0, #F, New East Ocean Centre, No. 9 Science Museum oad, Tsimshatsui East, Kowloon Hong Kong Tel: () 0-0 Data and specifications subject to change without notice. //000
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8-Stage Static Shift Register General Description The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages.
DS Tap Silicon Delay Line FEATURES PIN ASSIGNMENT. PIN DESCRIPTION TAP 1 TAP 5 TAP Output Number +5 Volts
DS00 -Tap Silicon Delay Line FEATURES All-silicon time delay taps equally spaced Delay tolerance ± ns or ±%, whichever is greater Stable and precise over temperature and voltage range Leading and trailing
74VHC00 Quad 2-Input NAND Gate
Quad 2-Input NAND Gate General Description The HC00 is an advanced high-speed CMOS 2-Input NAND Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent
MM74HC154 4-to-16 Line Decoder
4-to-16 Line Decoder General Description The MM74HC154 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses high
MM74HC139 Dual 2-To-4 Line Decoder
MM74HC139 Dual 2-To-4 Line Decoder General Description The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications.
MM74HCT08 Quad 2-Input AND Gate
MM74HCT08 Quad 2-Input AND Gate General Description The MM74HCT08 is a logic function fabricated by using advanced silicon-gate CMOS technology which provides the inherent benefits of CMOS low quiescent
MM74HCT138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits
MM54HC244 MM74HC244 Octal TRI-STATE Buffer
MM54HC244 MM74HC244 Octal TRI-STATE Buffer General Description These TRI-STATE buffers utilize advanced silicon-gate CMOS technology and are general purpose high speed noninverting buffers They possess
MM74HC251 8-Channel 3-STATE Multiplexer
8-Channel 3-STATE Multiplexer General Description The MM74HC251 8-channel digital multiplexer with 3- STATE outputs utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and
Features Y Wide analog input voltage range g6v. Y Low on resistance 50 typ (VCC V EE e4 5V) Y Logic level translation to enable 5V logic with g5v
74VHC4051 8-Channel Analog Multiplexer 74VHC4052 Dual 4-Channel Analog Multiplexer 74VHC4053 Triple 2-Channel Analog Multiplexer General Description These multiplexers are digitally controlled analog switches
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter
MM74C00 MM74C02 MM74C04 Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter General Description The MM74C00, MM74C02, and MM74C04 logic gates employ complementary MOS (CMOS) to achieve wide power
Features. Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD40160BM CD40160BC Decade Counter with Asynchronous Clear CD40161BM CD40161BC Binary Counter with Asynchronous Clear CD40162BM CD40162BC Decade Counter with Synchronous Clear CD40163BM CD40163BC Binary
MM54HC154 MM74HC154 4-to-16 Line Decoder
MM54HC154 MM74HC154 4-to-16 Line Decoder General Description This decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications It possesses
CD74HC195. High Speed CMOS Logic 4-Bit Parallel Access Register. Features. Description. Ordering Information. PInout. [ /Title (CD74 HC195 ) /Subject
Data sheet acquired from Harris Semiconductor SCHS165 September 1997 High Speed CMOS Logic 4-Bit Parallel Access Register [ /Title (CD74 HC195 ) /Subject High peed MOS ogic -Bit aralel ccess egiser) /Autho
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear General Description The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part.
Features. Y Low power TTL Fan out of 2 driving 74L. Y 5V 10V 15V parametric ratings. Y Symmetrical output characteristics
CD4001BM CD4001BC Quad 2-Input NOR Buffered B Series Gate CD4011BM CD4011BC Quad 2-Input NAND Buffered B Series Gate General Description These quad gates are monolithic complementary MOS (CMOS) integrated