# Capacitance - 1. The parallel plate capacitor. Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV

Size: px
Start display at page:

Download "Capacitance - 1. The parallel plate capacitor. Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV"

Transcription

1 Capacitance - 1 The parallel plate capacitor Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV Charge separation in a parallel-plate capacitor causes an internal electric field. A polarized dielectric spacer (orange) reduces the electric field and increase the capacitance. The electric field (force) E between the plates of a parallel plate capacitor is uniform and given by E=V/d Source: wikipedia 1

2 Capacitance - 2 Current flow L W Electrical-field lines H t di Dielectric Substrate c int = ε t di di WL C ox εox = t ox 2 ff/μm Defined by foundry Source: Rabaey 2

3 Capacitance - 3 Source: Rabaey 3

4 Capacitance - 4 Fabrication process (CMOS) AMIS 1.5 μm IBM 0.25 μm IBM 0.13 μm Gate oxide thickness (nm) Capacitance / area (ff/μm 2 ) Source: MOSIS Source: Intel Tech. Journal 4

5 Capacitance - 5 Q = CV ; I = dq / dt = d( CV ) / dt I = CdV / dt for constant capacitance I + V - For constant V I=0, i.e. a capacitor behaves as an open circuit at dc. Capacitors are energy-storage (memory) devices used in filters, oscillators, power sources. Ideal capacitors are not dissipative (and not noisy) but charging and discharging them causes heating through dissipative devices connected to the capacitors. 5

6 The RC circuit -1 + V R - I R V + S - C + V C - KCL I = CdVC / dt = VR/ R V = V + V KVL S C R V = RCdV / dt+ V S C C Assume that V S =0fort<0, V S =Afort 0 (and V C (0)=0). VC = A 1 exp ( t/ τ ) t 0; V = 0 t < 0 C ( τ ) I = CdV / dt = Aexp t / / R t 0 C 50% t d t d =τ ln τ τ = RC 6

7 The RC circuit -2 + V R - I R V + S - C + V C - Assume that V S =0fort<0, V S =A for t 0 (and V C (0)=0). C 1 exp ( / ) ( τ ) V = A t τ I = Aexp t/ / R t 0 The power dissipation p (electric power converted into heat) in the resistor is p = RI 2 = A 2 exp 2 t / τ / R ( ) The energy converted into heat in the resistor is 2 2 A 2t CA ER = pdt = exp dt = R τ The energy stored in the capacitor (for t ) CV CA E C = = C Exercise: (a) Using the energy conservation principle calculate the energy delivered by the source. (b) Calculate the energy E S delivered by the source using the formula below ES = VSIdt 0 7

8 Simulation V R I R V + S - C 0 + V C - RC1 * this is RC1.cir file v0 1 0 dc 0 pulse 0 1V 0 10ps 10ps 10ns 20ns R 1 2 1k C 2 0 1p.end 8

9 Exercise 4.2 Run SpiceOpus to determine the voltages at the intermediate nodes 2 and 3 for the stimulus of simulation I R/2 V + S - C/2 0 R/2 C/2 3 R= 1 kω C= 1 pf SpiceOpus (c) 1 -> source RC2.cir SpiceOpus (c) 2 -> tran 0.1ns 20ns SpiceOpus (c) 3 -> setplot new New plot Current tran1rc2 (Transient Analysis) V(2) V(3) const Constant values (constants) SpiceOpus (c) 4 -> plot v(1) v(2) v(3) xlabel time[s] ylabel Outputs[V] 9

10 Comparison between exercises 4.1 and I R/2 V + S - C/2 0 R/2 C/2 3 R= 1 kω C= 1 pf 1 4 I R V + S - C 0 V(3) V(4) 10

11 Capacitance - 6 Fringing Capacitance w=w-h/2 W H thick oxide substrate t di capacitance/unit length (a) H W - H/2 + Source: Rabaey (b) 11

12 Capacitance - 7 Interwire Capacitance Crosstalk: a signal can affect another nearby signal. fringing parallel Substrate noise coupling Source: Rabaey 12

13 Capacitance - 8 Wiring Capacitances (0.25 μm CMOS) af/μm 2 af/μm Source: Rabaey 13

14 Exercise 4.3 Estimate the capacitance of the wires specified below: 1. Polysilicon, W= 0.25μm, L=1 mm; 2. Polysilicon, W= 0.25μm, L=10 mm; 3. Metal 1, W= 0.25μm, L=1 mm; 4. Metal 1, W= 0.25μm, L=10 mm. In each case, calculate the delay time assuming a lumped RC model for the wire and the capacitance with the substrate. Assume that the sheet resistances for polysilicon (with silicide) and metal 1 are 5 Ω and 0.1 Ω, respectively. CPP C fringe CPP = WL; Cfringe = L area length L C PP 2 C = 88 af/μm fringe = 54 af/μm W area length thick oxide H substrate Cwire = CPP + Cfringe Rwire t 0.69R C d wire wire L = R W Source: Rabaey 14

15 Exercise Answer 1. C wire =76 ff, R wire = 20 kω, R wire C wire = 1520 ps, t d =0.69R wire C wire =1050 ps 2. C wire =760 ff, R wire = 200 kω, R wire C wire = 152 ns, t d =0.69R wire C wire =105 ns 3. C wire =47.5 ff, R wire = 400 Ω, R wire C wire = 19 ps, t d =0.69R wire C wire =13 ps 4. C wire =475 ff, R wire = 4 kω, R wire C wire = 1.9 ns, t d =0.69R wire C wire =1.3 ns Note that the delay time increases proportionally with the square of the wire length. Why? So far we have considered that the distributed RC line can be represented by a lumped RC model (pessimistic view) and that the drive signal is a step supplied by an ideal voltage source (optimistic view). 15

16 RC delay - 1 Influence of the output resistance of the driver Driver c wi re V out Example: R driver =100 kω, and 1-μm-wide, 10-mmlong Al1 wire. What s t pd? R driver V in Source: Rabaey R wire << R driver V out C lumped C PP 2 C = 30 af/μm fringe = 40 af/μm area length CPP C fringe CPP = WL= 0.3 pf; Cfringe = L= 0.4 pf area length C = C + C = wire PP fringe t 0.69R C d driver wire 0.7 pf td 50 ns What s the approximate maximum operating frequency of the input such that the output can detect the correct value of the input? 16

17 RC delay 2: The Elmore delay -1 Elmore delay model * method to determine the approximate delay time in an RC network; it avoids running costly simulations for calculation of delay time. Useful for determining delays in transmission lines, gates, clock distribution networks, Sources: Rabaey & *W. C. Elmore, The transient response of damped linear networks with particular regard to wideband amplifiers, J. Applied Physics, vol. 19, Jan

18 RC delay 3: The Elmore delay -2 path s i R ii =R 1 +R 3 +R i path s 1 R i1 =R 1 path s 2 R i2 =R 1 path s 3 R i3 =R 1 +R 3 path s 4 R i4 =R 1 +R 3 τ = R C + R C + R C + R C + R C = Di i1 1 i2 2 i3 3 i4 4 ii i ( ) R + R + R C + RC RC ( ) ( ) R + R C R + R C i i Sources: Rabaey & *W. C. Elmore, The transient response of damped linear networks with particular regard to wideband amplifiers, J. Applied Physics, vol. 19, Jan

### Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 7 Interconnections 1: wire resistance, capacitance,

### The Wire. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Wire July 30, 2002 1 The Wire transmitters receivers schematics physical 2 Interconnect Impact on

### Digital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC.

Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction The Wire transmitters receivers schematics physical 2 Interconnect Impact

### The Wire EE141. Microelettronica

The Wire 1 Interconnect Impact on Chip 2 Example: a Bus Network transmitters receivers schematics physical 3 Wire Models All-inclusive model Capacitance-only 4 Impact of Interconnect Parasitics Interconnect

### Lecture 9: Interconnect

Digital Integrated Circuits (83-313) Lecture 9: Interconnect Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 23 May 2017 Disclaimer: This course was prepared, in its entirety,

### Digital Integrated Circuits (83-313) Lecture 5: Interconnect. Semester B, Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1

Digital Integrated Circuits (83-313) Lecture 5: Interconnect Semester B, 2015-16 Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1 What will we learn today? 1 A First Glance at Interconnect 2 3

### Interconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1

Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 James Morizio 1 Introduction Chips are mostly made of wires called interconnect In stick diagram,

### CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

### EE115C Digital Electronic Circuits Homework #5

EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, 6pm @ 56-147E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors

### Interconnects. Introduction

Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 Krish Chakrabarty 1 Introduction Chips are mostly made of ires called interconnect In stick diagram,

### E40M Capacitors. M. Horowitz, J. Plummer, R. Howe

E40M Capacitors 1 Reading Reader: Chapter 6 Capacitance A & L: 9.1.1, 9.2.1 2 Why Are Capacitors Useful/Important? How do we design circuits that respond to certain frequencies? What determines how fast

### VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large

### VLSI Design and Simulation

VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage

### EE141-Spring 2008 Digital Integrated Circuits EE141. Announcements EECS141 EE141. Lecture 24: Wires

EE141-Spring 2008 Digital Integrated Circuits Lecture 24: Wires 1 Announcements Hw 8 posted last graded homework Project phase II feedback to be expected anytime 2 Material Last Lecture: Wire capacitance

### CMPEN 411 VLSI Digital Circuits Spring 2012

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

### Lecture 12 CMOS Delay & Transient Response

EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology

### CIRCUIT ELEMENT: CAPACITOR

CIRCUIT ELEMENT: CAPACITOR PROF. SIRIPONG POTISUK ELEC 308 Types of Circuit Elements Two broad types of circuit elements Ati Active elements -capable of generating electric energy from nonelectric energy

### Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 (12.8.2013) B. Mazhari Dept. of EE, IIT Kanpur 44 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive

### and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

### 10. Performance. Summary

10. Performance Summary Interconnect Parameters: Capacitance, Resistance, Inductance Electrical Wire Models Lumped C model Lumped RC model RC chain model Distributed RC line model Transmission line model

### Chapter 10 EMT1150 Introduction to Circuit Analysis

Chapter 10 EM1150 Introduction to Circuit Analysis Department of Computer Engineering echnology Fall 2018 Prof. Rumana Hassin Syed Chapter10 Capacitors Introduction to Capacitors he Electric Field Capacitance

### Introduction to AC Circuits (Capacitors and Inductors)

Introduction to AC Circuits (Capacitors and Inductors) Amin Electronics and Electrical Communications Engineering Department (EECE) Cairo University elc.n102.eng@gmail.com http://scholar.cu.edu.eg/refky/

### ECE2262 Electric Circuits. Chapter 6: Capacitance and Inductance

ECE2262 Electric Circuits Chapter 6: Capacitance and Inductance Capacitors Inductors Capacitor and Inductor Combinations Op-Amp Integrator and Op-Amp Differentiator 1 CAPACITANCE AND INDUCTANCE Introduces

### Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay

### Digital Integrated Circuits A Design Perspective

Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures

### E40M Review - Part 1

E40M Review Part 1 Topics in Part 1 (Today): KCL, KVL, Power Devices: V and I sources, R Nodal Analysis. Superposition Devices: Diodes, C, L Time Domain Diode, C, L Circuits Topics in Part 2 (Wed): MOSFETs,

### Lecture 25. Semiconductor Memories. Issues in Memory

Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access

### A capacitor is a device that stores electric charge (memory devices). A capacitor is a device that stores energy E = Q2 2C = CV 2

Capacitance: Lecture 2: Resistors and Capacitors Capacitance (C) is defined as the ratio of charge (Q) to voltage (V) on an object: C = Q/V = Coulombs/Volt = Farad Capacitance of an object depends on geometry

### Basic RL and RC Circuits R-L TRANSIENTS: STORAGE CYCLE. Engineering Collage Electrical Engineering Dep. Dr. Ibrahim Aljubouri

st Class Basic RL and RC Circuits The RL circuit with D.C (steady state) The inductor is short time at Calculate the inductor current for circuits shown below. I L E R A I L E R R 3 R R 3 I L I L R 3 R

### Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect

Wright State University CORE Scholar Browse all Theses and Dissertations Theses and Dissertations 2014 Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect

### EE141-Spring 2007 Digital Integrated Circuits. Administrative Stuff. Last Lecture. Wires. Interconnect Impact on Chip. The Wire

EE141-Spring 2007 Digital Integrated Circuits ecture 10 Administrative Stuff No ab this week Midterm 1 on Tu! HW5 to be posted by next Friday Due Fr. March 2 5pm Introduction to wires 1 2 ast ecture ast

### ECE2262 Electric Circuits. Chapter 6: Capacitance and Inductance

ECE2262 Electric Circuits Chapter 6: Capacitance and Inductance Capacitors Inductors Capacitor and Inductor Combinations 1 CAPACITANCE AND INDUCTANCE Introduces two passive, energy storing devices: Capacitors

### UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999

UNIVERSITY OF CLIFORNI College of Engineering Department of Electrical Engineering and Computer Sciences Professor Oldham Fall 1999 EECS 40 FINL EXM 13 December 1999 Name: Last, First Student ID: T: Kusuma

### ECE 497 JS Lecture - 18 Impact of Scaling

ECE 497 JS Lecture - 18 Impact of Scaling Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements Thursday April 8 th Speaker: Prof.

### Capacitors. Chapter How capacitors work Inside a capacitor

Chapter 6 Capacitors In every device we have studied so far sources, resistors, diodes and transistors the relationship between voltage and current depends only on the present, independent of the past.

### Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 13 The CMOS Inverter: dynamic behavior (delay) guntzel@inf.ufsc.br

### Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of

### CPE/EE 427, CPE 527 VLSI Design I L13: Wires, Design for Speed. Course Administration

CPE/EE 427, CPE 527 VLSI Design I L3: Wires, Design for Speed Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-05f

### Lecture 7 Circuit Delay, Area and Power

Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:

### Homework Assignment #5 EE 477 Spring 2017 Professor Parker

Homework Assignment #5 EE 477 Spring 2017 Professor Parker Question 1: (15%) Compute the worst-case rising and falling RC time constants at point B of the circuit below using the Elmore delay method. Assume

### MODULE I. Transient Response:

Transient Response: MODULE I The Transient Response (also known as the Natural Response) is the way the circuit responds to energies stored in storage elements, such as capacitors and inductors. If a capacitor

### ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

### Lecture 15: Scaling & Economics

Lecture 15: Scaling & Economics Outline Scaling Transistors Interconnect Future Challenges Economics 2 Moore s Law Recall that Moore s Law has been driving CMOS [Moore65] Corollary: clock speeds have improved

### EECS 141: SPRING 09 MIDTERM 2

University of California College of Engineering Department of Electrical Engineering and Computer Sciences J. Rabaey WeFr 2-3:30pm We, April 22, 2:00-3:30pm EECS 141: SPRING 09 MIDTERM 2 NAME Last First

### GMU, ECE 680 Physical VLSI Design 1

ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies

### Name: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015

University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings

### Next, we check the race condition to see if the circuit will work properly. Note that the minimum logic delay is a single sum.

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on May 1, 2003 by Dejan Markovic (dejan@eecs.berkeley.edu) Prof. Jan Rabaey EECS

### MOS Transistor Theory

MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

### EECE251. Circuit Analysis I. Set 4: Capacitors, Inductors, and First-Order Linear Circuits

EECE25 Circuit Analysis I Set 4: Capacitors, Inductors, and First-Order Linear Circuits Shahriar Mirabbasi Department of Electrical and Computer Engineering University of British Columbia shahriar@ece.ubc.ca

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission

### Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually

### EECS 151/251A Spring 2018 Digital Design and Integrated Circuits. Instructors: Nick Weaver & John Wawrzynek. Lecture 12 EE141

EECS 151/251A Spring 2018 Digital Design and Integrated Circuits Instructors: Nick Weaver & John Wawrzynek Lecture 12 1 Wire Models All-inclusive model Capacitance-only 2 Capacitance Capacitance: The Parallel

### ! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines. " Where transmission lines arise? " Lossless Transmission Line.

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission

### Chapter 13. Capacitors

Chapter 13 Capacitors Objectives Describe the basic structure and characteristics of a capacitor Discuss various types of capacitors Analyze series capacitors Analyze parallel capacitors Analyze capacitive

### Lecture #39. Transistor Scaling

Lecture #39 ANNOUNCEMENT Pick up graded HW assignments and exams (78 Cory) Lecture #40 will be the last formal lecture. Class on Friday will be dedicated to a course review (with sample problems). Discussion

### Dynamic operation 20

Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69

### CMOS Transistors, Gates, and Wires

CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? pplication R P C W / R W C W / 6.375 Complex Digital Systems Christopher atten February 5, 006

### Experiment FT1: Measurement of Dielectric Constant

Experiment FT1: Measurement of Dielectric Constant Name: ID: 1. Objective: (i) To measure the dielectric constant of paper and plastic film. (ii) To examine the energy storage capacity of a practical capacitor.

### Solution: Based on the slope of q(t): 20 A for 0 t 1 s dt = 0 for 3 t 4 s. 20 A for 4 t 5 s 0 for t 5 s 20 C. t (s) 20 C. i (A) Fig. P1.

Problem 1.24 The plot in Fig. P1.24 displays the cumulative charge q(t) that has entered a certain device up to time t. Sketch a plot of the corresponding current i(t). q 20 C 0 1 2 3 4 5 t (s) 20 C Figure

### ECE520 VLSI Design. Lecture 8: Interconnect Manufacturing and Modeling. Payman Zarkesh-Ha

ECE520 VLSI Design Lecture 8: Interconnect Manufacturing and Modeling Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review

### ENGR 2405 Chapter 6. Capacitors And Inductors

ENGR 2405 Chapter 6 Capacitors And Inductors Overview This chapter will introduce two new linear circuit elements: The capacitor The inductor Unlike resistors, these elements do not dissipate energy They

### Name:... Section:... Physics 208 Quiz 8. April 11, 2008; due April 18, 2008

Name:... Section:... Problem 1 (6 Points) Physics 8 Quiz 8 April 11, 8; due April 18, 8 Consider the AC circuit consisting of an AC voltage in series with a coil of self-inductance,, and a capacitor of

### RC, RL, and LCR Circuits

RC, RL, and LCR Circuits EK307 Lab Note: This is a two week lab. Most students complete part A in week one and part B in week two. Introduction: Inductors and capacitors are energy storage devices. They

### Semiconductor Memories

Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian

### EECS 141: FALL 05 MIDTERM 1

University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

### Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

### EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania

1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 -> ESD PROTECTION CIRCUITS (INPUT PADS) -> ON-CHIP CLOCK GENERATION & DISTRIBUTION -> OUTPUT PADS -> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE -> SUPER BUFFER

### Chapter 27. Circuits

Chapter 27 Circuits 1 1. Pumping Chagres We need to establish a potential difference between the ends of a device to make charge carriers follow through the device. To generate a steady flow of charges,

### Topic 4. The CMOS Inverter

Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated

### EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology

EECS240 Spring 2013 Lecture 2: CMOS Technology and Passive Devices Lingkai Kong EECS Today s Lecture EE240 CMOS Technology Passive devices Motivation Resistors Capacitors (Inductors) Next time: MOS transistor

### University of TN Chattanooga Physics 1040L 8/18/2012 PHYSICS 1040L LAB LAB 4: R.C. TIME CONSTANT LAB

PHYSICS 1040L LAB LAB 4: R.C. TIME CONSTANT LAB OBJECT: To study the discharging of a capacitor and determine the time constant for a simple circuit. APPARATUS: Capacitor (about 24 μf), two resistors (about

### Semiconductor Memories

!"#"\$%&'()\$*#+%\$*,' -"+./"\$0 1'!*0"#)'2*+03*.\$"4* Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002 !"#\$%&'()*&'*+&, Memory Classification Memory Architectures

### EECS 151/251A Homework 5

EECS 151/251A Homework 5 Due Monday, March 5 th, 2018 Problem 1: Timing The data-path shown below is used in a simple processor. clk rd1 rd2 0 wr regfile 1 0 ALU REG 1 The elements used in the design have

### Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics

Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance

### Phys 2025, First Test. September 20, minutes Name:

Phys 05, First Test. September 0, 011 50 minutes Name: Show all work for maximum credit. Each problem is worth 10 points. Work 10 of the 11 problems. k = 9.0 x 10 9 N m / C ε 0 = 8.85 x 10-1 C / N m e

### Interconnect (2) Buffering Techniques. Logical Effort

Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18-322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The check-off is due today (by 9:30PM) Students

### Lecture #3. Review: Power

Lecture #3 OUTLINE Power calculations Circuit elements Voltage and current sources Electrical resistance (Ohm s law) Kirchhoff s laws Reading Chapter 2 Lecture 3, Slide 1 Review: Power If an element is

### Chapt ha e pt r e r 9 Capacitors

Chapter 9 Capacitors Basics of a Capacitor In its simplest form, a capacitor is an electrical device constructed of two parallel plates separated by an insulating material called the dielectric In the

### Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

### ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.

### Louisiana State University Physics 2102, Exam 2, March 5th, 2009.

PRINT Your Name: Instructor: Louisiana State University Physics 2102, Exam 2, March 5th, 2009. Please be sure to PRINT your name and class instructor above. The test consists of 4 questions (multiple choice),

### Chapter 4 Transients. Chapter 4 Transients

Chapter 4 Transients Chapter 4 Transients 1. Solve first-order RC or RL circuits. 2. Understand the concepts of transient response and steady-state response. 1 3. Relate the transient response of first-order

### Elements of Circuit Analysis

ARSLAB - Autonomous and Robotic Systems Laboratory Dipartimento di Matematica e Informatica - Università di Catania, Italy santoro@dmi.unict.it L.A.P. 1 Course Basic Element of Direct Current (DC) Circuits

### ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft

ELEN0037 Microelectronic IC Design Prof. Dr. Michael Kraft Lecture 2: Technological Aspects Technology Passive components Active components CMOS Process Basic Layout Scaling CMOS Technology Integrated

### PASS-TRANSISTOR LOGIC. INEL Fall 2014

PASS-TRANSISTOR LOGIC INEL 4207 - Fall 2014 Figure 15.5 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between

### Inductance, Inductors, RL Circuits & RC Circuits, LC, and RLC Circuits

Inductance, Inductors, RL Circuits & RC Circuits, LC, and RLC Circuits Self-inductance A time-varying current in a circuit produces an induced emf opposing the emf that initially set up the timevarying

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CAIFORNIA, BERKEEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #7 - Solutions EECS141 Due Thursday, October 22, 5pm, box in 240 Cory

### EE292: Fundamentals of ECE

EE292: Fundamentals of ECE Fall 2012 TTh 10:00-11:15 SEB 1242 Lecture 14 121011 http://www.ee.unlv.edu/~b1morris/ee292/ 2 Outline Review Steady-State Analysis RC Circuits RL Circuits 3 DC Steady-State

### Characteristics of Passive IC Devices

008/Oct 8 esistors Characteristics of Passive IC Devices Poly esistance Diffusion esistance Well esistance Parasitic esistance Capacitors Poly Capacitors MOS Capacitors MIM Capacitors Parasitic Capacitors

### Chapter 2. Engr228 Circuit Analysis. Dr Curtis Nelson

Chapter 2 Engr228 Circuit Analysis Dr Curtis Nelson Chapter 2 Objectives Understand symbols and behavior of the following circuit elements: Independent voltage and current sources; Dependent voltage and

### Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

### VLSI Design I; A. Milenkovic 1

ourse dministration PE/EE 47, PE 57 VLSI Design I L3: Wires, Design for Speed Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic (.ece.uah.edu/~milenka

### ENERGY AND TIME CONSTANTS IN RC CIRCUITS By: Iwana Loveu Student No Lab Section: 0003 Date: February 8, 2004

ENERGY AND TIME CONSTANTS IN RC CIRCUITS By: Iwana Loveu Student No. 416 614 5543 Lab Section: 0003 Date: February 8, 2004 Abstract: Two charged conductors consisting of equal and opposite charges forms

### ENEE 359a Digital VLSI Design

SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay

### PURPOSE: See suggested breadboard configuration on following page!

ECE4902 Lab 1 C2011 PURPOSE: Determining Capacitance with Risetime Measurement Reverse Biased Diode Junction Capacitance MOSFET Gate Capacitance Simulation: SPICE Parameter Extraction, Transient Analysis

### Capacitance. A capacitor consists of two conductors that are close but not touching. A capacitor has the ability to store electric charge.

Capacitance A capacitor consists of two conductors that are close but not touching. A capacitor has the ability to store electric charge. a) Parallel-plate capacitor connected to battery. (b) is a circuit

### Capacitance, Resistance, DC Circuits

This test covers capacitance, electrical current, resistance, emf, electrical power, Ohm s Law, Kirchhoff s Rules, and RC Circuits, with some problems requiring a knowledge of basic calculus. Part I. Multiple

### Handout 10: Inductance. Self-Inductance and inductors

1 Handout 10: Inductance Self-Inductance and inductors In Fig. 1, electric current is present in an isolate circuit, setting up magnetic field that causes a magnetic flux through the circuit itself. This