Capacitance - 1. The parallel plate capacitor. Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV

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1 Capacitance - 1 The parallel plate capacitor Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV Charge separation in a parallel-plate capacitor causes an internal electric field. A polarized dielectric spacer (orange) reduces the electric field and increase the capacitance. The electric field (force) E between the plates of a parallel plate capacitor is uniform and given by E=V/d Source: wikipedia 1

2 Capacitance - 2 Current flow L W Electrical-field lines H t di Dielectric Substrate c int = ε t di di WL C ox εox = t ox 2 ff/μm Defined by foundry Source: Rabaey 2

3 Capacitance - 3 Source: Rabaey 3

4 Capacitance - 4 Fabrication process (CMOS) AMIS 1.5 μm IBM 0.25 μm IBM 0.13 μm Gate oxide thickness (nm) Capacitance / area (ff/μm 2 ) Source: MOSIS Source: Intel Tech. Journal 4

5 Capacitance - 5 Q = CV ; I = dq / dt = d( CV ) / dt I = CdV / dt for constant capacitance I + V - For constant V I=0, i.e. a capacitor behaves as an open circuit at dc. Capacitors are energy-storage (memory) devices used in filters, oscillators, power sources. Ideal capacitors are not dissipative (and not noisy) but charging and discharging them causes heating through dissipative devices connected to the capacitors. 5

6 The RC circuit -1 + V R - I R V + S - C + V C - KCL I = CdVC / dt = VR/ R V = V + V KVL S C R V = RCdV / dt+ V S C C Assume that V S =0fort<0, V S =Afort 0 (and V C (0)=0). VC = A 1 exp ( t/ τ ) t 0; V = 0 t < 0 C ( τ ) I = CdV / dt = Aexp t / / R t 0 C 50% t d t d =τ ln τ τ = RC 6

7 The RC circuit -2 + V R - I R V + S - C + V C - Assume that V S =0fort<0, V S =A for t 0 (and V C (0)=0). C 1 exp ( / ) ( τ ) V = A t τ I = Aexp t/ / R t 0 The power dissipation p (electric power converted into heat) in the resistor is p = RI 2 = A 2 exp 2 t / τ / R ( ) The energy converted into heat in the resistor is 2 2 A 2t CA ER = pdt = exp dt = R τ The energy stored in the capacitor (for t ) CV CA E C = = C Exercise: (a) Using the energy conservation principle calculate the energy delivered by the source. (b) Calculate the energy E S delivered by the source using the formula below ES = VSIdt 0 7

8 Simulation V R I R V + S - C 0 + V C - RC1 * this is RC1.cir file v0 1 0 dc 0 pulse 0 1V 0 10ps 10ps 10ns 20ns R 1 2 1k C 2 0 1p.end 8

9 Exercise 4.2 Run SpiceOpus to determine the voltages at the intermediate nodes 2 and 3 for the stimulus of simulation I R/2 V + S - C/2 0 R/2 C/2 3 R= 1 kω C= 1 pf SpiceOpus (c) 1 -> source RC2.cir SpiceOpus (c) 2 -> tran 0.1ns 20ns SpiceOpus (c) 3 -> setplot new New plot Current tran1rc2 (Transient Analysis) V(2) V(3) const Constant values (constants) SpiceOpus (c) 4 -> plot v(1) v(2) v(3) xlabel time[s] ylabel Outputs[V] 9

10 Comparison between exercises 4.1 and I R/2 V + S - C/2 0 R/2 C/2 3 R= 1 kω C= 1 pf 1 4 I R V + S - C 0 V(3) V(4) 10

11 Capacitance - 6 Fringing Capacitance w=w-h/2 W H thick oxide substrate t di capacitance/unit length (a) H W - H/2 + Source: Rabaey (b) 11

12 Capacitance - 7 Interwire Capacitance Crosstalk: a signal can affect another nearby signal. fringing parallel Substrate noise coupling Source: Rabaey 12

13 Capacitance - 8 Wiring Capacitances (0.25 μm CMOS) af/μm 2 af/μm Source: Rabaey 13

14 Exercise 4.3 Estimate the capacitance of the wires specified below: 1. Polysilicon, W= 0.25μm, L=1 mm; 2. Polysilicon, W= 0.25μm, L=10 mm; 3. Metal 1, W= 0.25μm, L=1 mm; 4. Metal 1, W= 0.25μm, L=10 mm. In each case, calculate the delay time assuming a lumped RC model for the wire and the capacitance with the substrate. Assume that the sheet resistances for polysilicon (with silicide) and metal 1 are 5 Ω and 0.1 Ω, respectively. CPP C fringe CPP = WL; Cfringe = L area length L C PP 2 C = 88 af/μm fringe = 54 af/μm W area length thick oxide H substrate Cwire = CPP + Cfringe Rwire t 0.69R C d wire wire L = R W Source: Rabaey 14

15 Exercise Answer 1. C wire =76 ff, R wire = 20 kω, R wire C wire = 1520 ps, t d =0.69R wire C wire =1050 ps 2. C wire =760 ff, R wire = 200 kω, R wire C wire = 152 ns, t d =0.69R wire C wire =105 ns 3. C wire =47.5 ff, R wire = 400 Ω, R wire C wire = 19 ps, t d =0.69R wire C wire =13 ps 4. C wire =475 ff, R wire = 4 kω, R wire C wire = 1.9 ns, t d =0.69R wire C wire =1.3 ns Note that the delay time increases proportionally with the square of the wire length. Why? So far we have considered that the distributed RC line can be represented by a lumped RC model (pessimistic view) and that the drive signal is a step supplied by an ideal voltage source (optimistic view). 15

16 RC delay - 1 Influence of the output resistance of the driver Driver c wi re V out Example: R driver =100 kω, and 1-μm-wide, 10-mmlong Al1 wire. What s t pd? R driver V in Source: Rabaey R wire << R driver V out C lumped C PP 2 C = 30 af/μm fringe = 40 af/μm area length CPP C fringe CPP = WL= 0.3 pf; Cfringe = L= 0.4 pf area length C = C + C = wire PP fringe t 0.69R C d driver wire 0.7 pf td 50 ns What s the approximate maximum operating frequency of the input such that the output can detect the correct value of the input? 16

17 RC delay 2: The Elmore delay -1 Elmore delay model * method to determine the approximate delay time in an RC network; it avoids running costly simulations for calculation of delay time. Useful for determining delays in transmission lines, gates, clock distribution networks, Sources: Rabaey & *W. C. Elmore, The transient response of damped linear networks with particular regard to wideband amplifiers, J. Applied Physics, vol. 19, Jan

18 RC delay 3: The Elmore delay -2 path s i R ii =R 1 +R 3 +R i path s 1 R i1 =R 1 path s 2 R i2 =R 1 path s 3 R i3 =R 1 +R 3 path s 4 R i4 =R 1 +R 3 τ = R C + R C + R C + R C + R C = Di i1 1 i2 2 i3 3 i4 4 ii i ( ) R + R + R C + RC RC ( ) ( ) R + R C R + R C i i Sources: Rabaey & *W. C. Elmore, The transient response of damped linear networks with particular regard to wideband amplifiers, J. Applied Physics, vol. 19, Jan