Discussions start next week Labs start in week 3 Homework #1 is due next Friday
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1 EECS141 1 Discussions start next week Labs start in week 3 Homework #1 is due next Friday Everyone should have an EECS instructional account Use cory, quasar, pulsar EECS
2 CMOS LEAKAGE CHARACTERIZATION X1 0 1 nvdd1 INVERTER X2 nvdd 2 nvdd2 INVERTER VDDS nvdd VDDN nvdd nvdd1 0 VDDP nvdd nvdd2 0.subckt INVERTER nin nout nsupply X1 nout nin 0 0 nsvt W=0.15 L=0.1 X2 nout nin nsupply nsupply psvt W=0.3 L=0.1.ends INVERTER * Commands.dc VDDS print i(vddn), i(vddp).options brief.lib '..\..\Models\65nmCMOS.lib' svt_tt.end Born in the days of punched cards EECS141 3 Last lecture Introduction, Moore s law, future of ICs Today s lecture Introduces basic metrics for design of integrated circuits How to measure cost? Intro to IC manufacturing EECS
3 How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Speed/Performance (delay, frequency) Power EECS141 5 NRE (non-recurrent engineering) costs - fixed Independent of volume (i.e., number of units made/sold) Examples: design time and effort, mask generation, equipment, etc. Recurrent costs - variable proportional to volume Examples: silicon processing, packaging, test Most of these proportional to chip area EECS
4 EECS141 7 Polysilicon Aluminum 8 EECS
5 The image cannot be displayed. Your computer may not have enough memory to optical mask oxidation The image cannot be displayed. Your computer The image cannot be displayed. Your computer may not have enough memory to The T h The imag e cann ot be displ photoresist removal (ashing) The image cannot be displayed. Your computer may not have enough memory to open the image, or the photoresist coating stepper exposure Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process step spin, rinse, dry The image cannot be displaye d. Your compute r may The imag e cann ot be displ EECS141 The image cannot be displayed. Your computer may 9 Chemical or plasma etch Si-substrate Hardened resist SiO 2 (a) Silicon base material Si-substrate Photoresist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 Si-substrate Hardened resist SiO 2 (b) After oxidation and deposition of negative photoresist Si-substrate UV-light Patterned optical mask (e) After etching Exposed resist SiO 2 Si-substrate Si-substrate (c) Stepper exposure EECS141 (f) Final result after removal of resist 10 5
6 EECS EECS
7 EECS NRE (non-recurrent engineering) costs - fixed Independent of volume (i.e., number of units made/sold) Examples: design time and effort, mask generation, equipment, etc. Recurrent costs - variable proportional to volume Examples: silicon processing, packaging, test Most of these proportional to chip area EECS
8 EECS ,000,000 10,000 1,000,000 1, , , , Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000, ,000 10,000 1, Complexity Logic Transistor per Chip (M) Productivity (K) Trans./Staff - Mo Source: Sematech Complexity outpaces design productivity Courtesy, ITRS Roadmap EECS
9 Cost per IC Variable cost EECS Wafer Single die From: EECS
10 AMD Athlon 8 (200mm) 12 (300mm) 12 (300mm) 90nm CMOS 90nm CMOS 65nm CMOS Next: 18 Wafers? From: EECS G. Moore, Keynote Address ISSCC 2003 EECS
11 EECS Yield = 1/4 Yield = 19/24 where α is approximately 3 EECS
12 Fabrication cost per transistor EECS The real world is analog All physical quantities you deal with as a circuit designer are actually continuous Thus, even a digital signal can be noisy: i ( t ) v ( t ) V DD Inductive coupling Capacitive coupling Power and ground noise EECS
13 Circuit needs to works despite analog noise Digital gates can reject noise This is actually how digital systems are defined Digital system is one where: Discrete values mapped to analog levels and back All the elements (gates) can reject noise For small amounts of noise, output noise is less than input noise Thus, for sufficiently small noise, the system acts as if it was noiseless EECS To see if a gate rejects noise Look at its DC voltage transfer characteristic (VTC) See what happens when input is not exactly 1 or 0 Ideal digital gate: Noise needs to be larger than V DD /2 to have any effect on gate output V DD V out Gain = 0 Gain = Gain = 0 V DD /2 V DD EECS V in 13
14 VOH = f(vol) VOL = f(voh) VM = f(vm) Switching Threshold Nominal Voltage Levels EECS V OH V out V OH Slope = -1 V IH Undefined Region V IL Slope = -1 0 V OL V OL V IL V IH V in EECS
15 1 V OH V OL NM H Undefined Region NM L V IH V IL Noise margin high: NM H = V OH V IH Noise margin low: NM L = V IL V OL 0 Gate Output (Stage M) Gate Input (Stage M+1) EECS v 0 v 1 v 2 v 3 v 4 v 5 v 6 A chain of inverters Simulated response EECS
16 Regenerative Non-Regenerative EECS N M Fan-out N Fan-in M There is a modified definition of fan-out for CMOS logic EECS
17 Absolute noise margin values are not the only things that matter e.g., floating (high impedance) nodes are more easily disturbed than low impedance nodes (in terms of voltage) Noise immunity (i.e., how well the gate suppresses noise sources) needs to be considered too Summary of some key reliability metrics: Noise transfer functions & margin (ideal: gain =, margin = V dd /2) Output impedance (ideal: R o = 0) Input impedance (ideal: R i = ) EECS NM L V out (V) 3.0 V M 1.0 NM H V (V) in EECS
18 V OH = 3.6V V OL = 0.4V V IL = 0.6V V IH = 2.3V NM H = V OH V IH = 1.3V NM L = V IL V OL = 0.2V EECS Understanding the design metrics that govern digital design is crucial We discussed cost and reliability so far Key design messages so far: Keep chip area as small as possible Pick design styles and parameters so that noise margins are reasonable EECS
19 Performance and energy A first glance at an inverter EECS
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