POWER SUPPLY INDUCED JITTER MODELING OF AN ON- CHIP LC OSCILLATOR. Shahriar Rokhsaz, Jinghui Lu, Brian Brunn
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1 POWER SUPPY INDUED JITTER MODEING OF AN ON- HIP OSIATOR Shahriar Rokhsaz, Jinghui u, Brian Brunn Rockethips Inc. (A Xilinx, Inc. Division) ABSTRAT This paper concentrates on developing a closed-form small signal model to determine the Power Supply Induced Jitter (PSIJ) for on chip based Voltage ontrolled Oscillator (VO). To determine the source of the PSIJ, we have developed a Mathcad model which is used to optimize the VO design in order to achieve the lowest possible jitter allowed by its architecture. I. INTRODUTION With high bandwidth demand in the telecommunication and networking area, low voltage and low jitter Phase ock oop (P) is becoming of utmost importance. As the data rate becomes faster, the total jitter budget gets smaller. For instance, an O-9 transceiver compliant is allowed less than ps of total jitter due to random noise (rms jitter) and a maximum of 0ps for the deterministic jitter. Therefore, predicting jitter induced both via power supply and random noise using simulation and modeling becomes crucial. In this paper we first discuss the startup condition of an VO oscillator. Next, we briefly touch on the on-chip inductance and varactor structures used in our modeling. Then, we derive a small signal model for the VO. Finally, we discuss the manner in which the power supply noise gets coupled to the output of the VO causing power supply induced jitter. with an inductor connected to its drain. This circuit has a small signal gain of Av Av Gm ( ) () Av ( s) Av ( s) Gm () + + s s Av ( s) Av ( s) Gm s (3) + s + s r out Where Gm and are the transconductance and the output resistance of M and M transistors respectively, / is the total output capacitance at the outputs and. For this circuit to oscillate, the gain around the loop must be equal to negative one; therefore, each crossed coupled gain stage can be presented as shown in figure.c. Hence, the total gain equation around the loop is equal to Av ( s) H( s) (4) Av ( s) / M M / II. STARTUP ONDITION AND OSIATION To understand the behavior of an oscillator at the oscillation frequency and the way any disturbance in the power supply affects the output wave form, we will briefly explain the basic operation of the VO, and the manner it oscillates. Figure.a. shows a simplified cross coupled VO with ideal inductors (no resistance). This circuit can be viewed as two gain stages cross coupled (figure.b) where each gain stage consists of an N-MOS Figure.a. Ideal VO AV / / AV Figure.b. VO equivalent
2 - inductance (), our model calculates an optimum inductor. The optimization criterion is maximum Q. Figure depicts a detailed smith chart plot of a 4nH inductance predicted by our model versus a fabricated on-chip inductance in TSM 0.8µ process. M Figure.c. VO equivalent at oscillating frequency Substituting for Av (s) Gm s + s + s H( s) (5) Gm s + s + s Gm s s ( Gm G out ) + s For this circuit to oscillate at ( ω osc ), it is necessary for the s term in the denominator (5) to be equal to zero; hence, Gm G out (6) By forcing Gm greater than G out a pair of complex poles are forced in the right side plane. This is the condition to start oscillation. Once the oscillation starts, the G eff parameter ( G Gm G ) approaches zero; hence, the eff out oscillation sustains. Furthermore, the Q of the circuit is Q R eff (7) G eff III. ON-HIP INDUTOR AND VARATOR MODE We developed closed-form equations for the series inductance (), series resistance ( ), the overlap capacitance ( O ), the capacitance from the inductor trace to substrate ( ox ), the parasitic resistance and capacitance associated with the substrate (i & si ) ( refer to figure 4). is calculated using a slightly modified version of the Greenhouse method [3]. is calculated using the process metal sheet-resistance and includes the increased resistance due to skin effect. ox is calculated directly from the inductor geometry and process parameters. i and si are empirical fitting parameters. For a given desired Figure.. Measured vs. modeled behavior of a 4nH on-chip inductor (TSM 0.8µ) For frequency tuning purposes, an accumulation mode varactor is used ( Tune ). The varactor is modeled as a transistor in an n-well structure with the n+ source and drain diffusions. In closed-form, the varactor is modeled as a resistance in series with an ideal variable capacitor. The resistance is derived directly from the geometry and process parameters. There is a slight increase in the well resistance as the capacitance is decreased; however, in a properly sized device, this variation is typically insignificant. We modeled the capacitance as a hyperbolic tangent function fit to measured data. At zero D voltage the capacitance is approximately 80% of max (typical max / min ratios exceed 3). Figure 3 depicts a measured versus modeled behavior of the varactor in TSM 0.8µ process. cap [pf] Meas FIT -5 dbm Wtot408u 0.38u n7 m3 FIT *(+tanh((V+0.5)/0.58)) Vgate Figure 3. Measured vs. Mathcad modeled for varactor (TSM 0.8µ)
3 IV. SMA SIGNA MODE Figure 4. depicts a typical on-chip VO with all its parasitics shown. Our approach is to simplify this fully balanced circuit in to its R equivalent via a half-circuit method. ox On-hip Inductor o ox m o ox par ( ω, Vds) er ( ω, V ds ) + er ( ω, V ds ) ser ( V ds) ω R () ser ( V ds ) par ( ω, V ds ) er ( ω, V ds ) ser ( V ds ) ω + () Figure 6 shows the small signal equivalent of the VO, where R p and p are the equivalent series to parallel converted parasitic impedance due to the on-chip inductor ( ox, i, and si ) seen from the outputs of the VO [4]. The parasitic seen at the drain of the current source is not included in our model since this node is a virtual ground as far as the differential output is concerned, and it has no significant effect on the common mode signal. Furthermore, gd, par, R p, and R par are converted to their half-circuit equivalents. i si i si i si Tune Tune o Virtual Ground o tune tune ds gd gd M M ds gd gd Virtual Ground gd gd gs gs p p Figure 4. On-chip VO par par First, we find an equivalent impedance model of the cross coupled transistor by finding the impedance looking between its gate and drain as shown in figure 5 [4]. The equivalent impedance is a series combination of resistor er and ser R par /4 R p / R par /4 R p / Z in ( ω ) er ( ω, V ds ) + ser ( Vds ) (8) Gm er ( ω, V ds ) (9) ds ( V ds ) gs ω ser ( V ds ) (0) ds ( V ds ) + gs Where ds (V ds ) capacitance is a function of the voltage across M s drain to source. Virtual Ground paracitics R tune Figure 6. Equivalent small signal representation of VO V. POWER SUPPY INDUED JITTER (PSIJ) Zin M ds gs Figure 5. Impedance looking in to the transistor Figure 7 depicts the half-circuit representation of the VO. Where Z cs, is the impedance looking in to the drain of the current source, Z inductor is the total impedance of the inductor, and Z par is the parallel combination of the varactor, total resistance and total parasitic capacitance. To construct the half-circuit, this impedance is converted in a parallel combination of R par, and par
4 Z cs ( ω) (3) + jω Gm p 0 r p 0 r p Z inductor ( ω) (4) + O jω ( jω + ) Z par ( ω, V Tune, V ds ) (5) paracitic ( V ds ) + Tune ( V Tune ) + R l VTune V out (6) impedance voltage source used to drive the varactor. The ac voltage hit seen at the output of this driver is R cntleq V vdd _ cntrl Z pvi + R cntleq _ ac (8) Where Rcntleq (9) + Rvi Rn Z pvi (0) + pvi jω Gm r r3 Bias N _ac M p m Bias pch0 Z cs M 3 M p0 Bias M o Z inductor Rs output node of circuit R vi M n parasitic Z par Tune R Figure 8. Output stage of the voltage driver Figure 7. Half-circuit We are assuming a sinusoidal hit on the power supply at ω c frequency (_ac ). The amount of the _ac which gets through to the output, is determined by the ratio of the impedance looking in to the output, towards and terminals. This signal will disturb the output as an additive noise as follows _ ac Z par ( ω ) V osc additive _ Vdd (7) Z cs ( ωc) + Z inductor ( ωosc) + Z par ( ωosc, V Tune, V ds) As (7) indicates, the frequency at which the VO oscillates determines the impedance seen from the output of the VO to the drain of the current source and the terminal. The only impedance determined by ω c is the one of the current source. The second cause of the induced jitter is contributed from the voltage control circuitry which sets the voltage across the varactor ( V ). Figure 8 shows a simple low vdd _ cntrl The total voltage change across the varactor ( V V V ) will result in a change in the vdd additive _ vdd vdd _ cntrl effective capacitance value Tune while V additive_vdd changes the ds (V ds ) value. This causes a change in the total capacitance forcing the oscillating frequency to deviate from its nominal frequency; hence, a frequency push ( ω ( V ) + ( V ) ). osc ds ds Tune Tune We predict the peak phase variation of the output frequency by calculating the difference between the nominal oscillating frequency and the frequency to which the oscillator has been pushed to, divided by the power supply hit s frequency ωosc ω pushed ω φvdd _ push () ωc ωc Furthermore, to find out the instantaneous frequency jitter, we normalize the phase shift to the nominal frequency. φvdd _ push τ PSIJ _ vdd () ωosc The same procedure can be followed to determine the jitter induced by a hit. The effect of the same hit from the terminal is much more severe than its counter part,
5 since the impedance seen from the output of the VO is small at the oscillating frequency. Therefore, a large percentage of the bounce gets through to the output of the VO, causing the ds (V ds ) capacitance value to change dramatically; hence, a larger frequency push. To measure the amount of the frequency pushed (in turn PSIJ) via and, we are assuming a 0% of the supply voltage hit on each supply separately (_ac _ac 80mVp-p). Figure 9 and figure 0 depict our modeled results. To achieve a low jitter P, these figures can be used to analyze the over all jitter performance [4]. Hz ω ( ω ) Frequency Pushed due to Vdd ω Frequency (Rad) VII. REFERENE [] J. N. Burghartz, RF ircuit Design Aspects of Spiral Inductors on silicon IEEE Journal of Solid State ircuit, Vol. 33, No., May 998, PP: [] J. raninckx, M. Steyaert ow Noise Voltage ontrolled Oscillator Using Enhanced -Tank IEEE Transaction on circuit and Systems, Vol. 4, No., Dec 995, PP: [3] H. M. Greenhouse, Design of planar rectangular microelectronic inductors, IEEE Trans. Parts, Hybrids & Packaging, vol. PHP-0, pp. 0-09, June 974. [4] J. u, S. Rokhsaz, B. Grung, S. Anderson Discrete Z- Domain Analysis of High Order Phase ocked oops,isaas, May 00, to be published. [5]. Patrick Yue, S.S. Wong On-hip Spiral Inductors with Patterned Ground Shield for Si-Based RF I s IEEE Journal of Solid State ircuit, Vol. 33, No. 5, May 998, PP: [6] Behzad Rasavi RF Microelectronics Prentice Hall, Inc.. Figure 9. Frequency push due to 80mVpp hit on Frequency Pushed due to Vss Hz ω ( ω ) ω Frequency (Rad) Figure. 0. Frequency push due to 80mVpp hit on VI. ONUSION A closed-form solution predicting the total jitter due to ripple on the power supplies has been developed. Using this closed-form solution, we used Mathcad to model and optimize the VO under investigation. Furthermore, we compared our results with the results of the Spectre RF simulator and found both our model and Spectre RF are in agreement. This modeling technique can be used to determine PSIJ in any VO topology besides the one discussed in this paper. Acknowledgement Authors would like to thank Moises Robinson and Mike Gaboury along with all of the Rockethips members for their valuable inputs throughout the development of this paper.
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