POWER SUPPLY INDUCED JITTER MODELING OF AN ON- CHIP LC OSCILLATOR. Shahriar Rokhsaz, Jinghui Lu, Brian Brunn

Size: px
Start display at page:

Download "POWER SUPPLY INDUCED JITTER MODELING OF AN ON- CHIP LC OSCILLATOR. Shahriar Rokhsaz, Jinghui Lu, Brian Brunn"

Transcription

1 POWER SUPPY INDUED JITTER MODEING OF AN ON- HIP OSIATOR Shahriar Rokhsaz, Jinghui u, Brian Brunn Rockethips Inc. (A Xilinx, Inc. Division) ABSTRAT This paper concentrates on developing a closed-form small signal model to determine the Power Supply Induced Jitter (PSIJ) for on chip based Voltage ontrolled Oscillator (VO). To determine the source of the PSIJ, we have developed a Mathcad model which is used to optimize the VO design in order to achieve the lowest possible jitter allowed by its architecture. I. INTRODUTION With high bandwidth demand in the telecommunication and networking area, low voltage and low jitter Phase ock oop (P) is becoming of utmost importance. As the data rate becomes faster, the total jitter budget gets smaller. For instance, an O-9 transceiver compliant is allowed less than ps of total jitter due to random noise (rms jitter) and a maximum of 0ps for the deterministic jitter. Therefore, predicting jitter induced both via power supply and random noise using simulation and modeling becomes crucial. In this paper we first discuss the startup condition of an VO oscillator. Next, we briefly touch on the on-chip inductance and varactor structures used in our modeling. Then, we derive a small signal model for the VO. Finally, we discuss the manner in which the power supply noise gets coupled to the output of the VO causing power supply induced jitter. with an inductor connected to its drain. This circuit has a small signal gain of Av Av Gm ( ) () Av ( s) Av ( s) Gm () + + s s Av ( s) Av ( s) Gm s (3) + s + s r out Where Gm and are the transconductance and the output resistance of M and M transistors respectively, / is the total output capacitance at the outputs and. For this circuit to oscillate, the gain around the loop must be equal to negative one; therefore, each crossed coupled gain stage can be presented as shown in figure.c. Hence, the total gain equation around the loop is equal to Av ( s) H( s) (4) Av ( s) / M M / II. STARTUP ONDITION AND OSIATION To understand the behavior of an oscillator at the oscillation frequency and the way any disturbance in the power supply affects the output wave form, we will briefly explain the basic operation of the VO, and the manner it oscillates. Figure.a. shows a simplified cross coupled VO with ideal inductors (no resistance). This circuit can be viewed as two gain stages cross coupled (figure.b) where each gain stage consists of an N-MOS Figure.a. Ideal VO AV / / AV Figure.b. VO equivalent

2 - inductance (), our model calculates an optimum inductor. The optimization criterion is maximum Q. Figure depicts a detailed smith chart plot of a 4nH inductance predicted by our model versus a fabricated on-chip inductance in TSM 0.8µ process. M Figure.c. VO equivalent at oscillating frequency Substituting for Av (s) Gm s + s + s H( s) (5) Gm s + s + s Gm s s ( Gm G out ) + s For this circuit to oscillate at ( ω osc ), it is necessary for the s term in the denominator (5) to be equal to zero; hence, Gm G out (6) By forcing Gm greater than G out a pair of complex poles are forced in the right side plane. This is the condition to start oscillation. Once the oscillation starts, the G eff parameter ( G Gm G ) approaches zero; hence, the eff out oscillation sustains. Furthermore, the Q of the circuit is Q R eff (7) G eff III. ON-HIP INDUTOR AND VARATOR MODE We developed closed-form equations for the series inductance (), series resistance ( ), the overlap capacitance ( O ), the capacitance from the inductor trace to substrate ( ox ), the parasitic resistance and capacitance associated with the substrate (i & si ) ( refer to figure 4). is calculated using a slightly modified version of the Greenhouse method [3]. is calculated using the process metal sheet-resistance and includes the increased resistance due to skin effect. ox is calculated directly from the inductor geometry and process parameters. i and si are empirical fitting parameters. For a given desired Figure.. Measured vs. modeled behavior of a 4nH on-chip inductor (TSM 0.8µ) For frequency tuning purposes, an accumulation mode varactor is used ( Tune ). The varactor is modeled as a transistor in an n-well structure with the n+ source and drain diffusions. In closed-form, the varactor is modeled as a resistance in series with an ideal variable capacitor. The resistance is derived directly from the geometry and process parameters. There is a slight increase in the well resistance as the capacitance is decreased; however, in a properly sized device, this variation is typically insignificant. We modeled the capacitance as a hyperbolic tangent function fit to measured data. At zero D voltage the capacitance is approximately 80% of max (typical max / min ratios exceed 3). Figure 3 depicts a measured versus modeled behavior of the varactor in TSM 0.8µ process. cap [pf] Meas FIT -5 dbm Wtot408u 0.38u n7 m3 FIT *(+tanh((V+0.5)/0.58)) Vgate Figure 3. Measured vs. Mathcad modeled for varactor (TSM 0.8µ)

3 IV. SMA SIGNA MODE Figure 4. depicts a typical on-chip VO with all its parasitics shown. Our approach is to simplify this fully balanced circuit in to its R equivalent via a half-circuit method. ox On-hip Inductor o ox m o ox par ( ω, Vds) er ( ω, V ds ) + er ( ω, V ds ) ser ( V ds) ω R () ser ( V ds ) par ( ω, V ds ) er ( ω, V ds ) ser ( V ds ) ω + () Figure 6 shows the small signal equivalent of the VO, where R p and p are the equivalent series to parallel converted parasitic impedance due to the on-chip inductor ( ox, i, and si ) seen from the outputs of the VO [4]. The parasitic seen at the drain of the current source is not included in our model since this node is a virtual ground as far as the differential output is concerned, and it has no significant effect on the common mode signal. Furthermore, gd, par, R p, and R par are converted to their half-circuit equivalents. i si i si i si Tune Tune o Virtual Ground o tune tune ds gd gd M M ds gd gd Virtual Ground gd gd gs gs p p Figure 4. On-chip VO par par First, we find an equivalent impedance model of the cross coupled transistor by finding the impedance looking between its gate and drain as shown in figure 5 [4]. The equivalent impedance is a series combination of resistor er and ser R par /4 R p / R par /4 R p / Z in ( ω ) er ( ω, V ds ) + ser ( Vds ) (8) Gm er ( ω, V ds ) (9) ds ( V ds ) gs ω ser ( V ds ) (0) ds ( V ds ) + gs Where ds (V ds ) capacitance is a function of the voltage across M s drain to source. Virtual Ground paracitics R tune Figure 6. Equivalent small signal representation of VO V. POWER SUPPY INDUED JITTER (PSIJ) Zin M ds gs Figure 5. Impedance looking in to the transistor Figure 7 depicts the half-circuit representation of the VO. Where Z cs, is the impedance looking in to the drain of the current source, Z inductor is the total impedance of the inductor, and Z par is the parallel combination of the varactor, total resistance and total parasitic capacitance. To construct the half-circuit, this impedance is converted in a parallel combination of R par, and par

4 Z cs ( ω) (3) + jω Gm p 0 r p 0 r p Z inductor ( ω) (4) + O jω ( jω + ) Z par ( ω, V Tune, V ds ) (5) paracitic ( V ds ) + Tune ( V Tune ) + R l VTune V out (6) impedance voltage source used to drive the varactor. The ac voltage hit seen at the output of this driver is R cntleq V vdd _ cntrl Z pvi + R cntleq _ ac (8) Where Rcntleq (9) + Rvi Rn Z pvi (0) + pvi jω Gm r r3 Bias N _ac M p m Bias pch0 Z cs M 3 M p0 Bias M o Z inductor Rs output node of circuit R vi M n parasitic Z par Tune R Figure 8. Output stage of the voltage driver Figure 7. Half-circuit We are assuming a sinusoidal hit on the power supply at ω c frequency (_ac ). The amount of the _ac which gets through to the output, is determined by the ratio of the impedance looking in to the output, towards and terminals. This signal will disturb the output as an additive noise as follows _ ac Z par ( ω ) V osc additive _ Vdd (7) Z cs ( ωc) + Z inductor ( ωosc) + Z par ( ωosc, V Tune, V ds) As (7) indicates, the frequency at which the VO oscillates determines the impedance seen from the output of the VO to the drain of the current source and the terminal. The only impedance determined by ω c is the one of the current source. The second cause of the induced jitter is contributed from the voltage control circuitry which sets the voltage across the varactor ( V ). Figure 8 shows a simple low vdd _ cntrl The total voltage change across the varactor ( V V V ) will result in a change in the vdd additive _ vdd vdd _ cntrl effective capacitance value Tune while V additive_vdd changes the ds (V ds ) value. This causes a change in the total capacitance forcing the oscillating frequency to deviate from its nominal frequency; hence, a frequency push ( ω ( V ) + ( V ) ). osc ds ds Tune Tune We predict the peak phase variation of the output frequency by calculating the difference between the nominal oscillating frequency and the frequency to which the oscillator has been pushed to, divided by the power supply hit s frequency ωosc ω pushed ω φvdd _ push () ωc ωc Furthermore, to find out the instantaneous frequency jitter, we normalize the phase shift to the nominal frequency. φvdd _ push τ PSIJ _ vdd () ωosc The same procedure can be followed to determine the jitter induced by a hit. The effect of the same hit from the terminal is much more severe than its counter part,

5 since the impedance seen from the output of the VO is small at the oscillating frequency. Therefore, a large percentage of the bounce gets through to the output of the VO, causing the ds (V ds ) capacitance value to change dramatically; hence, a larger frequency push. To measure the amount of the frequency pushed (in turn PSIJ) via and, we are assuming a 0% of the supply voltage hit on each supply separately (_ac _ac 80mVp-p). Figure 9 and figure 0 depict our modeled results. To achieve a low jitter P, these figures can be used to analyze the over all jitter performance [4]. Hz ω ( ω ) Frequency Pushed due to Vdd ω Frequency (Rad) VII. REFERENE [] J. N. Burghartz, RF ircuit Design Aspects of Spiral Inductors on silicon IEEE Journal of Solid State ircuit, Vol. 33, No., May 998, PP: [] J. raninckx, M. Steyaert ow Noise Voltage ontrolled Oscillator Using Enhanced -Tank IEEE Transaction on circuit and Systems, Vol. 4, No., Dec 995, PP: [3] H. M. Greenhouse, Design of planar rectangular microelectronic inductors, IEEE Trans. Parts, Hybrids & Packaging, vol. PHP-0, pp. 0-09, June 974. [4] J. u, S. Rokhsaz, B. Grung, S. Anderson Discrete Z- Domain Analysis of High Order Phase ocked oops,isaas, May 00, to be published. [5]. Patrick Yue, S.S. Wong On-hip Spiral Inductors with Patterned Ground Shield for Si-Based RF I s IEEE Journal of Solid State ircuit, Vol. 33, No. 5, May 998, PP: [6] Behzad Rasavi RF Microelectronics Prentice Hall, Inc.. Figure 9. Frequency push due to 80mVpp hit on Frequency Pushed due to Vss Hz ω ( ω ) ω Frequency (Rad) Figure. 0. Frequency push due to 80mVpp hit on VI. ONUSION A closed-form solution predicting the total jitter due to ripple on the power supplies has been developed. Using this closed-form solution, we used Mathcad to model and optimize the VO under investigation. Furthermore, we compared our results with the results of the Spectre RF simulator and found both our model and Spectre RF are in agreement. This modeling technique can be used to determine PSIJ in any VO topology besides the one discussed in this paper. Acknowledgement Authors would like to thank Moises Robinson and Mike Gaboury along with all of the Rockethips members for their valuable inputs throughout the development of this paper.

Advanced Current Mirrors and Opamps

Advanced Current Mirrors and Opamps Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------

More information

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

More information

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,

More information

Introduction to CMOS RF Integrated Circuits Design

Introduction to CMOS RF Integrated Circuits Design V. Voltage Controlled Oscillators Fall 2012, Prof. JianJun Zhou V-1 Outline Phase Noise and Spurs Ring VCO LC VCO Frequency Tuning (Varactor, SCA) Phase Noise Estimation Quadrature Phase Generator Fall

More information

Characteristics of Passive IC Devices

Characteristics of Passive IC Devices 008/Oct 8 esistors Characteristics of Passive IC Devices Poly esistance Diffusion esistance Well esistance Parasitic esistance Capacitors Poly Capacitors MOS Capacitors MIM Capacitors Parasitic Capacitors

More information

ECE 255, Frequency Response

ECE 255, Frequency Response ECE 255, Frequency Response 19 April 2018 1 Introduction In this lecture, we address the frequency response of amplifiers. This was touched upon briefly in our previous lecture in Section 7.5 of the textbook.

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH) EE05 Fall 205 Microelectronic Devices and Circuits Frequency Response Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Amplifier Frequency Response: Lower and Upper Cutoff Frequency Midband

More information

High Speed Communication Circuits and Systems Lecture 4 Generalized Reflection Coefficient, Smith Chart, Integrated Passive Components

High Speed Communication Circuits and Systems Lecture 4 Generalized Reflection Coefficient, Smith Chart, Integrated Passive Components High Speed Communication Circuits and Systems Lecture 4 Generalized Reflection Coefficient, Smith Chart, Integrated Passive Components Michael H. Perrott February 11, 2004 Copyright 2004 by Michael H.

More information

Lecture 37: Frequency response. Context

Lecture 37: Frequency response. Context EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in

More information

Analysis of MOS Cross-Coupled LC-Tank Oscillators using Short-Channel Device Equations

Analysis of MOS Cross-Coupled LC-Tank Oscillators using Short-Channel Device Equations Analysis of MOS Cross-Coupled C-Tank Oscillators using Short-Channel Device Equations Makram M. Mansour Mohammad M. Mansour Amit Mehrotra Berkeley Design Automation American University of Beirut University

More information

Stability and Frequency Compensation

Stability and Frequency Compensation 類比電路設計 (3349) - 2004 Stability and Frequency ompensation hing-yuan Yang National hung-hsing University Department of Electrical Engineering Overview Reading B Razavi hapter 0 Introduction In this lecture,

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology EECS240 Spring 2013 Lecture 2: CMOS Technology and Passive Devices Lingkai Kong EECS Today s Lecture EE240 CMOS Technology Passive devices Motivation Resistors Capacitors (Inductors) Next time: MOS transistor

More information

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 (12.8.2013) B. Mazhari Dept. of EE, IIT Kanpur 44 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive

More information

Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005

Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 23 Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier December, 2005 Contents:. Introduction 2. Intrinsic frequency response

More information

EKV Modelling of MOS Varactors and LC Tank Oscillator Design

EKV Modelling of MOS Varactors and LC Tank Oscillator Design EKV Modelling of MOS Varactors and LC Tank Oscillator Design Wolfgang Mathis TET Leibniz Universität Hannover Jan-K. Bremer NXP Hamburg MOS-AK Workshop 01 6. 7. April 01, Dresden Content: Motivation: VCO

More information

The Miller Approximation

The Miller Approximation The Miller Approximation The exact analysis is not particularly helpful for gaining insight into the frequency response... consider the effect of C µ on the input only I t C µ V t g m V t R'out = r o r

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

Advantages of Using CMOS

Advantages of Using CMOS Advantages of Using CMOS Compact (shared diffusion regions) Very low static power dissipation High noise margin (nearly ideal inverter voltage transfer characteristic) Very well modeled and characterized

More information

Lecture 040 Integrated Circuit Technology - II (5/11/03) Page ECE Frequency Synthesizers P.E. Allen

Lecture 040 Integrated Circuit Technology - II (5/11/03) Page ECE Frequency Synthesizers P.E. Allen Lecture 040 Integrated Circuit Technology - II (5/11/03) Page 040-1 LECTURE 040 INTEGRATED CIRCUIT TECHNOLOGY - II (Reference [7,8]) Objective The objective of this presentation is: 1.) Illustrate and

More information

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

More information

Analytical Optimization of High Performance and High Quality Factor MEMS Spiral Inductor

Analytical Optimization of High Performance and High Quality Factor MEMS Spiral Inductor Progress In Electromagnetics Research M, Vol. 34, 171 179, 2014 Analytical Optimization of High Performance and High Quality Factor MEMS Spiral Inductor Parsa Pirouznia * and Bahram Azizollah Ganji Abstract

More information

Refinements to Incremental Transistor Model

Refinements to Incremental Transistor Model Refinements to Incremental Transistor Model This section presents modifications to the incremental models that account for non-ideal transistor behavior Incremental output port resistance Incremental changes

More information

ECE315 / ECE515 Lecture 11 Date:

ECE315 / ECE515 Lecture 11 Date: ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012 /3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators

Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators IEICE TRANS. EECTRON., VO.E93 C, NO.6 JUNE 200 777 PAPER Special Section on Analog Circuits and Related SoC Integration Technologies Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Design of Analog Integrated Circuits

Design of Analog Integrated Circuits Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

Electrical and Thermal Packaging Challenges for GaN Devices. Paul L. Brohlin Texas Instruments Inc. October 3, 2016

Electrical and Thermal Packaging Challenges for GaN Devices. Paul L. Brohlin Texas Instruments Inc. October 3, 2016 Electrical and Thermal Packaging Challenges for GaN Devices Paul L. Brohlin Texas Instruments Inc. October 3, 2016 1 Outline Why GaN? Hard-Switching Losses Parasitic Inductance Effects on Switching Thermal

More information

Lecture 14 Date:

Lecture 14 Date: Lecture 14 Date: 18.09.2014 L Type Matching Network Examples Nodal Quality Factor T- and Pi- Matching Networks Microstrip Matching Networks Series- and Shunt-stub Matching L Type Matching Network (contd.)

More information

KH600. 1GHz, Differential Input/Output Amplifier. Features. Description. Applications. Typical Application

KH600. 1GHz, Differential Input/Output Amplifier. Features. Description. Applications. Typical Application KH 1GHz, Differential Input/Output Amplifier www.cadeka.com Features DC - 1GHz bandwidth Fixed 1dB (V/V) gain 1Ω (differential) inputs and outputs -7/-dBc nd/3rd HD at MHz ma output current 9V pp into

More information

Miniature Electronically Trimmable Capacitor V DD. Maxim Integrated Products 1

Miniature Electronically Trimmable Capacitor V DD. Maxim Integrated Products 1 19-1948; Rev 1; 3/01 Miniature Electronically Trimmable Capacitor General Description The is a fine-line (geometry) electronically trimmable capacitor (FLECAP) programmable through a simple digital interface.

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

EE C245 ME C218 Introduction to MEMS Design

EE C245 ME C218 Introduction to MEMS Design EE C45 ME C18 Introduction to MEMS Design Fall 008 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 9470 Lecture 6: Output

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process EECS240 Spring 202 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS Technology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 Today s Lecture

More information

LAYOUT TECHNIQUES. Dr. Ivan Grech

LAYOUT TECHNIQUES. Dr. Ivan Grech LAYOUT TECHNIQUES OUTLINE Transistor Layout Resistor Layout Capacitor Layout Floor planning Mixed A/D Layout Automatic Analog Layout Layout Techniques Main Layers in a typical Double-Poly, Double-Metal

More information

VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large

More information

EE382M-14 CMOS Analog Integrated Circuit Design

EE382M-14 CMOS Analog Integrated Circuit Design EE382M-14 CMOS Analog Integrated Circuit Design Lecture 3, MOS Capacitances, Passive Components, and Layout of Analog Integrated Circuits MOS Capacitances Type of MOS transistor capacitors Depletion capacitance

More information

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C

More information

CE/CS Amplifier Response at High Frequencies

CE/CS Amplifier Response at High Frequencies .. CE/CS Amplifier Response at High Frequencies INEL 4202 - Manuel Toledo August 20, 2012 INEL 4202 - Manuel Toledo CE/CS High Frequency Analysis 1/ 24 Outline.1 High Frequency Models.2 Simplified Method.3

More information

ELEN 610 Data Converters

ELEN 610 Data Converters Spring 04 S. Hoyos - EEN-60 ELEN 60 Data onverters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 04 S. Hoyos - EEN-60 Electronic Noise Signal to Noise ratio SNR Signal Power

More information

ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture 11 MOS Amplifiers ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive

More information

Exact Analysis of a Common-Source MOSFET Amplifier

Exact Analysis of a Common-Source MOSFET Amplifier Exact Analysis of a Common-Source MOSFET Amplifier Consider the common-source MOSFET amplifier driven from signal source v s with Thévenin equivalent resistance R S and a load consisting of a parallel

More information

Voltage-Controlled Oscillator (VCO)

Voltage-Controlled Oscillator (VCO) Voltage-Controlled Oscillator (VCO) Desirable characteristics: Monotonic f osc vs. V C characteristic with adequate frequency range f max f osc Well-defined K vco f min slope = K vco VC V C in V K F(s)

More information

Volterra Series: Introduction & Application

Volterra Series: Introduction & Application ECEN 665 (ESS : RF Communication Circuits and Systems Volterra Series: Introduction & Application Prepared by: Heng Zhang Part of the material here provided is based on Dr. Chunyu Xin s dissertation Outline

More information

Class E Design Formulas V DD

Class E Design Formulas V DD Class E Design Formulas V DD RFC C L+X/ω V s (θ) I s (θ) Cd R useful functions and identities Units Constants Table of Contents I. Introduction II. Process Parameters III. Inputs IV. Standard Class E Design

More information

Introduction and Background

Introduction and Background Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments

More information

EECS 105: FALL 06 FINAL

EECS 105: FALL 06 FINAL University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last

More information

Preamplifier in 0.5µm CMOS

Preamplifier in 0.5µm CMOS A 2.125 Gbaud 1.6kΩ Transimpedance Preamplifier in 0.5µm CMOS Sunderarajan S. Mohan Thomas H. Lee Center for Integrated Systems Stanford University OUTLINE Motivation Shunt-peaked Amplifier Inductor Modeling

More information

Voltage AmpliÞer Frequency Response

Voltage AmpliÞer Frequency Response Voltage AmpliÞer Frequency Response Chapter 9 multistage voltage ampliþer 5 V M 7B M 7 M 5 R 35 kω M 6B M 6 Q 4 100 µa X M 3 Q B Q v OUT V s M 1 M 8 M9 V BIAS M 10 Approaches: 1. brute force OCTC -- do

More information

Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered. capacitance inductance transmission lines Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of

More information

AN019. A Better Approach of Dealing with Ripple Noise of LDO. Introduction. The influence of inductor effect over LDO

AN019. A Better Approach of Dealing with Ripple Noise of LDO. Introduction. The influence of inductor effect over LDO Better pproach of Dealing with ipple Noise of Introduction It has been a trend that cellular phones, audio systems, cordless phones and portable appliances have a requirement for low noise power supplies.

More information

Lecture 100 Voltage-Controlled Oscillators (09/01/03) Page 100-1

Lecture 100 Voltage-Controlled Oscillators (09/01/03) Page 100-1 ecture 00 Voltageontrolled Oscillators (09/0/03) Page 00 ETURE 00 VOTAGEONTROED OSIATORS INTRODUTION Objective The objective of this presentation is examine and characterize the types of voltagecontrolled

More information

Multistage Amplifier Frequency Response

Multistage Amplifier Frequency Response Multistage Amplifier Frequency Response * Summary of frequency response of single-stages: CE/CS: suffers from Miller effect CC/CD: wideband -- see Section 0.5 CB/CG: wideband -- see Section 0.6 (wideband

More information

Schedule. ECEN 301 Discussion #20 Exam 2 Review 1. Lab Due date. Title Chapters HW Due date. Date Day Class No. 10 Nov Mon 20 Exam Review.

Schedule. ECEN 301 Discussion #20 Exam 2 Review 1. Lab Due date. Title Chapters HW Due date. Date Day Class No. 10 Nov Mon 20 Exam Review. Schedule Date Day lass No. 0 Nov Mon 0 Exam Review Nov Tue Title hapters HW Due date Nov Wed Boolean Algebra 3. 3.3 ab Due date AB 7 Exam EXAM 3 Nov Thu 4 Nov Fri Recitation 5 Nov Sat 6 Nov Sun 7 Nov Mon

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers

6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers 6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers Michael Perrott Massachusetts Institute of Technology March 8, 2005 Copyright 2005 by Michael H. Perrott Notation for Mean,

More information

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

More information

Switching characteristics of lateral-type and vertical-type SiC JFETs depending on their internal parasitic capacitances

Switching characteristics of lateral-type and vertical-type SiC JFETs depending on their internal parasitic capacitances Switching characteristics of lateral-type and vertical-type SiC JFETs depending on their internal parasitic capacitances Nathabhat Phankong 1a), Tsuyoshi Funaki 2, and Takashi Hikihara 1 1 Kyoto University,

More information

Lecture 020 Review of CMOS Technology (09/01/03) Page 020-1

Lecture 020 Review of CMOS Technology (09/01/03) Page 020-1 Lecture 020 Review of CMOS Technology (09/01/03) Page 020-1 LECTURE 020 REVIEW OF CMOS TECHNOLOGY INTRODUCTION Objective Provide sufficient background to understand the limits and capabilities of CMOS

More information

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier

More information

Chapter 33. Alternating Current Circuits

Chapter 33. Alternating Current Circuits Chapter 33 Alternating Current Circuits 1 Capacitor Resistor + Q = C V = I R R I + + Inductance d I Vab = L dt AC power source The AC power source provides an alternative voltage, Notation - Lower case

More information

EE C245 ME C218 Introduction to MEMS Design

EE C245 ME C218 Introduction to MEMS Design EE C45 ME C8 Introduction to MEMS Design Fall 007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 9470 Lecture 5: Output t

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators

CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater

More information

Lecture 14: Electrical Noise

Lecture 14: Electrical Noise EECS 142 Lecture 14: Electrical Noise Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2008 by Ali M. Niknejad A.M.Niknejad University of California, Berkeley EECS 142 Lecture 14 p.1/20

More information

Amplifiers, Source followers & Cascodes

Amplifiers, Source followers & Cascodes Amplifiers, Source followers & Cascodes Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 02 Operational amplifier Differential pair v- : B v + Current mirror

More information

Homework Assignment 11

Homework Assignment 11 Homework Assignment Question State and then explain in 2 3 sentences, the advantage of switched capacitor filters compared to continuous-time active filters. (3 points) Continuous time filters use resistors

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

ECE 202 Fall 2013 Final Exam

ECE 202 Fall 2013 Final Exam ECE 202 Fall 2013 Final Exam December 12, 2013 Circle your division: Division 0101: Furgason (8:30 am) Division 0201: Bermel (9:30 am) Name (Last, First) Purdue ID # There are 18 multiple choice problems

More information

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

More information

A Novel Tunable Dual-Band Bandstop Filter (DBBSF) Using BST Capacitors and Tuning Diode

A Novel Tunable Dual-Band Bandstop Filter (DBBSF) Using BST Capacitors and Tuning Diode Progress In Electromagnetics Research C, Vol. 67, 59 69, 2016 A Novel Tunable Dual-Band Bandstop Filter (DBBSF) Using BST Capacitors and Tuning Diode Hassan Aldeeb and Thottam S. Kalkur * Abstract A novel

More information

Power Management Circuits and Systems. Basic Concepts: Amplifiers and Feedback. Jose Silva-Martinez

Power Management Circuits and Systems. Basic Concepts: Amplifiers and Feedback. Jose Silva-Martinez Power Management Circuits and Systems Basic Concepts: Amplifiers and Feedback Jose Silva-Martinez Department of Electrical & Computer Engineering Texas A&M University January 2, 209 Non-Inverting Amplifier

More information

Microelectronics Main CMOS design rules & basic circuits

Microelectronics Main CMOS design rules & basic circuits GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September

More information

Chapter 9 Frequency Response. PART C: High Frequency Response

Chapter 9 Frequency Response. PART C: High Frequency Response Chapter 9 Frequency Response PART C: High Frequency Response Discrete Common Source (CS) Amplifier Goal: find high cut-off frequency, f H 2 f H is dependent on internal capacitances V o Load Resistance

More information

Circuit Topologies & Analysis Techniques in HF ICs

Circuit Topologies & Analysis Techniques in HF ICs Circuit Topologies & Analysis Techniques in HF ICs 1 Outline Analog vs. Microwave Circuit Design Impedance matching Tuned circuit topologies Techniques to maximize bandwidth Challenges in differential

More information

Analysis and Design of Differential LNAs with On-Chip Transformers in 65-nm CMOS Technology

Analysis and Design of Differential LNAs with On-Chip Transformers in 65-nm CMOS Technology Analysis and Design of Differential LNAs with On-Chip Transformers in 65-nm CMOS Technology Takao Kihara, Shigesato Matsuda, Tsutomu Yoshimura Osaka Institute of Technology, Japan June 27, 2016 2 / 16

More information

Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics

Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance

More information

Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling

Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling Li Ding and Pinaki Mazumder Department of Electrical Engineering and Computer Science The University of Michigan,

More information

Lecture 04: Single Transistor Ampliers

Lecture 04: Single Transistor Ampliers Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37 Single-Transistor

More information

ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

More information

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OP-AMP It consists of two stages: First

More information

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS 98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC

More information

University of Toronto. Final Exam

University of Toronto. Final Exam University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

More information

R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6

R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6 R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition Figures for Chapter 6 Free electron Conduction band Hole W g W C Forbidden Band or Bandgap W V Electron energy Hole Valence

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

Core Technology Group Application Note 3 AN-3

Core Technology Group Application Note 3 AN-3 Measuring Capacitor Impedance and ESR. John F. Iannuzzi Introduction In power system design, capacitors are used extensively for improving noise rejection, lowering power system impedance and power supply

More information

EKV MOS Transistor Modelling & RF Application

EKV MOS Transistor Modelling & RF Application HP-RF MOS Modelling Workshop, Munich, February 15-16, 1999 EKV MOS Transistor Modelling & RF Application Matthias Bucher, Wladek Grabinski Electronics Laboratory (LEG) Swiss Federal Institute of Technology,

More information

Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers

Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers 6.012 Electronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 Wednesday night,

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

Lecture 23 - Frequency Resp onse of Amplifiers (I) Common-Source Amplifier. May 6, 2003

Lecture 23 - Frequency Resp onse of Amplifiers (I) Common-Source Amplifier. May 6, 2003 6.0 Microelectronic Devices and Circuits Spring 003 Lecture 3 Lecture 3 Frequency Resp onse of Amplifiers (I) CommonSource Amplifier May 6, 003 Contents:. Intro duction. Intrinsic frequency resp onse of

More information

Frequency Response Prof. Ali M. Niknejad Prof. Rikky Muller

Frequency Response Prof. Ali M. Niknejad Prof. Rikky Muller EECS 105 Spring 2017, Module 4 Frequency Response Prof. Ali M. Niknejad Department of EECS Announcements l HW9 due on Friday 2 Review: CD with Current Mirror 3 Review: CD with Current Mirror 4 Review:

More information

55:041 Electronic Circuits The University of Iowa Fall Final Exam

55:041 Electronic Circuits The University of Iowa Fall Final Exam Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a class-b amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered

More information