1 3/4 2. Features / Advantages: Applications: Package: SimBus A
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1 hyristor Module RRM 2x 6.3 Phase leg Part number Backside: isolated 3/ Features / dvantages: pplications: Package: SimBus hyristor for line frequency Planar passivated chip Long-term stability Copper base plate with Direct Copper Bonded l2o3-ceramic Spring contacts for solder-free dirver connection Line rectifying /6 Hz Softstart C motor control DC Motor control Power converter C power control Lighting and temperature control solation oltage: 48 ~ ndustry standard outline RoHS compliant Gate: Spring contacts for solder-free PCB-mounting Height: 7 mm Base plate: Copper internally DCB isolated dvanced power cycling XYS reserves the right to change limits, conditions and dimensions. 24 XYS all rights reserved Data according to EC 6747and per semiconductor unless otherwise specified
2 hyristor Symbol Definition 6 2 C J 2 C Ratings min. typ. max. 7 forward voltage drop 2 C.6 (RMS) Conditions 4 4 C 9 C 8 sine 2 C J 2 C J threshold voltage J 4 C.8 for power loss calculation only r slope resistance.6 mω R thermal resistance junction to case. K/ thjc P tot total power dissipation C 2 C 76 SM max. forward surge current J 4 C 6. k R 6.48 k J 4 C. k R. k ²t value for fusing J 4 C 8. k²s R 74.7 k²s J 4 C 3. k²s 26.3 k²s P GM RSM/DSM RRM/DRM P G average forward current RMS forward current J J 2 C C J junction capacitance 4 f MHz 2 C 273 max. gate power dissipation t P 3 µs C 4 C 2 t µs 6 average gate power dissipation P J J 4 C R Unit R J pf (di/dt) cr critical rate of rise of current J 4 C; f Hz repetitive, 6 t P µs; di G /dt./µs; G.; D ⅔ DRM non-repet., (dv/dt) critical rate of rise of voltage ⅔ 4 C cr max. non-repetitive reverse/forward blocking voltage max. repetitive reverse/forward blocking voltage reverse current, drain current 6 R R thch thermal resistance case to heatsink.8 K/ D GK ; method (linear voltage rise) G gate trigger voltage D 6 J 2 C J -4 C DRM J µ m /µs /µs /µs G gate trigger current D 6 J 2 C m J -4 C m GD gate non-trigger voltage D ⅔ DRM J 4 C.2 GD gate non-trigger current m L latching current t p 3µs J 2 C m G.; di G /dt./µs H holding current D 6 R GK J 2 C m t gd gate controlled delay time D ½ DRM J 2 C 2 µs G.; di G /dt./µs t q turn-off time R ; ; D ⅔ DRM J 4 C µs di/dt /µs; dv/dt 2/µs; t p µs XYS reserves the right to change limits, conditions and dimensions. 24 XYS all rights reserved Data according to EC 6747and per semiconductor unless otherwise specified
3 Package SimBus Ratings Symbol Definition Conditions min. typ. max. Unit RMS RMS current per terminal J virtual junction temperature -4 4 C op operation temperature -4 2 C stg storage temperature -4 2 C eight M D M d Spp/pp d Spb/pb SOL mounting torque 3 terminal torque 2. creepage distance on surface striking distance through air isolation voltage t second t minute terminal to terminal terminal to backside /6 Hz, RMS; SOL m g Nm Nm mm mm yyww add XXXXXXXXX Part Name Date Code Data Matrix Part number M C M P 6 S Module hyristor (SCR) hyristor (up to 8) Current Rating [] Phase leg Reverse oltage [] SimBus Ordering Standard Part Number Marking on Product Delivery Mode Quantity Code No. Blister Similar Part Package oltage class MCMPD6S Simbus 6 Equivalent Circuits for Simulation * on die level J 4 C hyristor R max threshold voltage.8 R max slope resistance *.8 mω XYS reserves the right to change limits, conditions and dimensions. 24 XYS all rights reserved Data according to EC 6747and per semiconductor unless otherwise specified
4 Outlines SimBus 3/ XYS reserves the right to change limits, conditions and dimensions. 24 XYS all rights reserved Data according to EC 6747and per semiconductor unless otherwise specified
5 hyristor 4 6 Hz, 8% RRM 6 R [] J 2 C 4 C.... [] J 2 C Fig. Forward current vs. voltage drop per thyristor SM 4 [] J 4 C J 4 C.. t [s] Fig. 2 Surge overload current vs. time per thyristor 2 t [ 2 s] 4 J 4 C J 4 C t [ms] Fig. 3 2 t vs. time per thyristor G [] : G, J 2 C 2: G, J 2 C 3: G, J -4 C t gd [μs]. J 2 C lim. typ. 3 2 M [] dc : P GM 8 GD, J 4 C : P GM 6. 6: P GM G [] Fig. 4 Gate voltage & gate current..... G [] Fig. Gate controlled delay time t gd case [ C] Fig. 6 Max. forward current vs. case temperature per thyr. 3 2 P tot [] dc R thh Z thjc.8 [K/] i R thi (K/) t i (s) () [] amb [ C] Fig. 7 Power dissipation vs. forward current and ambient temperature per thyristor. t [ms] Fig. 8 ransient thermal impedance junction to case vs. time per thyristor XYS reserves the right to change limits, conditions and dimensions. 24 XYS all rights reserved Data according to EC 6747and per semiconductor unless otherwise specified
3 1/4. Features / Advantages: Applications: Package: SOT-227B (minibloc)
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