ELE 312 Digital Electronics

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1 ELE 312 Digital Electronics Textbooks DeMassa and Ciccone, Digital Integrated Circuits, John Wiley & Sons. Taub and Schilling, Digital Integrated Electronics, McGraw-Hill 1

2 Contents Basic Properties of Digital Integrated Circuits Diode Digital Circuits BJT Digital Circuits Ebers & Moll equations Transistor modelling State of transistor in a circuit Resistor-Transistor Logic (RTL) Diode-Transistor Logic (DTL) Transistor-Transistor Logic (TTL) Schottky Transistor Transistor Logic (STTL) Different TTL Gates Emitter-Coupled Logic (ECL) MOS Digital Circuits NMOS Gates CMOS Gates Properties of Digital Integrated Circuits 2

3 Most important elements: Inverter and Noninverter Idealized Inverter and Voltage Transfer Characteristics( VTCs) 3

4 Propagation Delays Rise and fall times and turn-on and turn-off times 4

5 Power dissipation Logic Element Equivalent Circuit and Fan-out 5

6 Power - Delay Product: Speed-power product = (Average Power Diss) x (Propagation Delay) PD = P DISS(avg) x t P(avg) Diode Digital Circuits 6

7 Diodes Shockleys Eq I D = I S (e V D /V T 1) for Forward Bias V D V 0 = 0.7 V 7

8 IV Characteristics for PN Junction diodes for MN Schottky diodes SPICE model I = I D S (e V D /V T 1) 8

9 Basic Logic Gates: AND Basic Logic Gates: OR 9

10 Clamping Diodes Level shifting diodes Level Shifting Diode AND Gate Level Shifting Diode OR Gate 10

11 BJT Transistors BJT Fabrication Example 1

12 Multi-Emitter Fabrication Examples NPN BJT 2

13 Ebers-Moll NPN BJT Model I I I E C B = I D,BE = α I = I E F α I D,BE I C R I D,BC D,BC I I D,BE D,BC = I = I ES CS (e (e VBE / VT VBC / VT 1) 1) I S Reciprocity theorem = α I = α I F ES R CS transport saturation current BJT Modes of Operation BE junction Reverse Forward Forward Reverse BC junction Reverse Reverse Forward Forward Mode Cutoff (OFF) Forward active (FA) Saturation (SAT) Reverse active (RA) 3

14 Reduced models of the operation modes αf βf = 1 α F (a) Cutoff (b) Forward active I = σβ I C σ 1 F B α R βr = 1 α R (c) Saturation (d) Reverse active IV Characteristics 4

15 Modes of Operation Examples β F = 65 I C, I B =? Base and emitter voltages =? 5

16 TTL Circuit Design Output-High Pull-up Driver Output-Low Pull-down Driver Discharge path and Base-Driving circuitry 6

17 Power Dissipation Example Resistor-Transistor Logic (RTL) 7

18 INVERTER Voltage Transfer Characteritics (VTC) V IL = V BE(FA) V IH = V BE(SAT) V + CC V β R F CE(SAT) C R B NAND NOR 8

19 RTL Fan-out RTL fan-out analysis 9

20 RTL fan-out analysis Maximum fan-out? I N = I OUT IN I OUT V = CC V R C OUT I IN V = OUT V R B BE(SAT) V OUT = V IH V IH = V BE(SAT) V + CC V β R F CE(SAT) C R B 10

21 RTL NONINVERTER 11

22 AND OR 12

23 RTL with Active Pull-up Fan-out of RTL with Active Pull-up Determined by the output high state as Q S is cut-off for low-inputs Simplified output high state Simplified input high state 1

24 2 Simplified output-high fan-out configuration = IH OH I I N CP OUT CE(SAT) CC EP OUT R V V V I I = 2 / R V V I B BE(SAT) OUT IN = IH (min) OUT V V = B C F CE(SAT) CC BE(SAT) IH R R V V V V β + =

25 Diode-Transistor Logic (DTL) Basic DTL Inverter Basic DTL NAND Gate 3

26 Diode Modified DTL Inverter Transistor Modified DTL Inverter 4

27 VTC of Transistor Modified DTL Inverter V OH = V CC V IL = V BE,O(FA) + V BE,L(FA) V OL = V CE,O(SAT) V IH = V BE,O(SAT) + V BE,L(FA) DTL Fan-out Determined by the output low state as D I is off for high-inputs 5

28 Cascaded DTL I N = I OL IL I I I OL RC = I C,O(SAT) I C RC VCC VCE,O(SAT) = Path 2 R = σβ I C,O(SAT) F B,O(SAT) For maximum fan-out σ =1 IB,O = I V I = E,L I RD BE,O(SAT) RD R D VCC VBE,L(FA) VD,L(ON) VBE,O(SAT) IE,L σr B V V V CC D,I(ON) CE,O(SAT) IL = Path 3 R B I Example: Calculate the DTL fan-out for β F = 49 and σ = Power Dissipation Example: Calculate the average power dissipation for the above example? 6

29 Tansistor-Transistor Logic (TTL) Basic TTL Inverter Basic DTL Inverter (compare) Basic TTL NAND Gate 7

30 Actual TTL NAND Gate with Totem Pole Output VTC of an actual TTL Inverter V OH = V CC V BE,P(FA) V D,L(ON) V OL = V CE,O(SAT) V OB = V CC I RC R C V BE,P(FA) V D,L(ON) V I RC = IRD = R BE,O(FA) D V IL = V BE,S(FA) V CE,I(SAT)) V IH = V BE,O(SAT) + V BE,S(SAT) V CE,I(SAT) V IB = V BE,O(FA) + V BE,S(FA) V CE,I(SAT) 8

31 States of diodes and BJTs EOC: Edge of conduction TTL Fan-out Determined by the output low state as Q I is cut-off for high-inputs 9

32 Cascaded TTL Path 1 I IL V = CC V BE,I(SAT) R B V CE,O(SAT) I = I + I E,S(SAT) B,S C,S I N = I OL IL I OL = I C,O(SAT) IB,O(SAT) = I V I RD = R BE,O(SAT) D = σβ I E,S(SAT) For maximum fan-out F B,O(SAT) I RD σ =1 Path 2 I I I C,S B,S B,I V = = I V = CC CC V C,I(RA) V CE,S(SAT) R BC,I(RA) C V = (1 + β ) I R V R B BE,O(SAT) B,I BE,S(SAT) V BE,O(SAT) Example (TTL Fan-out) Example: Calculate the TTL fan-out for β F = 25, σ = 0.85 and β R = 0.1 I RB(OL) = 675 μa I RC(OL) = 2.5 ma I IL = I RB(OH) = 1 ma I OL = 51.9 ma I N = I OL = IL 51 Example (Power Dissipation) Example: Calculate the average power dissipation for the above example? P CC(avg) = 10.4 mw 10

33 Open-Collector TTL Mostly used in data busses where multiple gate outputs must be ANDed. This can be accomplished by using a single pull-up resistor with open-collector TTL gates This type of connection is referred to as wired-and. Low Power TTL (LTTL) Accomplished simply by increasing the resistance values. However this results in Decreased fan-out Longer transient-response times 1

34 LTTL Example Compare the power dissipation of the LTTL and TTL gates. I RB(OL) = 67.5 μa I RC(OL) = 200 μa I RB(OH) = 100 μa P CC(avg) = 919 μw TTL vs LTTL power dissipation ratio = 10.4 / = 11.3 High Speed TTL (HTTL) Accomplished simply by decreasing the resistance values. However this results in Increased power dissipation 2

35 Schottky Tansistor-Transistor Logic (STTL) Schottky Barrier MN diode Schottky-clamped BJT (Schottky Transistor) 3

36 Multi-Emitter Fabrication Examples Modes of Operation for SBJT 1. OFF 2. FA 3. On Hard 4. Reverse Schottky 4

37 Example (SBJT) Example: Draw the VTC graph of the SBJT inverter shown below STTL NAND Gate 5

38 STTL NAND Gate (VTC) V OH = V CC V BE,P(FA) V BE,P2(FA) V OL = V CE,O(HARD) V IL = V BE,O(FA) + V BE,S(FA) V CE,I(HARD) V IH = V BE,O(HARD) + V BE,S(HARD) V CE,I(HARD) STTL NAND Gate (Device states) Device state table 6

39 STTL Fan-out Determined by the output low state as Q I is cut-off for high-inputs Cascaded STTL I IL V = CC V Path 1 BE,I(HARD) R B V CE,O(HARD) I N = I OL IL I I I OL = I B,O(HARD) C,D(HARD) C,O(HARD) = I V = = β I E,S(HARD) BE,O(HARD) F B,O(HARD) R I V CD C,D(HARD) CE,D(HARD) Path 2, 3 I I SBD C,S V = V = CC CC V V I = I + I CE,S(HARD) I = I = I B,S C,I(RS) BC,I(RS) E,S(HARD) R SBD C V V BE,S(HARD) R B B,S BE,O(HARD) V C,S BE,O(HARD) 7

40 Example (TTL Fan-out) Example: Calculate the STTL maximum fan-out for β F = 49. I RB(OL) = 1.11 ma I RC(OL) = 4.11 ma I RCD(OL) = 1.20 ma I E,S(OL) = 4.22 ma I R,O(OL) = 4.02 ma I OL = 197 ma I IL = I RB(OH) = 1.32 ma I N = I OL = IL 149 Example (Power Dissipation) Example: Calculate the average power dissipation for the above example? I E,P(OL) = ma I E,P(OH) = 1.3 ma P CC(avg) = mw Low Power STTL (LSTTL) Accomplished by 1. Increasing the resistance value 2. Diode input section 3. Pull-down enhancements 8

41 Low Power STTL (LSTTL) LSTTL Example Compare the power dissipation of the LSTTL and STTL gates. I RB(OL) = 170 μa I RC(OL) = 463 μa I RB(OH) = 210 μa P CC(avg) = 2.11 mw STTL vs LSTTL power dissipation ratio = / 2.11 = 9.5 9

42 Advanced Schottky Tansistor- Transistor Logic (ASTTL) Advanced Schottky Transistor Logic Advanced Low-Power Schottky TTL (ALSTTL) Fairchild Advanced Schottky TTL (FAST) Advanced Schottky TTL (ASTTL) 10

43 ALSTTL ALSTTL VTC V OH = V CC V BE,P(FA) V OL = V CE,O(HARD) V IL = V BE,O(FA) + V EB,IPA(FA) V IH = V BE,O(HARD) + V BE,S(HARD) + V BE,SB(HARD) V BE,IPA(FA) 11

44 ALSTTL VTC FAST 12

45 FAST VTC V OH = V CC V BE,P(FA) V OL = V CE,O(HARD) V IL = V BE,O(FA) + V BE,S(FA) + V BE,SB(FA) V D,IA(ON) V IH = V BE,O(HARD) + V BE,S(HARD) + V BE,SB(HARD) V D,IA(ON) ASTTL 13

46 ASTTL 14

47 Other TTL Gates Other TTL Gates AND gates NOR gates OR gates AND-OR-INVERT (AOI) gates XOR gates Schmitt Trigger Inverters and NAND gates Tri-State buffers 1

48 TTL AND gate TTL AND gate - VTC 2

49 TTL NOR gate TTL NAND gate Power Dissipation Example I RB(IL) = 1 ma I RB(IH) = 675 μa I RC(OL) = 2.5 ma I CC(LL) = 2 ma I CC(HL) = ma I CC(LH) = ma I CC(HH) = 3.85 ma P CC(avg) = mw TTL OR gate Example: Noise margins V NMH, V NML? TTL AND gate 3

50 Complex Logic TTL Gate Design 1. ANDing of signals Multi-emitter input BJT sections 2. ORing of signals Multiple input sections (Q I and R B ) Multiple drive splitting BJTs (Q S ) 3. If non-inverting ORing is desired Addional logic inversion circuitry 4. Totem-pole output branch AND-OR-INVERT (AOI) gate 4

51 Example Design a complex logic TTL gate that V OUT = V A V B + V C + V D V E V F Example Design a complex logic TTL gate that V OUT = V A V B + V C + V D V E V F 5

52 TTL XOR gate Hysteresis and Schmitt Trigger Gates 6

53 Hysteresis Hysteresis Base-Emitter coupled Schmitt Trigger Non-inverting circuit V OHS = V CC VCC VBE(SAT) VCC VCE(SAT) V OLS = R eq + V R CS1 R CS2 R = R eq CS1 R CS2 R E CE(SAT) VCC VBE(SAT) VCC VCE(SAT) V IUS = R eq + V R CS1 R CS2 V IDS V = CC + α V BE,S1(SAT) α V BE,S2(FA) R α = R BE,S1(FA) CS 1 + E 1 7

54 Example Find the V OHS, V OLS, V IUS and V IDS points where R CS1 = 4kΩ, R CS2 = 2.5kΩ, and R ES = 1kΩ. V OHS = 5V R eq = 606Ω V OLS = 2V V IUS = 2.5V I CS1 = 1.05mA V IDS = 1.66V I CS1 = 1.92mA TTL Schmitt Trigger NAND gate 8

55 Example Find the V OH, V OL, V IU and V ID points where R CS1 = 4kΩ, R CS2 = 2.5kΩ, and R ES = 1kΩ. V OH = 3.6V V OL = 0.2V V IUS = 2.5V V IDS = 1.66V V IU = 1.8V V ID = 0.96V TTL Tri-state Buffers 9

56 TTL Tri-state Buffers Connecting TTL Tri-state buffers to a Bus 10

57 11

58 Emitter-Coupled Logic (ECL) Basic ECL Inverter/Non-inverter (ECL Current Switch) 1

59 Basic ECL Inverter/Non-inverter VTC According to inverting output: V INV V OH = V CC VIH VBE ( ECL ) + V VOL = VCC R E EE R CI V V IL = V BB 0.05 V IH = V BB S V = CC + V BC (SAT ) R CI + (V R E R CI 1 + R E BE (SAT ) V EE ) Example Calculate the critical VTC points for the ECL current switch V CC = 5V, V EE = 0V, V BB = 2.6V, R CI = R CR = R E = 1kΩ, V BE(ECL) = 0.75V, V BE(SAT) = 0.8V, V BC(SAT) = 0.6V V OH = 5V V OL = 3.10V V IL = 2.55V V IH = 2.65V V S = 3.2V V INV (V IN = V S ) = 2.6V 2

60 Basic ECL NOR/OR Gate 3

61 MECL I NOR/OR Gate V OH V = R CI EE V F BE ( ECL ) + (β + 1)R DN R CI V BE ( ECL ) V OL V = IH V BE ( ECL ) R E + V EE R CI V BE ( ECL ) Example Find the logical swing, noise margins and noise immunities for the MECL I circuit above. β F = 49, V BE(ECL) = 0.75V, V BE(FA) = 0.75V, V BE(SAT) = 0.8V, V BC(SAT) = 0.6V V OH = 0.76V V OL = 1.55V V LS = 0.79V V IL = 1.225V V IH = 1.125V V NMH = 0.365V V NML = 0.325V V S = 0.29V V NIH = 0.53V V NIL = 0.475V 4

62 MECL I Fanout I N = I OH IH I OH = I E,BN(FA) I RDN VOH + VEE IRDN = R DN I E,BN(FA) = (βf + 1) I VOH V IB,BN = R CI B,BN BE,BN(ECL) I I IH RE E IRE = β + 1 F VE + V = R V = V OH E EE V BE(ECL) Fan-out Example Find the maximum fan-out for the MECL I circuit above β F = 49, V BE(ECL) = 0.75V, V BE(FA) = 0.75V, V BE(SAT) = 0.8V, V BC(SAT) = 0.6V Assume load gates reduce V OH by 0.03 volts. V OH = 0.79V I RDN = ma V E = V I B,BN = 148 μa I RE = 2.95 ma I OH N = = 87 I E,BN = 7.4 ma IIH I IH = 59 μa I OH = 5.2 ma 5

63 Power Dissipation Example Find the average power dissipated in the MECL I circuit above I RE(NOH) = 2.64 ma I RDN(NOH) = 2.22 ma I RDO(NOH) = ma I EE(NOH) = ma I RE(NOL) = 2.98 ma I RDN(NOL) = ma I RDO(NOL) = 2.22 ma I EE(NOL) = ma P EE(avg) = 35.6 mw Other ECL Gates 6

64 DeMorgan s Theorems NOR and OR using ANDs and NANDs NOR: A + B = A B OR: A + B = A B NAND and AND using ORs and NORs NAND: AND: A B = A + B A B = A + B Example Implement the following logic using only ECL gates ( A + B)(C + D) Solution: ( A + B)(C + D) (A + B) + (C + D) 7

65 Collector Dotting Wired-AND Gates Complex Logic Gates with Collector Dotting 8

66 Example Series Gating Basic ECL NAND/AND Current Switch 9

67 Series Gating NAND/AND Gate Complex Logic Gates with Series Gating 10

68 Example ECL XOR/XNOR Gates 11

69 ECL Decoding Tree 12

70 MOS Logic MOS Logic NMOS gates Fabrication Modes of operation NMOS Inverters and Analysis General NMOS Inverter Resistor Loaded NMOS Inverter E-MOSFET loaded NMOS Inverter D-MOSFET loaded NMOS Inverter 1

71 NMOS (n-channel E-MOSFET) Fabrication Examples CMOS Fabrication Example 2

72 IV Characteristics NMOS modes of operation (a) Cutoff mode (b) Linear mode (c) Saturation mode (d) body-bias effect on threshold voltage 3

73 General NMOS Inverter Graphical analysis when load is a resistor 4

74 Load capacitance Power dissipation (a) Static power dissipation P DD = V DD (I DD(OH) + I DD(OL) ) / 2 V DD I DD(OL) / 2 (b) Transient power dissipation P TOTAL = P DD + P D P D = C L ƒ V 2 DD ƒ: frequency at which the gate is switched 5

75 Resistor Loaded NMOS Resistor Loaded NMOS Inverter 6

76 Propagation Delay Fall time 7

77 E-MOSFET Loaded NMOS E-MOSFET Loaded NMOS Inverter 8

78 D-MOSFET Loaded NMOS D-MOSFET Loaded NMOS Inverter 9

79 NMOS Gates Symbol Shorthands 10

80 NOR Gate NOR Gates 11

81 NAND Gate WO k = O LA + LB VOL (NAND) > V OL (Inverter) OR Gates 12

82 AND Gates Example 13

83 AOI (AND-OR-INVERT) Gates Examples 14

84 XOR/XNOR Gates Hysteresis 15

85 Schmitt Trigger Transmission Gate 16

86 Transmission Gate Array CMOS Logic 17

87 CMOS Inverter CMOS Inverter 18

88 Symmetric CMOS Inverter Capacitance Effect on Transition

89 Capacitance Effect on Transition - 2 Electrostatic Discharge (ESD) Protection 20

90 CMOS Gates Symbol Shorthands 21

91 CMOS NAND Gate CMOS NAND Gates 22

92 CMOS NOR Gate CMOS NOR Gates 23

93 CMOS AND/NAND Gate CMOS OR/NOR Gate 24

94 CMOS AOI Gates CMOS AOI Gates 25

95 CMOS AND-OR Gate CMOS OAI Gates 26

96 CMOS AOI Gates Example 27

97 Example 28

98 XOR Gate 29

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