HC5503PRC SLIC and the IDT Quad PCM CODEC with Programmable Gain

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1 HC5503PC SLIC and the IDT Quad PCM CODEC with Programmable Gain Application Note AN352 eference Design Using the HC5503PC SLIC and the IDT Quad PCM CODEC with Programmable Gain The network requirements of many countries require the analog subscriber line circuit (SLIC) to terminate the subscriber line with an impedance for voiceband frequencies which is complex, rather than resistive (e.g., 600Ω). This requires that the physical resistance that is situated between the SLIC and the subscriber line, comprised of protection and/or sensing resistors, and the output resistance of the SLIC itself, be adapted to present an impedance to the subscriber line that varies with frequency. This is accomplished using feedback around the SLIC. The purpose of this application note is to show a means of accomplishing this task for the HC5503PC and the IDT Quad PCM CODEC [1]. Discussed in this application note are the following: 2wire 600Ω impedance matching 2wire complex impedance matching eceive gain (4wire to 2wire) and transmit gain (2wire to 4wire) calculations Transhybrid balance calculations eference design for 600Ω 2wire load eference design for China complex 2wire load Author: Don LaFontaine and Chris Ludeman(Intersil) 2*p 2*s x2 FEED AMPS FOM COMBO Vs. Z SLIC TANSMIT x2 f(z 0 ) TO COMBO Figure 1 Impedance Matching Block Diagram Impedance Matching Impedance matching of the HC5503PC to the subscriber load is important for optimization of 2wire return loss, which in turn cuts down on echoes in the endtoend voice communication path. It is also important for maintaining voice signal levels on long loops. Consider the equivalent circuit shown in Figure 1. The circuitry inside the dotted box is representative of the SLIC feed and transmit amplifiers. The feed and transmit amplifiers pass the voice signals in the receive and transmit directions respectively. Without the feedback block f(z 0 ), the termination resistance at would equal the two protection resistors ( ) and the two sense resistors ( ), as the feed amplifiers present a very low output impedance to the subscriber line. The desired termination impedance at is Z 0. The feedback block f(z 0 ) matches the SLICs output impedance (Z SLIC ) plus the two protection resistors ( ) and the two sense resistors ( ) to the load (Z 0 ). 1 of 10 April Integrated Device Technology, Inc. All rights reserved specifications subject to change without notice. DSC 6154/

2 Application Note AN352 V S IL V T T T F X 0.47µ f 2.5V a4 2 f 2 f VFO IDT QUAD CODEC 2.19dB D F a1 *4 Z SLIC INTESIL HC5503PC VFXI 1.309dB DX 2.5V T X 0.47µ 4 s Z01 Z 0 (100) GSX 4 I L Figure 2 Impedance Matching Impedance matching of the HC5503PC is accomplished by making the SLIC s impedance (Z SLIC, Figure 2) equal to the desired terminating impedance Z 0, minus the value of the protection and sense resistors. The desired impedance at the input to the SLIC is given in Equation 1. Z SLIC Z (EQ. 1) The AC loop current required to satisfy this condition is given in Equation 2. I L V T at matching (EQ. 2) ( Z ) The current calculated in Equation 2 is used as feedback to match the impedance of the SLIC and both protection and sense resistors to the load Z 0. The output voltage of the SLIC (VTX) is defined by design and given in Equation 3. 4 I L (EQ. 3) Substituting for I L from Equation 2 into Equation 3 results in the voltage at the VTX output that will be used to generate the required feedback. 4 V S V T TX ( Z ) (EQ. 4) By design, V T is equal to 2 times the voltage at the receive input (X) Figure 2. V T 2 x (EQ. 5) Substituting Equation 5 into Equation V X ( Z ) (EQ. 6) 2 of 10 April 2002

3 Application Note AN352 Solving Equation 6 for the voltage at as a function of (when matching the Z SLIC, the two protection resistors ( ) and the two sense resistors ( ) to the load ) is given in Equation 7. ( Z 0 2 p 2 ) 8 (EQ. 7) Equation 7 is the gain of the feedback circuit (output/input /) used to match the impedance of the SLIC and both protection and sense resistors. Note: In Equation 7 it seemed logical to simplify the numerator by trying to combine Z 0 and the two subsequent terms together. In practice however, the impedance of the network you want to match (Z 0 ) cannot easily have 2* p and 2* s subtracted from it since the sum of these resistors is often larger than the value of the series resistance of the complex network. Equation 7 is therefore rewritten in Equation 8. Z 0 ( ) (EQ. 8) Analysis of Equation 8 yields a 2 OpAmp feedback network. The first term has and no phase inversion. This requires the path to flow through 2 OpAmps and makes the matching of different complex loads easy. (i.e., can set in feedback network equal to the you want to match). The second term has a phase inversion and requires only one OpAmp in the feedback path. Figure 2 shows the circuit required to achieve matching of the SLIC s impedance to the load. The voltage at is a function of, ( / ) and. The voltage at is determined via superposition. The circuit equation for the feedback network is given in Equation 9. f V TX f V IN f (EQ. 9) a1 a4 For impedance matching of the two wire side, we set equal to zero. This reduces Equation 9 to that shown in Equation 10. f V TX f (EQ. 10) a1 To achieve the desired matching of the circuit to the line impedance, we set our design Equation 8 equal to our circuit Equation 10. By inspection of the correct phase in Equations 8 and 10, we have Equations 11 and 12. Z 0 8 f (EQ. 11) 2 ( ) 8 f (EQ. 12) a1 Given: f, 2, Note: by making 2 f, the value of becomes 4 (Equation 13). This results in the 2wire to 4 wire gain being equal to 1 (Equation 24 and Equation 25) From Equation (EQ. 13) S From Equation a1 (EQ. 14) 3 of 10 April 2002

4 Application Note AN352 eceive Gain ( to ) 4wire to 2wire gain is equal to the divided by the input voltage, reference Figure 3. The gain through the IDT is programmed for this example to one ( V D V VFO ). V A 2W 4W 2W (EQ. 15) The 2wire voltage is determined by a loop equation and is given in Equation 16. ( 2 2 ) I L V T (EQ. 16) Combining Equation 5 and Equation 9, gives an expression for V T in terms of, as shown in Equation 17. f V V T 2 2 TX f V IN f (EQ. 17) a1 a4 The voltage at V T is therefore a function of and. Note: contribution from (middle term in Equation 17) is zero due to the transhybrid circuit, reference section titled Transhybrid Balance G(44). This reduces Equation 17 to Equation 18. f V V T 2 2 IN f (EQ. 18) a1 Substituting 4 I L (Equation 3) for in Equation 18 and combining this with Equation 16, results in an equation for in terms of: I L, the external resistors and the input voltage (Equation 19). Ohms law defines I L as being equal to /. Substituting / for I L in Equation 19 gives Equation 20. a4 ( 2 2 ) I L 8 I f L 2 f (EQ. 19) a1 a4 V ( 2 2 ) 2W 8 f 2 f (EQ. 20) a1 Equation 20 can be rearranged to solve for the 4wire to 2wire gain /, as shown in Equation 21. a4 A 4W 2W (EQ. 21) 2 f a4 a1 a1 ( 2 2 ) a1 8 f Given: f100kω, a4200kω, a1267kω, ZO600Ω, S, P. Note: by making a4 equal to 2 f the 4wire to 2wire gain becomes 1. Transmit Gain across HC5503PC ( to ) The output voltage of the SLIC ( ) was defined in Equation 3 as being equal to 4 I L. I L is equal to twice the input voltage (2 ) divided by the total loop resistance as shown in Figure 4. If the load impedance is 600Ω, then the gain across the HC5503PC is 2/3 (400/600) the input voltage. Transmit Gain ( to ) 2wire to 4wire gain is equal to the voltage divided by the 2wire voltage, reference Figure 3. V A GSX 2W 4W (EQ. 22) 4 of 10 April 2002

5 Application Note AN352 LOOP EQUATION I L (2 2 ) I L V T V T T F X F INTESIL HC5503PC 0.47µ a4 2 f a1 f *4 2.5V 2 f 2.5V 0.47µ CA5470M Z 0 (100) VFO VFXI IDT QUAD CODEC 2.19dB 1.309dB D DX 2.5V T X 0.47µ 4 s Z01 Z 0 (100) GSX 4 I L Figure 3 eceive Gain G(42), Transmit Gain (24) and Transhybrid Balance A 24 V T FEEDBACK 1 TIP 4 I L 2 I L TOTAL s p Z L 600Ω 2 I L ING H C P C I L 600Ω p 4 I L Ω s 2 3 FEEDBACK Z L Figure 4 Transmit Gain Across HC of 10 April 2002

6 Application Note AN352 is only a function of and the feedback resistors and Equation 23. This is because is considered ground for this analysis, thereby effectively grounding the VFO input. Substituting Equation 3 for and IL for / into Equation 23, equals: is equal to (actual values of and a2 were multiplied by 100 to reduce loading effects on the OpAmps). Simplifying Equation 24 and assuming 4S from Equation 13 results in Equation 25. The transmit gain 2wire to 4wire is equal to one. TX V (EQ. 23) 4 (EQ. 24) A 2W 4W (EQ. 25) Transhybrid Balance G(44) Transhybrid balance is a measure of how well the input signal is canceled (that being received by the SLIC) from the transmit signal (that being transmitted from the SLIC to the CODEC). Without this function, voice communication would be difficult because of the echo. The signals at V FO and (Figure 3) are in phase. Transhybrid balance is achieved by summing two signals that are equal in magnitude and opposite in phase into the GSX amplifier. The CA5470M opamp provides a signal that is equal in magnitude an opposite in phase from the V FO signal. Transhybrid balance is achieved by summing the output of the CA5470M signal with the output signal from the HC5503PC, when the proper gain adjustments are made to match V FO and magnitudes. For discussion purpose, the GSX amplifier is redrawn with the external resistors in Figure 5. Z01 V FO VFXI GSX Figure 5 Transhybrid Balance Circuit The gain through the GSX amplifier from is set by resistors and Z01. Both resistors ( and Z01 ) are used in the feedback loop to match the two wire impedance, and thus set. The gain through the GSX amplifier from V FO is set by resistors and Z01. Matching of the magnitudes for transhybrid balance will be accomplished using resistor. Using superposition for both inputs to the GSX amplifier and setting both gains equal to each other yields Equation 26. Cancelling out Z01, setting equal to 400/Z L times (V FO ) and rearranging to solve for results in Equation 27. The values of,, and should be scaled by 100 to minimize loading of the GSX amplifier (Figure 5). 2.5V Z01 VFO Z01 (EQ. 26) VFO Z L (EQ. 27) of 10 April 2002

7 Application Note AN352 eference Design of the HC5503PC and the IDT With a 600Ω Load Impedance The design criteria is as follows: 4wire to 2wire gain (PCMIN to ) equal 0dB 2wire to 4wire gain ( to PCMOUT) equal 0dB Two Wire eturn Loss greater than 30dB (200Hz to 4kHz) p 50, s 100. Figure 6 gives the reference design using the Intersil HC5503PC SLIC and the IDT Quad Combo. Also shown in Figure 5 are the voltage levels at specific points in the circuit. These voltages will be used to adjust the gains of the network. Impedance Matching For impedance matching of the 2wire side we set the input voltage at D equal to zero. This effectively grounds the V FO input of the GSX amplifier. To determine the value of to achieve a 2wire to 4wire gain ( to DX) of 0dB we use Equation 24, repeated here for convenience in Equation 28. The programmed transmit and receive gains of the IDT are set to 0dB for this application. 4 (EQ. 28) Substituting the required voltage levels (Figure 6) for (0.7745) and (0.7745) and rearranging to solve for results in Equation 29. Where: / 1.0, and Z 0 Z01 : (EQ. 29) 1.0 The value of needs to be scaled by 100 to minimize the effects of loading on the GSX amplifier. The nearest standard value for is 40.2kΩ. needs to be adjusted by / to maintain the same feedback for impedance matching Equation 30. ( 200kΩ) ( 1.0) 200kΩ (EQ. 30) The closest standard value is for is 200kΩ. Transhybrid Balance (Z L 600Ω) The internal GSX amplifier of the IDT is used to perform the transhybrid balance function. Equation 27, repeated here in Equation 31, is used to determine the value of for proper transhybrid balance. The values of,, and should be scaled by 100 to minimize loading of the GSX amplifier. is equal to (0.7745V MS )(2/3). V FO is equal to V MS. Closest standard value for a5 is 60.4kΩ V FO Z L (EQ. 31) 400 Z L K Ω 600Ω 60.3 k Ω (EQ. 32) 400Ω 7 of 10 April 2002

8 Application Note AN352 G V MS 600Ω T F X F INTESIL HC5503PC 2.5V a4 200K f 100k 200K a1 267k 60.4k V MS 2.5V CA5470M VFO IDT QUAD CODEC 0dB V MS D PCM Bus 4 I L VFXI 0dB DX 2.5V T X 40.2k Z k GSX V MS 3.52dBm0 (600Ω) (0.7745)(2/3)V MS (2/3) V MS G24 Figure 6 reference Design of the HC5503PC and the IDT with a 600Ω Load Impedance Specific Implementation for China The design criteria for a China specific solution are as follows: Desired line circuit impedance is //0.1µF eceive gain ( /V PCMIN ) is 3.5dB Transmit gain (V PCMOUT / ) is 0dB 0dBm0 is defined as 1mW into the complex impedance at 1020Hz p 50, s 100. Figure 7 gives the reference design using the Intersil HC5503PC SLIC and the IDT Quad Combo. Also shown in Figure 7 are the voltage levels at specific points in the circuit. These voltages will be used to adjust the gains of the network. Adjustment to Get 3.5dBm0 at The Load eferenced to 600Ω The voltage equivalent to 0dBm0 into 811Ω (0dBm0 (811Ω) ) is calculated using Equation 33. China complex 1kHz is equal to 811Ω. 0dBm ( 811Ω) 10 The gain referenced back to is equal to: The adjustment to get 3.5dBm0 at the load referenced to 600Ω is: V 2 log V (EQ. 33) 811( 0.001) MS V GAIN 20log MS 1.309dB (EQ. 34) V MS Adjustment 3.5dBm dBm0 2.19dB (EQ. 35) The voltage at the load (referenced to 600Ω) is given in Equation 36: 2.19dBm 600Ω ( ) 10 V 2 log V (EQ. 36) 600( 0.001) MS 8 of 10 April 2002

9 Application Note AN352 Impedance Matching For impedance matching of the 2wire side we set the input voltage at D equal to zero. To determine the value of to achieve a 2wire to 4wire gain ( to DX) of 0dB we use Equation 24, repeated in Equation (EQ. 37) Substituting the required voltage levels Figure 7) for ( ) and ( ) and rearranging to solve for results in Equation 39. Where:, and Z 0 Z01 : 400 a k (EQ. 38) 1 G42 V2W 2.19dBm0 (600Ω) V MS 200Ω 681Ω 0.1µF T F X F INTESIL HC5503PC 2.5V a4 200k f 100k 200k a1 267k 68.1k 2.19dBm0 (600Ω) V MS V MS IDT V PWO QUAD CODEC VFO 2.19dB D 2.5V CA5470M 1nF PCM Bus T X 20k Z01 1nF VFXI 2.5V 1.309dB DX 40.2k 20k 68.1k GSX 2.19dBm0 (600Ω) V MS 8.32dBm0 (600Ω) ( )(400/811)V MS (400/811) G24 3.5dBm0 (600Ω) V MS Figure 7 eference Design of the HC5503PC and the IDT with Cchina Complex Load Impedance The value of needs to be scaled by 100 to minimize the effects on the GSX amplifier. The nearest standard value for is 40.2kΩ. needs to increase by the ratio / (1 for this example) to maintain the same feedback for impedance matching as shown in Equation 39. ( 200kΩ) ( 1) 200kΩ (EQ. 39) The closest standard value is for is 200kΩ. Programming the Gain of the IDT To achieve a receive gain (V2W / VDX) of 3.5dB at the load referenced to 600Ω, the IDT receive gain must be programmed to 2.19dB. To achieve a transmit gain (V DX / ) of 0dB, the IDT transmit gain must be programmed to 1.309dB. 9 of 10 April 2002

10 Application Note AN352 Transhybrid Balance (Z L //0.1µF) The internal GSX amplifier of theidt is used to perform the transhybrid balance function. Equation 27, repeated here in Equation 40, is used to determine the value of for proper transhybrid balance. is equal to ( V MS )(400/811). V PWO is equal to V MS. Closest standard values, a5 20kΩ 68.1kΩ II 1nF. The values of,, and should be scaled by 100 to minimize loading of the GSX amplifier. Scaling of a complex load is shown in Equation 46. Note: When matching a complex impedance some impedance models ( µF, K100) will cause the OpAmp feedback to be open at DC currents, bringing the OpAmp to an output rail. A resistor with a value of about 10 times the reactance of the capacitor (21.6nF) at the low frequency of interest (200Hz for example) can be placed in parallel with the capacitor in order to solve the problem (368kΩ for a 21.6nF capacitor). eference [1] Website VFO Z L (EQ. 40) 400 Z L KΩ 200Ω 680ΩII0.1µF (EQ. 41) 400Ω or ZO2 100( esistive) eactive (EQ. 42) 100 COPOATE HEADQUATES 2975 Stender Way Santa Clara, CA for SALES: or fax: for Tech Support: telecomhelp@idt.com 10 of 10 April 2002

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