4 Mbit (256K x 16) Static RAM

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4 Mbit (256K x 16) Static RAM Features Temperature Ranges Industrial: 40 C to 85 C Automotive-A [1] : 40 C to 85 C Automotive-E [1] : 40 C to 125 C Pin and Function compatible with CY7C1041CV33 High

1 4 Mbit (256K x 16) Static RAM Features Temperature Ranges Industrial: 40 C to 85 C Automotive-A [1] : 40 C to 85 C Automotive-E [1] : 40 C to 125 C Pin and Function compatible with CY7C1041CV33 High Speed t AA = 10 ns Low Active Power I CC = 90 ma at 10 ns (industrial) Low CMOS Standby Power I SB2 = 10 ma 2.0V Data Retention Automatic Power Down when deselected TTL compatible Inputs and Outputs Easy Memory Expansion with and OE features Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded SOJ, and 44-pin TSOP II Packages Functional Description The CY7C1041DV33 is a high performance CMOS Static RAM organized as 256K words by 16 bits. To write to the device, take Chip Enable () and Write Enable () inputs LOW. If Byte LOW Enable (BLE) is LOW, then data from I/O pins (I/O 0 to I/O 7 ) is written into the location specified on the address pins (A 0 to A 17 ). If Byte HIGH Enable (BHE) is LOW, then data from I/O pins (I/O 8 to I/O 15 ) is written into the location specified on the address pins (A 0 to A 17 ). To read from the device, take Chip Enable () and Output Enable (OE) LOW while forcing the Write Enable () HIGH. If BLE is LOW, then data from the memory location specified by the address pins appears on I/O 0 to I/O 7. If BHE is LOW, then data from memory appears on I/O 8 to I/O 15. See the Truth Table on page 9 for a complete description of read and write modes. The input and output pins (I/O 0 to I/O 15 ) are placed in a high impedance state when the device is deselected ( HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation ( LOW and LOW). The CY7C1041DV33 is available in a standard 44-pin 400-mil wide SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout and a 48-ball fine-pitch ball grid array (FBGA) package. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram INPUT BUFFER A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 ROW DECODER 256K 16 SENSE AMPS IO 0 IO 7 IO 8 IO 15 COLUMN DECODER A9 A10 A11 A12 A13 A AA16 A17 BHE OE BLE Note 1. Automotive product information is preliminary. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document #: Rev. *F Revised July 24, 2009

2 Selection Guide Description 10 (Industrial) 10 (Automotive-A) [1] 12 (Automotive-E) [1] Unit Maximum Access Time ns Maximum Operating Current ma Maximum CMOS Standby Current ma Pin Configuration Figure Ball VFBGA (Pinout 1) [2, 3] Figure Ball VFBGA (Pinout 2) [2, 3] BLE OE A 0 A 1 A 2 A BLE OE A 0 A 1 A 2 A IO 0 BHE A 3 A 4 IO 8 B IO 8 BHE A 3 A 4 IO 0 B IO 1 IO 2 A 5 A 6 IO 10 IO 9 C IO 9 IO 10 A 5 A 6 IO 1 IO 2 C V SS IO 3 A 17 A 7 IO 11 D V SS IO 11 A 17 A 7 IO 3 D IO 4 A 16 IO 12 V SS E IO 12 A 16 IO 4 V SS E IO 6 IO 5 A 14 A 15 IO 13 IO 14 F IO 14 IO 13 A 14 A 15 IO 5 IO 6 F IO 7 A 12 A 13 IO 15 G IO 15 A 12 A 13 IO 7 G A 8 A 9 A 10 A 11 H A 8 A 9 A 10 A 11 H Figure Pin SOJ/TSOP II A 0 A 1 A 2 A 3 A 4 IO 0 IO 1 IO A 17 A 16 A 15 OE BHE BLE IO 15 IO 14 IO 13 IO IO V SS V SS 33 IO 4 32 IO 11 IO IO 10 IO IO 9 IO IO A 5 A A 13 A A A 11 A Notes 2. pins are not connected on the die. 3. Pinout 1 is compliant with CY7C1041CV33 and pinout 2 is JEDEC compliant. The difference between the two is that the higher and lower byte I/Os (I/O [7:0] and I/O [15:8] balls) are swapped. Document #: Rev. *F Page 2 of 13

3 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature C to +150 C Ambient Temperature with Power Applied C to +125 C Supply Voltage on Relative to GND [5] V to +4.6V DC Voltage Applied to Outputs in High-Z State [5] V to +0.3V DC Input Voltage [5] V to +0.3V Current into Outputs (LOW) ma Static Discharge Voltage......>2001V (MIL-STD-883, Method 3015) Latch Up Current... >200 ma Operating Range Range Ambient Temperature Speed Industrial 40 C to +85 C 3.3V ± 0.3V 10 ns Automotive-A [1] 40 C to +85 C 3.3V ± 0.3V 10 ns Automotive-E [1] 40 C to +125 C 3.3V ± 0.3V 12 ns DC Electrical Characteristics Over the Operating Range 10 (Industrial) 10 (Automotive-A) [1] 12 (Automotive-E) [1] Parameter Description Test Conditions Unit Min Max Min Max Min Max V OH Output HIGH Voltage = Min, I OH = 4.0 ma V V OL Output LOW Voltage = Min, I OL = 8.0 ma V [5] V IH Input HIGH Voltage V [5] V IL Input LOW Voltage V I IX Input Leakage Current GND < V I < μa I OZ Output Leakage GND < V OUT <, Output μa Current Disabled I CC I SB1 I SB2 Operating Supply Current Automatic Power Down Current TTL Inputs Automatic Power Down Current CMOS Inputs = Max, 100 MHz ma f = f MAX = 1/t RC 83 MHz ma 66 MHz ma 40 MHz ma Max, > V IH V IN > V IH or V IN < V IL, f = f MAX Max, > 0.3V, V IN > 0.3V, or V IN < 0.3V, f = ma ma Note 5. Minimum voltage is 2.0V and V IH (max) = + 2V for pulse durations of less than 20 ns. Document #: Rev. *F Page 3 of 13

4 Capacitance [6] Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, = 3.3V 8 pf C OUT I/O Capacitance 8 pf Thermal Resistance [6] Parameter Description Test Conditions Θ JA Θ JC Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Still Air, soldered on a inch, four layer printed circuit board FBGA Package SOJ Package TSOP II Package Unit C/W C/W AC Test Loads and Waveforms The AC test loads and waveform diagram follows. [7] 10 ns device OUTPUT * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT High-Z Characteristics 3.3V OUTPUT 5 pf Z = 50Ω R 317Ω 50 Ω 1.5V (a) R2 351Ω 30 pf* 3.0V GND Rise Time: 1 V/ns 90% 10% ALL INPUT PULSES 90% 10% (b) Fall Time: 1 V/ns (c) Notes 6. Tested initially and after any design or process changes that may affect these parameters. 7. AC characteristics (except High-Z) are tested using the load conditions shown in AC Test Loads and Waveforms (a). High-Z characteristics are tested for all speeds using the test load shown in (c). Document #: Rev. *F Page 4 of 13

5 AC Switching Characteristics Over the Operating Range [8] 10 (Industrial) 10 (Automotive-A) [1] 12 (Automotive-E) [1] Parameter Description Unit Min Max Min Max Min Max Read Cycle [9] t power (Typical) to the First Access μs t RC Read Cycle Time ns t AA Address to Data Valid ns t OHA Data Hold from Address Change ns t A LOW to Data Valid ns t DOE OE LOW to Data Valid ns t LZOE OE LOW to Low-Z ns t HZOE OE HIGH to High-Z [10, 11] ns t LZ LOW to Low-Z [11] ns t HZ HIGH to High-Z [10, 11] ns t PU LOW to Power Up ns t PD HIGH to Power Down ns t DBE Byte Enable to Data Valid ns t LZBE Byte Enable to Low-Z ns t HZBE Byte Disable to High-Z ns [12, 13] Write Cycle t WC Write Cycle Time ns t S LOW to Write End ns t AW Address Setup to Write End ns t HA Address Hold from Write End ns t SA Address Setup to Write Start ns t P Pulse Width ns t SD Data Setup to Write End ns t HD Data Hold from Write End ns t LZ HIGH to Low-Z [11] ns t HZ LOW to High-Z [10, 11] ns t BW Byte Enable to End of Write ns Notes 8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and 30-pF load capacitance. 9. t POR gives the minimum amount of time that the power supply should be at typical values until the first memory access is performed. 10. t HZOE, t HZ, t HZBE, and t HZ are specified with a load capacitance of 5 pf as in part (c) of AC Test Loads and Waveforms. Transition is measured when the outputs enter a high impedance state. 11. At any given temperature and voltage condition, t HZ is less than t LZ, t HZOE is less than t LZOE, t HZBE is less than t LZBE, and t HZ is less than t LZ for any given device. Document #: Rev. *F Page 5 of 13

6 Data Retention Characteristics Over the Operating Range Parameter Description Conditions [14] Min Max Unit V DR for Data Retention 2.0 V I CCDR Data Retention Current = V DR = 2.0V, > 0.3V, Industrial 10 ma V IN > 0.3V or V IN < 0.3V Auto-A [1] 10 ma Auto-E [1] 15 ma t [6] CDR Chip Deselect to Data Retention Time 0 ns t [15] R Operation Recovery Time t RC ns Data Retention Waveform 3.0V DATA RETENTION MODE V DR > 2V 3.0V t CDR t R Switching Waveforms Figure 4. Read Cycle No. 1 [16, 17] t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes 12. The internal write time of the memory is defined by the overlap of LOW and LOW. and must be LOW to initiate a write and the transition of either of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 13. The minimum write cycle time for Write Cycle No. 4 ( controlled, OE LOW) is the sum of t HZ and t SD. 14. No input may exceed + 0.3V. 15. Full device operation requires linear ramp from V DR to (min.) > 50 μs or stable at (min.) > 50 μs. 16. Device is continuously selected. OE,, BHE, and BHE = V IL. 17. is HIGH for read cycle. Document #: Rev. *F Page 6 of 13

7 Switching Waveforms (continued) Figure 5. Read Cycle No. 2 (OE Controlled) [17, 18] ADDRESS t RC t A OE BHE, BLE t DOE t LZOE t HZOE t DBE t HZ DATA OUT t LZBE HIGH IMPEDAN DATA VALID t HZBE HIGH IMPEDAN SUPPLY CURRENT t LZ t PU 50% t PD 50% IICC IISB [19, 20] Figure 6. Write Cycle No. 1 ( Controlled) t WC ADDRESS t SA t S t AW t HA t P tbw BHE, BLE t SD t HD DATAI/O Notes 18. Address valid prior to or coincident with transition LOW. 19. Data I/O is high impedance if OE or BHE and BLE = V IH. 20. If goes HIGH simultaneously with going HIGH, the output remains in a high impedance state. Document #: Rev. *F Page 7 of 13

8 Switching Waveforms (continued) Figure 7. Write Cycle No. 2 (BLE or BHE Controlled) ADDRESS t WC BHE,BLE t SA t BW t AW t HA t P t S t SD t HD DATAI/O Figure 8. Write Cycle No. 3 ( Controlled, OE HIGH During Write) [19, 20] t WC ADDRESS t S t AW t HA t SA t P OE BHE,BLE t SD t HD DATA I/O NOTE 21 t HZOE DATAIN VALID Note 21. During this period the I/Os are in the output state and input signals should not be applied. Document #: Rev. *F Page 8 of 13

9 Switching Waveforms (continued) Figure 9. Write Cycle No. 4 ( Controlled, OE LOW) ADDRESS t WC t S t SA t AW t P t HA t BW BHE, BLE t HZ t SD t HD DATA I/O NOTE 21 t LZ Truth Table OE BLE BHE I/O 0 I/O 7 I/O 8 I/O 15 Mode Power H X X X X High-Z High-Z Power Down Standby (I SB ) L L H L L Data Out Data Out Read All Bits Active (I CC ) L L H L H Data Out High-Z Read Lower Bits Only Active (I CC ) L L H H L High-Z Data Out Read Upper Bits Only Active (I CC ) L X L L L Data In Data In Write All Bits Active (I CC ) L X L L H Data In High-Z Write Lower Bits Only Active (I CC ) L X L H L High-Z Data In Write Upper Bits Only Active (I CC ) L H H X X High-Z High-Z Selected, Outputs Disabled Active (I CC ) Document #: Rev. *F Page 9 of 13

10 Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 10 CY7C1041DV33-10BVI Ball VFBGA Industrial CY7C1041DV33-10BVXI 48-Ball VFBGA (Pb-Free) Pinout - 1 [3] CY7C1041DV33-10BVJXI 48-Ball VFBGA (Pb-Free) Pinout - 2 [3] CY7C1041DV33-10VXI Pin (400-mil) Molded SOJ (Pb-Free) CY7C1041DV33-10ZSXI Pin TSOP II (Pb-Free) 10 CY7C1041DV33-10BVXA Ball VFBGA (Pb-Free) Pinout - 1 [3] Automotive-A [1] CY7C1041DV33-10ZSXA Pin TSOP II (Pb-Free) 12 CY7C1041DV33-12BVXE Ball VFBGA (Pb-Free) Pinout - 1 [3] Automotive-E [1] CY7C1041DV33-12BVJXE 48-Ball VFBGA (Pb-Free) Pinout - 2 [3] CY7C1041DV33-12VXE Pin (400-mil) Molded SOJ (Pb-Free) CY7C1041DV33-12ZSXE Pin TSOP II (Pb-Free) Please contact your local Cypress sales representative for availability of these parts Package Diagrams A1 CORNER TOP VIEW Figure Ball VFBGA (6 x 8 x 1 mm) ( ) BOTTOM VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X) A A B B C C 8.00±0.10 D E F G 8.00± D E F G H H A A B 6.00± B 6.00± C 0.55 MAX. 0.21± C 0.15(4X) *D SEATING PLANE 0.26 MAX. C 1.00 MAX a Document #: Rev. *F Page 10 of 13

11 Package Diagrams(continued) Figure Pin (400-mil) Molded SOJ ( ) *B Figure Pin TSOP II ( ) *A Document #: Rev. *F Page 11 of 13

12 Document History Page Document Title: CY7C1041DV33 4 Mbit (256K x 16) Static RAM Document Number: Rev. ECN No. Orig. of Change Submission Date Description of Change ** SWI See ECN Advance Data sheet for C9 IPP *A RKF See ECN 1.AC, DC parameters are modified as per EROS(Spec # ) 2.Pb-free offering in the Ordering information *B PCI See ECN Changed from Advance to Preliminary Removed 15 and 20 ns Speed bin Corrected DC voltage (min) value in maximum ratings section from to - 0.3V Redefined I CC values for Com l and Ind l temperature ranges I CC (Com l): Changed from 100, 80 and 67 ma to 90, 80 and 75 ma for 8, 10 and 12ns speed bins respectively I CC (Ind l): Changed from 80 and 67 ma to 90 and 85 ma for 10 and 12ns speed bins respectively Added Static Discharge Voltage and latch-up current spec Added V IH(max ) spec in Note# 2 Changed Note# 4 on AC Test Loads Changed reference voltage level for measurement of Hi-Z parameters from ±500 mv to ±200 mv Added Data Retention Characteristics/Waveform and footnote # 11, 12 Added Write Cycle ( Controlled, OE HIGH During Write) Timing Diagram Changed Package Diagram name from 44-Pin TSOP II Z44 to 44-Pin TSOP II ZS44 and from 44-Pin (400-mil) Molded SOJ V34 to 44-Pin (400-mil) Molded SOJ V44 Changed part names from Z to ZS in the Ordering Information Table Added 8 ns Product Information Added Pin-Free Ordering Information Shaded Ordering Information Table *C NXR See ECN Converted from Preliminary to Final Removed -8 speed bin Removed Commercial Operating Range product information Included Automotive Operating Range product information Updated Thermal Resistance table Updated footnote #8 on High-Z parameter measurement Updated the ordering information and replaced Package Name column with Package Diagram in the Ordering Information Table *D VKN See ECN Added -10BVI product ordering code in the Ordering Information table *E VKN/PYRS 07/22/08 Added -10BVJXI part *F VKN 08/18/2009 Added Automotive-A information For 12 ns speed, changed I SB1 spec from 25 ma to 15 ma For 12 ns speed, changed t DOE and t DBE specs from 6 ns to 7 ns Updated ordering information table Document #: Rev. *F Page 12 of 13

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13 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, ILUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: Rev. *F Revised July 24, 2009 Page 13 of 13 All product and company names mentioned in this document are the trademarks of their respective holders.

2-Mbit (128K x 16)Static RAM

2-Mbit (128K x 16)Static RAM Features Functional Description Pin-and function-compatible with CY7C1011CV33 High speed t AA = 10 ns Low active power I CC = 90 ma @ 10 ns (Industrial) Low CMOS standby power