Digital Integrated Circuits EECS 312. Review. Dependence of delay on width (R) Lab 3. Intuition. Inverter chain delay optimization

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1 IBM ES9000 Bipolar Fujitsu VP000 IBM 3090S Pulsar 4 IBM 3090 IBM Y6 CDC Cyber 05 IBM 4381 IBM Y4 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium IIDSIP) Fujitsu M-780 Year of announcement IBM Y5 CMOS Jayhawkdual) IBM Y7 Prescott -ex Mckinley Squadrons IBM GP IBM Z9 Pentium adio eceive for Mesh Maintenance - 6 ma ypical Current Draw 1 sec Heartbeat 30 beats per sample Sampling and adio ransmission 9-15 ma Low Power Sleep ma Heartbeat 1 - ma ime seconds) Digital Integrated Circuits EECS 31 eview eacher: obert Dick Office: 417-E EECS dickrp@umich.edu Phone: Cellphone: HW engineers SW engineers GSI: Shengshou Lu Office: 75 BBB luss@umich.edu Current ma) Design a non-trivial logic gate. What happens to inverter delay as the driving MOSFE widths are increased? What happens to inverter delay as the driven MOSFE widths are increased? What impact does non-instantaneous rise/fall time have on the propagation delay for the subsequent logic stage? Power density Watts/cm ) obert Dick Digital Integrated Circuits Lab 3 Dependence of delay on width ) Input inverters. Implications of sizing on energy consumption. Derive and explain. Fix L C L and vary W. Eventually, self-loading dominates. 3 obert Dick Digital Integrated Circuits 5 obert Dick Digital Integrated Circuits Inverter chain delay optimization Intuition Given Size width) of first inverter in chain, Driven load, ransistors are minimal length, and W p/w n approximately balances t phl and t plh. Find Optimal number of inverters in chain and Optimal size width) of each inverter to minimize chain delay. Given two inverters first fixed) and a large load C L ), how should the second be sized to minimize delay? C G C G1 minimal)? C G > C L? C G C L? Some other setting? Why? 6 obert Dick Digital Integrated Circuits 7 obert Dick Digital Integrated Circuits

2 Derivation I Let W W n W p / p n phl plh 0.69C L C i 3 W i+1 W unit C unit t p 0.69C int +C L ) Derivation II Consider the impact of scaling factor S. t p0 : Intrinsic delay. t p 0.69 S SC int 1+ C L t p 0.69C int 1+ C L t p t p0 1+ C ) L SC int Scaling doesn t impact intrinsic delay. Scaling does impact total delay. t p t p0 as S. Diminishing returns with increasing S. SC int SC int ) )) 8 obert Dick Digital Integrated Circuits 9 obert Dick Digital Integrated Circuits Consider chain of inverters I Consider chain of inverters II Given that t p,chain t p1 +t p + +t pn t pi t p0 1+ C ) g,i+1 t p,chain i1 t pi t p,chain t p0 i1 γc g,i 1+ C ) g,i+1 γc g,i and γ C int C g 1 technology-dependent constant). C g,+1 C L 10 obert Dick Digital Integrated Circuits 11 obert Dick Digital Integrated Circuits Sketch of derivation Sizing for optimal inverter chain delay For each i, find σt p,chain/σc g,i. Solve for σt p,chain/σc g,i 0, i1. esult is C g,i+1 C g,i C g,i C g,i 1. Each stage size geometric mean of previous and next: C g,i C g,i 1 C g,i+1. Constant factor relates sizing of all adjacent gate pairs. Each stage has same delay. Optimal stage-wise sizing factor: CL C g,1. Minimum path delay: t p,chain t p0 1+ CL C g,1 /γ ) 1 obert Dick Digital Integrated Circuits 13 obert Dick Digital Integrated Circuits

3 Example of inverter sizing Optimizing I Given C L 16C Per-stage scaling factor: 4 16C 1 /C 1 Let Φ C L C g,1 ) Φ t p,chain t p0 1+ γ d t p,chain d γ + ΦlnΦ) Φ 14 obert Dick Digital Integrated Circuits 15 obert Dick Digital Integrated Circuits Optimizing II Set this to zero. Let φ Φ 0 γ +φ φln φ ) 0 γ φ +1 ln φ ) 0 γ lnφ) +1 φ 0 γ φ +1 lnφ) Optimizing III φ e γ/φ+1 Hard to deal with this for γ 0. Consider implications for γ 0. φ e lnφ) γ φ obert Dick Digital Integrated Circuits 17 obert Dick Digital Integrated Circuits Optimal stage sizing factor t p,chain Φ) Φ Unbuffered Optimal ,000 1, ,000 10, Optimal tapering factor for γ 0: e for γ obert Dick Digital Integrated Circuits 19 obert Dick Digital Integrated Circuits

4 Buffering example Upcoming topics Interconnect. Alternative logic design styles. 0 obert Dick Digital Integrated Circuits 1 obert Dick Digital Integrated Circuits eview How can the optimal number of inverters in a load-driving chain be determined? How can the optimal size of each inverter in the chain be decided? How do determine optimal sizes of logic gates in arbitrary structures? May cover this near end of course. Do example problem. Derive and explain. Power consumption in synchronous CMOS P P SWICH +P SHO +P LEAK P SWICH C V DD f A P SHO b 1 V DD V ) 3 f A t P LEAK V DD I SUB +I GAE +I JUCIO +I GIDL ) C : total switched capacitance f : switching frequency b : MOS transistor gain t : rise/fall time of inputs V DD : high voltage A : switching activity V : threshold voltage P SHO usually 10% of P SWICH Smaller as V DD V A < 0.5 for combinational nodes, 1 for clocked nodes. obert Dick Digital Integrated Circuits easons for power consumption Dynamic Charging and discharging C loads. E dyn C L V DD. P dyn C L V DD f. But f V DD. So P dyn C L V DD 3. Static Sub-threshold leakage. Gate leakage. Short-circuit: Pull-up and pull-down networks briefly both on. Fixed voltage charging V DD V DD V t)i t)dt V t) V t) dt V DD e V t /C DDe t/c dt V DD C V DD C C e t / dt 0 1) ) e t /C 5 obert Dick Digital Integrated Circuits

5 Fixed current charging I V t)i t)dt Let be the voltage ramp duration, I is fixed. V is fixed. Fixed current charging II V q C V DD I C I CV DD V I I t)v t)dt CV DD V DD C CV DD dt 1dt 7 obert Dick Digital Integrated Circuits 8 obert Dick Digital Integrated Circuits Fixed current charging III Break-even point V DD C V DD C V DD C C V DD C Properly controlling V t). Performance. V DD C 1 C C C In limit, permits reversible computation with low/no power consumption during charging and discharging. 9 obert Dick Digital Integrated Circuits 30 obert Dick Digital Integrated Circuits Charging methods summary Capacitive load modeling It) influences energy consumption for same change in V. In theory, keeping voltage differences very small can permit extremely low-power operation. Leakage, current control, and preserving reversiblity make this challenging. 31 obert Dick Digital Integrated Circuits 33 obert Dick Digital Integrated Circuits

6 Interconnect capacitance C ǫ ox t ox WL 34 obert Dick Digital Integrated Circuits 35 obert Dick Digital Integrated Circuits Permittivity k) Fringing Material ǫ Vacuum 1 Aerogels 1.5 Polyimides 3 4 SiO 3.9 Glass-epoxy 5 Si Alumina 9.5 Silicon 11.7 c wire c pp +c fringe W ǫ ox + πǫ ox t ox logt ox /H) 36 obert Dick Digital Integrated Circuits 37 obert Dick Digital Integrated Circuits rends in interconnect design Upcoming topics More metal layers. Lower aspect ratios. More coupling. Smaller transistors, but similar-length global interconnect. Alternative logic design styles. Latches and flip-flops. Memories. 38 obert Dick Digital Integrated Circuits 39 obert Dick Digital Integrated Circuits

7 assignment 10 October:. 10 October: ead sections 5.4, 5.5, 5.6, and 3.5 in J. abaey, A. Chandrakasan, and B. ikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, October: ead sections 6..1, 4.1, and 4.3. in J. abaey, A. Chandrakasan, and B. ikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, 003. October: Lab obert Dick Digital Integrated Circuits

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