Compact Modeling of Ultra Deep Submicron CMOS Devices

Transcription

1 Compact Modeling of Ultra Deep Submicron CMOS Devices Wladyslaw Grabinski*, Matthias Bucher, Jean-Michel Sallese, François Krummenacher Swiss Federal Institute of Technology (EPFL), Electronics Laboratory, CH-115 Lausanne, Switzerland * Motorola, Modeling and Characterization Lab, CH-118 Le Grand Saconnex, Switzerland Trends of the MOSFET Devices Scaling Challenges of the Compact Modeling The EPFL EKV v.6 Model Model Formulation Recent Developments Analog and RF Application of the EKV v.6 Model Trends of the MOSFET Devices Scaling Channel Dimensions 1um 1um 1nm 1nm 4k 8k 64k 56k Clasic CMOS 1M Neuron Level Quantum Level 4M DRAM Production 16M 64M 56M 1G 4G 16G 64G56G Research Labs 1nm 1A Years Predictable Moor s Law Technology Limitations Physical Limitations

2 State-of-art CMOS Technology CL15LV CL15H CL15LP Core Voltage 1. V V V Gate Dielectric - Core- IO, Analog Option Dual Å 7/5 Å Dual 7 Å 7 Å Dual 7 Å 7 Å Physical Gate.1 m.14 m.13 m M1:.39- m Contacted Metal Pitch M-6:.48- m M7:.9- m IOFF Spec. (worst case) < 1 na/ m < 1 na/ m <.5 na/ m Well Formation Isolation Super-steep retrograde Shallow trench isolation Salicide CoSi Metal Intermetal Dielectric AlCu or Cu, up to 7 layers Low-K Via Fill Lithography Tungsten or copper, with CMP Deep UV, with phase shifting mask TSMC Delivers Foundry's First.15 um Technology Development of the Compact Models 1 BSIM3v BSIM3v3 No. of Model Parameters 1 1 LEVEL LEVEL3 HSP8 BSIM BSIM BSIM3v3 BSIM BSIM3v BSIM4 BSIM HSP8 PCIM SP BSIM3v1 MM9 EKV v3. EKV v.6 LEVEL Number of DC model parameters vs. the year of the introduction of the model Years Including L,W,P scaling Without scaling Significant growth of the parameter number that includes geometry (W/L) scaling Most recent versions of the BSIM, EKV, MM and PCIM models are included

3 Compact Modeling Approaches Regional Approach: Easy to implement short-channel effects (but empirically), Simple implementation into simulation tools = fast execution Models are in public domain Discontinuous and ignores quantum effects Introduce Binning to improve scaliability Large number of parameters Surface Potential Based Approach: Most accurate, Needs iterative solution (no analytical solution), Complex implementation and slow execution time Hybrid Approach: Combines advantages of both presented approaches Good fitting demonstrated for.1um CMOS devices Public-domain model evolution: EKV Introduction of EKV model versions: 1994: v., first fully continuous model (1 parameters): continuous: weak/strong inversion, conduction/saturation symmetric forward/reverse operation: bulk reference drain current, capacitances, thermal noise, 1/f noise, NQS model mobility, velocity saturation, CLM, short-, narrow-channel effects 1995: v.3 (16 parameters): improved short-channel effects and RSCE, added substrate current 1996: new QS charge-conservative model 1997: v.6, applicable to deep sub- µm (.18µm) (18 parameters): coherent charge-based modeling of: static, QS, NQS and noise includes matching (statistical circuit simulation) 1999: v.6, new analytical NQS and polydepletion models : v3., has been announced

4 EKV v.6 MOSFET Model EKV v.6 available in major commercial circuit simulators: Antrim-AMS, Aplac, Eldo-Accusim, PSpice, Saber, SmartSpice, Smash, Spectre-RF, Star-HSpice. on-going implementations: ADS, MacSpice, Spice3, T-Spice, MINIMOS (TU Vienna), TRANZ-TRAN (TU Budapest) Visit: EKV model web site: < Charge-based Static Model B V S V D V G S G D V G S G I D D DL/ L eff DL/ x V S B VD y Bulk-reference, symmetric model structure. Drain current expression including drift and diffusion: I D V D Q I β V Q d β I ch V Q I = = d β ch d V = I ch F I R V S C ox V S C ox V D C ox (1) where: W eff β = µ C' ox L eff

5 Drain Current Normalization and Pinch-off Voltage Current normalization using the Specific current : I S I D = I F I R = I S ( i f i r ) = nβu T V P Pinch-off voltage accounts for... ( ) i f i r () V TO γ = ( qε s N sub ) C ox threshold voltage and substrate effect γ P V G V TO γ V G V + TO Ψ + -- γ = Ψ + -- (3) Slope factor n: n 1 V P = = V G γ Ψ + V P (4) Pinch-off Voltage Characteristic V G I B V S =V P VTO I S I ---- B = n β U T Pinch-off voltage measurement at constant current (I S /) Gate voltage V G is swept and V P =V S is measured at the source for a transistor biased in moderate inversion and saturation

6 EKV v.6 Model Structure Coherent model for static, dynamic and noise aspects. physical model basis leads to accurate description of transconductance-to-current ratio at all current levels allows to derive all other model quantities in a coherent way Transconductance to current ratio g ms U t I D g ms I D V S Static Model Dynamic Model Mobility Model Noise Model i f (V), i r (V) Q I,G,D,S,B (i f, i r ) µ s (Q B,Q I (i f, i r )) common variables to the entire model: normalized currents i f and i r (forward and reverse) S Nth (Q I (i f, i r )) Transconductance to Current Ratio.5um CMOS example.5um CMOS example Normalized transconductance-to-current ratio g ms U T I D vs. normalized current from weak thru moderate to strong inversion. D I S Measurement and simulation comparisons show that g ms /I D ratio is technology independent.

7 Mobility Model Influence of KP and E, respectively, on the transfer characteristic (low V DS ) Field- and position-dependent mobility: µ ( x) µ ' = where: E E 1 eff ( x) eff ( x) = E Q' B ( x) + η Q' inv ( x) ε ε si One parameter: E vertical critical field in the oxide No back-bias dependence needed due to inclusion of bulk charge (5) Reverse Short Channel Effect (RSCE).5um CMOS example.5um CMOS example Defect enhanced diffusion during fabrication leads to RSCE RSCE is modeled as a change in the threshold voltage depending on L eff Two model parameters Q and LK

8 Velocity Saturation Influence of UCRIT on the output characteristics A high lateral electric field in the channel causes the carrier velocity to saturate and limits the drain current. Parameter UCRIT accounts for this effect. Channel-Length Modulation (CLM) Influence of LAMBDA on the output characteristics The relative channel length reduction depends on the pinch-off point in the MOSFET channel near drain end. Depletion length coefficient (LAMBDA) models CLM effect.

9 Impact Ionization Current Influence of IBA and IBB, respectively, on the substrate current The substrate current is treated as a component of the total extrinsic current: I D = I DS + I DB Substrate current affects the total extrinsic conductances, in particular drain conductance (g DS ). (Trans-)Capacitances Model Intrinsic Capacitances C/(C ox WL) T OX =6.6nm V D =V S =V W=µm, L=5µm C GG C GD =C GS C GB Simulated: Measured: 1 V G [V] 3 Transcapacitances: derivation with respect to the terminal voltage: C MN = ± ( Q M ) M, N = G, D, S, B V N Accurate capacitances through all inversion levels. Symmetric C GS and C GD at V D =V S =. (6)

10 Polydepletion modeling Normalized Transcapacitances [-] n-channel T ox =4.5nm L=1µm N s = cm -3 N p = cm -3 V FB =-.9V D sim. model C GG C DG =C SG C BG V D = V S = Normalized Transcapacitances [-] n-channel T ox =4.5nm L=1µm N s = cm -3 N p = cm -3 V FB =-.9V D sim. model C GG C SG C DG CBG V D =1V V S = - -1 V G [V] V G [V] 1 3 Strengths of new polydepletion model: consistent effect from weak to strong inversion, conduction/saturation one single extra parameter: N POLY polydepletion only affects threshold voltage V TO, pinch-off voltage V P, and slope factor n Polydepletion modeling 6x1-6 5 n-channel L=1µm W=1µm T ox =4.5nm N s = cm -3 µ =6cm /Vs Θ=8.8nm/V I D [A] 4 3 D sim. model (N P = cm -3 ) D sim. model (N P =9.1.1 cm -3 ) V D =1V V D =.5V 1 V S = 1 V G - V FB [V] 3 comparison with D simulation with and without polydepletion no fitting parameters: same parameters used as for CV coherent with all other aspects of charge based model (IV, CV, thermal noise)

11 Vertical field dependent mobility modeling Deep sub- µm CMOS uses higher N sub lower µ Mobility µ depends on Q B, Q i (bias), N sub, T The scattering-limited mobility depends on, Coulomb-scattering (low field) [significant in.15µm CMOS even at room T] phonon-scattering (intermediate field) surface-roughness scattering (high field) Problem: difficult to address all dependencies together with few parameters mobility effects are position-dependent! Idea: use the charges model for modeling mobility model should have built-in temperature behaviour Vertical field dependent mobility modeling Effective Mobility µ eff µ PH ~ E eff -. µ C ~ [1+ζ*Q' i ] - µ SR ~ E eff µ eff T=3K T ox =1nm N sub =4e17cm µ = µ C µ PH µ SR µ C N sub [ 1 + ζ Q i ]. µ PH E eff µ SR E eff x Effective Vertical Field E eff E eff = Q B + η Q i ε si Strengths of new mobility model: directly linked to charges model position- (and bias-) dependence accounted for by integration along channel few parameters (5, none required for bias-dependence)

12 Velocity saturation modeling Velocity saturation is the main cause of reduction in short-channel MOS transistors NMOS and PMOS transistors have different µ ( E ) relationships NMOS is much more strongly affected by velocity saturation than PMOS I D µ µ = (NMOS); µ = (PMOS) 1 + ( E E c ) 1 + E E c µ Velocity saturation modeling has many implications: bias-dependence scaling asymptotic behaviour: series connection of multiple devices asymptotic behaviour at V DS Velocity saturation modeling 1 8 N=1 (approximate) N=1 (integral) V G /U T =1 1 8 N=1 (approximate) N=1 (integral) V G /U T =1 I D /I [-] 6 4 V S /U T = V G /U T =8 V G /U T =6 I D /I [-] 6 4 V S /U T = V G /U T =6 V G /U T =8 1 V G /U T =4 3 (V D -V S )/U T [-] NMOS δ= E c =3.1V/µm L=N*(.µm/N) V G /U T =4 3 (V D -V S )/U T [-] PMOS 4 δ=1 E c =5V/µm L=N*(.µm/N) 5 6 Strengths of new velocity saturation model: charge-based, from strong to weak inversion correct multiple series devices behaviour improved scaling correct asymptotic behaviour at V DS

13 Non-quasistatic (NQS) AC modeling New physics-based NQS model Exact analytical solutions for complex transadmittances 1st and nd-order approximations «-order» approximation: coincides with QS model! No additional parameters Normalization of different quantities: normalized Currents, Potentials, Charges normalized Coordinates, Time, Frequency Non-quasistatic (NQS) AC modeling y DG (magnitude&phase), measurements, exact model, 1 st - & nd -order approximations Strengths of new NQS model: valid from strong through moderate to weak inversion simple analytical expressions for (complex) transadmittances entirely consistent with polydepletion, mobility model, etc. easy to implement in circuit simulators (access to complex admittances matrix)

14 18 Intrinsic Model Parameters EKV v.6 Parameter Set Purpose NAME DESCRIPTION UNITS EXAMPLE Process parameters Doping & Mobility related parameters Short- & narrow-channel effect parameters Substrate current related parameters COX gate oxide capacitance per unit area F m 3.45E-3 XJ junction depth m.15e-6 DW channel width correction m -.5E-6 DL channel length correction m -.1E-6 VTO long-channel threshold voltage V.55 GAMMA body effect parameter V.7 PHI bulk Fermi potential (*) V.8 KP transconductance parameter A V 16E-6 E vertical characteristic field for mobility reduction V m 8E6 UCRIT longitudinal critical field V m 4.E6 LAMBDA depletion length coefficient (channel length modulation) -.3 WETA narrow-channel effect coefficient -.1 LETA short-channel effect coefficient -.3 Q reverse short-channel effect peak charge density A s m 5E-6 LK reverse short-channel effect characteristic length m.34e-6 IBA first impact ionization coefficient 1 / m 6E6 IBB second impact ionization coefficient V / m 35E6 IBN saturation voltage factor for impact ionization - EKV v.6 Parameter Set (cont.) Completed with 3 matching parameters 4 temperature parameters noise parameters NAME DESCRIPTION UNITS Example AVTO area related threshold voltage mismatch parameter Vm - DEV=15E-9 AKP area related gain mismatch parameter m - DEV=5E-9 AGAMMA area related body effect mismatch parameter Vm - DEV=1E-9 NAME DESCRIPTION UNITS Example TCV threshold voltage temperature coefficient V/K E-3 BEX mobility temperature exponent - - UCEX longitudinal critical field temperature exponent -.8 IBBT temperature coefficient for IBB 1/K 9.E-4 NAME DESCRIPTION UNITS Example KF flicker noise coefficient - AF flicker noise exponent - 1

15 EKV v.6 Parameter Extraction Methodology PRELIMINARY EXTRACTION WIDE LONG WIDE SHORT NARROW LONG NARROW SHORT Extraction of DL, DW, RSH from several geometries specific current measurement specific current measurement L specific current measurement final check and fine tuning VP vs. VG VTO, GAMMA, PHI VP vs. VG VP LETA vs. VG VP LETA vs. VG LETA, Q, LK VP vs. VG WETA ID vs. VG KP, E ID vs. VD UCRIT, LAMBDA IB vs. VG IBA, IBB, IBN Sequential task: parameter extraction methodology established for EKV v.6 performed using an array of transistors in the W/L plane. EKV v um CMOS 6 5 L=1um L=.5um 3 L=.18um L=1um.5 L=.5um 5 L=.18um 4. x x1-3 x Transfer characteristics IdVg and gmgvg (low drain voltage Vd)

16 EKV v um CMOS 3 L=1um 4 L=.5um 1 L=.18um L=1um 1-3 L=.5um L=.18um Output characteristics IdVd and gdsvd. D/A Converter Circuit I I I/ I/4 I/8 I/16 I/16 I I/ I/4 I/8 I/ W(I1) W(I) W(I3) W(I4) W(I5) W(I6) correct response (EKV v.6 model) 1.4 W(I1) W(I) W(I3) W(I4) W(I5) W(I6) incorrect response (competitor s model) Normalized Current (MSB-LSB) Normalized Current (MSB-LSB) e-7 1e-6 1e-5 1e-4 Reference Current.9 1e-7 1e-6 1e-5 1e-4 Reference Current

17 RF Characterization: De-embedding Open-Short Open EKV v.6 Open-Short f t Open, Open-Short deembedding and simulation data up to 11GHz nmosfet Device: 3 x um/.35um Bias condition: V g =V, V d =V RF Power Amplifier s m m s a) V supply =V b) V supply =.7V Output power vs. input power characteristics (in dbm) a) supply voltage V supply = V b) supply voltage V supply =.7V

18 Harmonic Oscillator MM9 EKV v.6 Simulation results: MM9 vs. EKV v.6 Summary EPFL EKV v.6 MOST model is a charge-based compact model Continuous, physics-based model valid for all bias conditions. Includes charge-based static and dynamic models, and noise. Uses a low number of parameters EPFL-EKV model enables the simulation of ultra deep submicron CMOS integrated systems, from DC to RF Experimental validation down to.18um CMOS Circuit applications have been presented The model and related parameter extraction methodology have been developed at Electronics Labs of EPFL Web resource: < Parameter extraction services and design support are available through Smart Silicon Systems, Lausanne Contact: modeling@smartsilicon.ch