Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers

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1 Mote Calo-Fee Pedictio o Spuiou Peoace o ECDLL-Baed Sytheize Ai Ojai, Behzad Megazadeh ad Atila Alvadpou Liköpig Uiveity Pot Pit.B.: Whe citig thi wok, cite the oigial aticle. Ai Ojai, Behzad Megazadeh ad Atila Alvadpou, Mote Calo-Fee Pedictio o Spuiou Peoace o ECDLL-Baed Sytheize, 15, IEEE Taactio o Cicuit ad Syte Pat 1: Regula Pape, (6), 1, IEEE. Peoal ue o thi ateial i peitted. Howeve, peiio to epit/epublih thi ateial o advetiig o pootioal pupoe o o ceatig ew collective wok o eale o editibutio to eve o lit, o to eue ay copyighted copoet o thi wok i othe wok ut be obtaied o the IEEE. Potpit available at: Liköpig Uiveity Electoic Pe

2 Mote Calo-Fee Pedictio o Spuiou Peoace o ECDLL-Baed Sytheize Ai Ojai, Studet Mebe, IEEE, Behzad Megazadeh, Mebe, IEEE, ad Atila Alvadpou, Seio Mebe, IEEE Abtact Mialiget o delay-locked loop (DLL) output edge ceate a udeied peiodicity, eultig i eeece haoic toe at the output pectu o edge-cobiig DLL (ECDLL)-baed equecy ytheize. Thee puiou toe coupt the pectal puity to a uacceptable level o wiele applicatio. The pu agitude i a ado vaiable deied by the eeece equecy, ube o DLL phae, haoic ode, tage-delay tadad deviatio (SD), duty cycle ditotio (DCD) o the eeece clock, ad tatic phae eo (SPE) o the lockedloop due to chage pup/phae detecto ipeectio. Hece, to etiate the puiou peoace o uch ytheize, exhautive Mote Calo (MC) iulatio ae ievitable. Baed o cloed-o expeio, thi pape popoe a geeic pedictive odel o haoic pu chaacteizatio o ECDLLbaed equecy ytheize, whoe pedictio accuacy i idepedet o ytheize deig paaete ad yte oidealitie. Theeoe, it ca eplace MC ethod to igiicatly acceleate the iteative deig pocedue o the ytheize, while povidig copaable pedictio i te o obute ad accuacy to that o MC. Validity, accuacy, ad obute o the popoed pedictio ethod agait wide-age value o oidealitie ae veiied though MC iulatio o both the behavioal odel ad taito-level odel o the ytheize i a tadad 65- CMOS techology. Idex Te delay iatch, DLL, duty cycle ditotio, equecy ytheize, haoic pu, Mote Calo, peiodic jitte, pedictive odel, tatic phae eo S I. ITRODUCTIO PECTRAL puity i a key equieet o equecy geeatio chee i wiele applicatio. I itege locked-loop-baed equecy ythei, whee the yte i locked to a low-equecy eeece clock, o-idealitie o the yte ca poduce a eoeou peiodicity, kow a peiodic jitte, eultig i appeaace o eeece haoic toe at the pectu o the ytheized caie. Thee haoic pu ca potetially dowcovet out-o-bad iteee ito the deied bad, couptig the wated igal. Delay-locked loop (DLL)-baed equecy ythei achieve low cloe-i phae oie by takig advatage o the lowaccuulative-jitte popety o DLL, which i obtaied by peiodically eettig the jitte back to zeo, ad coit o two ai appoache. I eciculatig DLL-baed appoach [1]-[7] whee the ultiplied clock i geeated by a iila echai a i ig voltage-cotolled-ocillato (VCO)- baed phae-locked loop (PLL), the haoic pu-to-caie atio (SCR) i diectly deied by the output equecy ad tatic phae eo (SPE) o the locked-loop [5], [7]. Edgecobiig DLL (ECDLL)-baed ytheize [8]-[16], o the othe had, ae oe poe to geeatio o puiou toe. A the caie i poduced by cobiig the equally-paced DLL output edge, ay ot o o-ideality, icludig SPE, duty cycle ditotio (DCD), ad tage-delay iatch (a a tochatic vaiable), will caue ialiget i thoe edge, degadig the puiou peoace. Coequetly, the SCR i ECDLL becoe a ado vaiable which i deied by the deig paaete, i.e., the eeece equecy ad ube o DLL phae, a well a the yte o-idealitie, i.e., SPE, DCD, ad tage-delay tadad deviatio (SD) [16]. A a eult, pu chaacteizatio o ECDLL-baed ytheize equie exhautive taiet Mote Calo (MC) iulatio which igiicatly low dow thei deig pocedue. Aog thoe pio at [1], [1], [13], [16] which tudy the puiou chaacteitic o ECDLL ytheize, a copeheive behavioal odel i popoed i [16] which iclude all the aoeetioed ouce o haoic pu i uch ytheize, ad povide a aalyi which lead to deivatio o a cloed-o appoxiatio o ytheize SCR. Howeve, thee ae two liitatio egadig the appoxiatio i [16]. Fit, the pedictio accuacy i guaateed oly o oe bouded value o SPE, DCD, ad delay SD, ad will degade othewie. Secod, due to depedecy o the pedictio eo upo the ytheize deig paaete ad yte o-idealitie, it i challegig to deie ad oulate geeic accuacy boud o the odel, without peoig cae-peciic MC iulatio o a give deig ceaio. Thee liitatio idicate the eceity ad ipotace o developig a oe geeic ad accuate pedictive odel, which povide pedictio that ae a obut a thoe achieved uig tatitical iulatio, ad hece, ca be eployed a a geeal eplaceet to MC ethod. I thi wok, the ai objective i to itigate thoe ajo liitatio o the appoxiatio odel i [16], by developig geeic ad obut pedictio which ca thooughly eplace exhautive MC ethod o pu chaacteizatio o ECDLL ytheize. I ode to do o, the pape it ivetigate the behavio o eve- ad odd-ode haoic pu at the output pectu o uch ytheize, ad deotate that depedig o the elatio aog SPE, DCD, ad delay SD value, eithe o thoe haoic ca have the laget pu level. Thi iplie that the SCR eed to be accuately chaacteized ad pedicted o both the adjacet ad alteate haoic to the caie. Atewad, the liitatio egadig the appoxiatio odel i [16] ae elaboated, ephaizig the eed o oe accuate pedictio. Accodigly, baed o cloed-o expeio, the pape popoe a geeic pedictive odel o ECDLL ytheize, whoe accuacy i

3 SCR etiatio i idepedet o the deig paaete o yte o-idealitie. Thi odel exhibit copaable accuacy ad obute with that o the MC ethod, wheea it eliiate the exteive iulatio tie which i ivolved i tatitical MC iulatio. Hece, the popoed odel ca eliably eplace MC ethod to acceleate the iteative deig pocedue o ECDLL-baed equecy ytheize. The pape i ogaized a ollow. Sectio II povide the eceay backgoud egadig the behavioal odel o ECDLL-baed equecy ytheize. I Sectio III, diiila chaacteitic o eve- ad odd-ode haoic pu ae ivetigated. Sectio IV deotate the liitatio o the odel i [16] o SCR etiatio, idicatig the dead o a oe geeic pedictive odel o SCR chaacteizatio, which i the popoed i Sectio V. I Sectio VI, the popoed odel i validated though MC iulatio o the behavioal odel a well a the taitolevel odel o ECDLL ytheize i a tadad 65- CMOS poce. Fially, the pape i cocluded i Sectio VII. II. BACKGROUD TO ECDLL BEHAVIORAL MODEL Aue that the chage pup (CP) ECDLL ytheize how i Fig. 1 eploy a voltage-cotolled delay lie (VCDL) o delay tage ad locked to the iig edge o a eeece clock o equecy e. The coepodig ECDLL odel which iclude SPE, DCD, ad delay iatch, i illutated a a tiig diaga i Fig.. The ytheized output i geeated by uatio o the iig ad allig DLL output cuet edge ( i odd) [8] ad cotai a udaetal toe at c = e ad eeece haoic pu at = e, whee i a itege haoic ode. It ca be how that the iatche o the iig- ad allig-edge delay ae odeled a two idepedet Gauia ado vaiable [13], [16]-[18], t ~ (, ), t ~ (, ) (1) d, d, whee µ, σ, µ, ad σ ae the ea ad vaiace o iigad allig-edge delay, epectively. I Fig., k odel the iput clock pulewidth. So, the tie-doai DCD value T dcd i T ( T ) k () dcd e Due to phae detecto (PD)/CP iatche, the lock peiod T lock deviate o T e with a tie-doai SPE o T pe. Hece, T T T. (3) lock e I the ea value o iig- ad allig-edge delay ae equal, i.e., µ = µ = µ = T lock/, the Δt d, ad Δt d, ae epeeted a Tlock td, tavg G, Tlock td, tavg G (4) whee i the tage idex, ϵ [1, ], ad G ad G ae two idepedet et o zeo-ea Gauia vaiable deied a G,..., ~ (, ), G,..., ~ (, ). (5) 1 G pe 1 G Futheoe, t avg i the aveaged u o ado vaiable G, i.e., the iig-edge delay iatche. It eeble the iatch-aveagig popety o the loop ad ca be deived a 1 tavg G ~,. (6) 1 Aalyzig Fouie eie o the DLL phae i Fig., a ad b e Ф 1 Ф Ф e Fouie coeiciet o the ytheized output ae oud [16] a A k G i tavg a i 1 co( t) dt (7) Te 1 Gi tavg Te i1 A k G i tavg b i 1 i( t) dt (8) Te 1 Gi tavg Te i1 whee A ad T e ae the aplitude ad peiod o the eeece clock, epectively. ote that (7) ad (8) coepod to the output Fouie coeiciet o a cuet-uatio edgecobie (EC) [8]. oethele, the peeted behavioal odel ca be geeally eployed to id the Fouie coeiciet o othe EC type. Uig (7) ad (8), the aalytical odel o SCR o a give haoic i expeed a UP V -Stage VCDL c PD D CP D 1 e k T e / T dcd T e (µ -t avg )+G 1 +G (µ -t avg )+G 1 + +G e µ -t avg +G 1 µ -t avg+g 1+k T lock (µ -t avg )+G 1 +G +k T pe Fig.. Tiig diaga o ECDLL, odelig SPE, DCD, ad delay iatch. SCR S C a b a b (9) whee S ad C ae the agitude o haoic pu ad caie, epectively. Rado vaiable SCR i (9) oulate the puiou peoace o ECDLL ytheize by odelig the eect o delay iatch aog the delay tage, SPE o the loop due to iatch o up ad dow igal i PD/CP, ad DCD o the eeece clock. Equatio (9) i utilized a a eeece aalytical odel o evaluatig the validity ad accuacy o the pedictio odel thoughout the pape. III. EVE-ORDER VERSUS ODD-ORDER HARMOIC SPURS I thi ectio, the puiou chaacteitic o the adjacet (eve-ode) ad alteate (odd-ode) haoic at the output pectu o ECDLL ytheize ae ivetigated. The pupoe i to deotate that depedig o the elatio aog SPE, DCD, ad delay SD value, eithe o the adjacet o alteate haoic to the caie ay have the laget pu level. Thi iplie that the puiou peoace equieet o a cetai wiele tadad eed to be veiied though Ф 1 D Ф Edge Cobie Fig. 1. Block diaga o a aalog ECDLL-baed equecy ytheize.

Fo the peeted aalyi thoughout the pape, a ECDLL ytheize i utilized that i locked to a eeece clock o e = 4 MHz ad eploy a VCDL with = 5 tage, poducig a caie equecy o c = 1 GHz.

4 3 Fig. 3. MC iulatio o the aalytical ea SCR o (9) o the adjacet ( = 1, = c e) ad alteate ( =, = c e) haoic a a uctio o oalized DCD ad SPE, uig oalized delay SD o % ad.%. pu aalyi o both the adjacet ad alteate haoic. ote that becaue i the utilized ECDLL odel peeted i the peviou ectio, i aued to be odd, the adjacet haoic with = ± 1 ae o eve ode. Fo the peeted aalyi thoughout the pape, a ECDLL ytheize i utilized that i locked to a eeece clock o e = 4 MHz ad eploy a VCDL with = 5 tage, poducig a caie equecy o c = 1 GHz. Futheoe, DCD ad SPE value ae wept o T dcd = 1 to 3 p ad T pe =.1 to 5 p, epectively. I additio, by chooig two oalized delay SD value o σ /µ = σ /µ = σ/µ =.% ad %, the ytheize SCR i iulated o the adjacet ( = c e) ad alteate ( = c e) haoic. Thu, ou dieet tet ceaio ae ivetigated. ote that the value o oidealitie ae elected i uch a way that ealitic coe cae egadig ECDLL ytheize ipleetatio ae coveed. MC iulatio o the aalytical odel o the ytheize give i (9) ae peoed i MATLAB ad the ea SCR eult ae plotted i Fig. 3. The X ad Y axe coepod to the oalized SPE ad DCD value, epectively. It ca be obeved o Fig. 3 that with a lage delay SD o % ad withi the utilized weep age o SPE ad DCD, the SCR o the adjacet haoic alway doiate that o the alteate oe. Howeve, it i ot the cae i alle value o delay SD ae utilized to achieve lowe SCR which i equied o wiele applicatio. A how i Fig. 3, o a delay SD o.% (a ode o agitude alle tha the peviou cae), a SPE iceae, the SCR o the alteate haoic ca doiate. Thi obevatio idicate that thee ae diiila puiou chaacteitic o the eve- ad odd-ode haoic. Howeve, a illutated i Fig. 3, thi dieet behavio i ot evealed i SPE ad DCD value ae abobed by a lage tage-delay iatch. Fo Fig. 3 it ca be peceived that the ea SCR o the adjacet haoic deped upo both the SPE ad DCD value. O the othe had, o the alteate haoic, the ea SCR i aily deied by SPE value, ad degade igiicatly a SPE gow, egadle o DCD value. Thi behavio ca be explaied by evaluatig the phae ialiget patte o the taiet waveo o the ECDLL output. Each o-ideality paaete (SPE, DCD, o delay SD) geeate a uique patte which eult i cetai haoic behavio. Ditictive chaacteitic o adjacet ad alteate haoic pu i ECDLL ytheize iply that to eue a cetai puiou peoace, the SCR o both the haoic pu eed to be aitaied below the equied value. A a coequece, a geeic pedictive odel hould be able to accuately etiate SCR, ot oly o wide-age value o o-idealitie, but alo o both eve ad odd haoic ode. IV. LIMITATIOS OF THE APPROXIMATE MODEL The liitatio egadig the appoxiatio odel o [16] ae addeed i thi ectio by evaluatig it accuacy i SCR etiatio i ou dieet tet ceaio, iila to thoe o the peviou ectio. Deotatig that the odel ca accuately pedict the puiou peoace oly whe the SPE ad DCD value ae uicietly abobed by the value o the delay SD, it liitatio o beig eployed a a geeal eplaceet to MC ethod o pu chaacteizatio o ECDLL-baed ytheize ae claiied. Auig that the haoic Fouie coeiciet a ad b o the ytheize output, expeed by (7) ad (8) epectively, ae two idepedetly ad idetically ditibuted (iid) ado vaiable, they ae appoxiated i [16] a two zeo-ea Gauia vaiable with equal vaiace, i.e., a ~ (, ), b ~ (, ) (1) ad hece, the pu agitude S a b i odeled a a Rayleigh ado vaiable [19], whoe ea value i S / (11) To exaie the odel accuacy, the iulated ad pedicted ea SCR value, o the aalytical odel (9) ad the cloed-o appoxiatio odel o [16], ae copaed ove wide-age value o SPE ad DCD. The eult ae plotted i Fig. 4 ad 5 epectively, o a lage ad all oalized delay SD o % ad.%. The tapaet plae coepod to the MC-iulated SCR ad the olid plae depict the pedicted eult. Whe delay SD i %, the pedictio ollow the iulatio quite cloely o both the adjacet ad alteate haoic pu how i Fig. 4 ad 4 epectively. Theeoe, o the it two ceaio, a quite acceptable accuacy i povided. Howeve, the achieved ea SCR value

4 Fig. 4. MC iulatio o the aalytical odel (9) veu the appoxiate pedictio odel o [16] o ea SCR value a a uctio o oalized SPE ad DCD, uig oalized delay SD o %: the adjacet, ad the alteate haoic. Fig. 5.

MC iulatio o the aalytical odel (9) veu the pedictio odel o [16] o ea SCR value a a uctio o oalized delay SD. (~ - dbc) uig the delay SD o % i ot adequate o wiele applicatio.

It ca be obeved that the accuacy o the pedictio i lagely degaded o both the adjacet ad alteate haoic, though with dieet eo chaacteitic. A how i Fig.

5, o a vey all o-ideality pai o T pe = 1 p (T pe/µ = 1 - ) ad T dcd = 1 p (T dcd/µ = 1-1, duty cycle = 49.6%), the pedictio eo i ad 3 db, o the adjacet ad alteate haoic, epectively.

5 4 Fig. 4. MC iulatio o the aalytical odel (9) veu the appoxiate pedictio odel o [16] o ea SCR value a a uctio o oalized SPE ad DCD, uig oalized delay SD o %: the adjacet, ad the alteate haoic. Fig. 5. MC iulatio o the aalytical odel (9) veu the appoxiate pedictio odel o [16] o ea SCR value a a uctio o oalized SPE ad DCD, uig oalized delay SD o.%: the adjacet, ad the alteate haoic. Fig. 6. MC iulatio o the aalytical odel (9) veu the pedictio odel o [16] o ea SCR value a a uctio o oalized delay SD. (~ - dbc) uig the delay SD o % i ot adequate o wiele applicatio. Hece, iila evaluatio o the ext two ceaio ae epeated uig a oe pactical delay SD o.% ad the eult ae plotted i Fig. 5. It ca be obeved that the accuacy o the pedictio i lagely degaded o both the adjacet ad alteate haoic, though with dieet eo chaacteitic. A how i Fig. 5, the pedictio accuacy o the adjacet haoic pu deped o both the SPE ad DCD value, wheea o the alteate haoic illutated i Fig. 5, the accuacy i aily depedet o the value o SPE. A it ca be ee o Fig. 5, o a vey all o-ideality pai o T pe = 1 p (T pe/µ = 1 - ) ad T dcd = 1 p (T dcd/µ = 1-1, duty cycle = 49.6%), the pedictio eo i ad 3 db, o the adjacet ad alteate haoic, epectively. Howeve, ice the adjacet pu i lage tha the alteate oe i thi cae, the coepodig 3-dB eo i ot ipotat. O the othe had, o a lage o-ideality pai o T pe = 5 p ad T dcd = 1 p, the ituatio i quite dieet. The pedictio eo becoe a high a 5 db ad 15 db o the adjacet ad alteate pu, epectively. Alo, i cotat to the peviou tet cae, the alteate pu i lage tha the adjacet oe. ote that thee eo will be agiied i the delay SD i uthe educed. Thi ca be oticed o Fig. 6 which illutate the ea SCR o the adjacet haoic with epect to oalized delay SD ad o a cotat SPE-DCD pai o (5p, 1p). The MC iulatio eult epeeted by the olid lie how that o all delay SD the ea SCR i aily deied by SPE ad DCD ad ot ipoved by uthe deceaig the delay SD. Howeve, the pedictio eult o the odel [16] (dahed lie) caot ollow that o the MC. Beide it coditioal accuacy, thee i aothe liitig acto coceig thi odel. It ca be cocluded by copaig Fig. 4 ad 5 that the accuacy coditio ae deied by the elatio aog the value o delay SD, SPE, ad DCD. Thi ake it coplicated to deie thoe coditio ad boud i uch a geeic o which ca be utilized o evey deig ceaio without eedig to peo

6 5 Fig. 7. SCR ado vaiable idetiicatio: MC hitoga o the aalytical odel (9), uig a delay SD o.% ad dieet (Tpe, Tdcd) pai: the adjacet, ad the alteate haoic. cae-peciic iulatio. Thi idicate that it i o geat ipotace to develop a oe geeic pedictive odel o SCR etiatio i ECDLL ytheize, whoe accuacy i idepedet o the deig paaete ad o-idealitie. V. A GEERIC PREDICTIVE MODEL Dieet appoache ca be eployed to id the pobability deity uctio (PDF) o the SCR ado vaiable deied i (9). A exact olutio would be to deive the PDF o Fouie coeiciet diectly o the ado oidealitie ad the, by taoatio o the eultig PDF ito thei oot u quae, calculate the PDF o SCR. By olvig (7) ad (8), ad applyig Taylo eie appoxiatio, expeio o a ad b ae deived a A a X X cx X 1 X X X X (1) A b whee X 1 c X X X X X X X X (13) Gi G, i X Gi G. (14) i i1 i1 i1 i1, k i, k ad c co (15) T T T e e Te co ( Te Tpe) T (16) dcd Te Te i ( Te Tpe) T. (17) dcd Te Deivig PDF o a ad b equie calculatio o PDF o the eleet o (1) ad (13), which ae i o o tie eie ad would eult i coplex aalyi. I ode to avoid dealig with coplicated deivatio ivolved i the diect PDF taoatio ethod, aothe appoach i eployed i thi wok. The idea i to aociate the SCR ado vaiable to a well-kow ditibutio o a to eicietly chaacteize the ea ad PDF o the ytheize SCR, baed o the popetie o that ecogized ditibutio. I ode to do o, a c c e obevatio i ade o dieet MC hitoga o the SCR it. The, the citeia egadig the idetiied ditibutio ae ipected o the output Fouie coeiciet o the ytheize, ad ially, the odel paaete ae deteied o (1) ad (13), uig oet ethod. A. Rado Vaiable Idetiicatio To idetiy the ditibutio egadig the agitude o the haoic pu, MC iulatio ae peoed o ytheize aalytical odel o (9), ad the eultig SCR hitoga ae plotted i Fig. 7. Fo thi pupoe, a all (ad oe pactical) delay SD o.% i utilized to bette obeve the eect o SPE ad DCD. Alo, ive dieet pai o (T pe, T dcd) ae eployed o the iulatio, i.e., A = (, ), B = (1p, 1p), C = (.5p, 1p), D = (5p, 1p), ad E = (5p, p). By evaluatig the plotted ditibutio i Fig. 7, it ca be oted that the SCR exhibit the ditibutio o Rayleigh ado vaiable o alle SPE-DCD value, i.e., A ad B pai. Movig towad the laget iput pai E, the ditibutio deotate a ooth taitio o Rayleigh to Gauia o. The obeved behavio i the iulated ditibutio i i act iila to that o Ricea ado vaiable [19]. Fo the deiitio o uch vaiable, the pu agitude S a b will have a Ricea ditibutio i the haoic Fouie coeiciet a ad b epeeted by (7) ad (8), ae two oal ado vaiable with equal vaiace which ae expeed a a ~ (, ), b ~ (, ) (18) a whee µ a ad µ b ae the ea value o a ad b epectively, ad σ i thei vaiace. Equatio (18) hould ow be ivetigated by evaluatig the vaiace ad ea o the haoic Fouie coeiciet. The vaiace o a ad b ae plotted i Fig. 8 o the adjacet haoic pu a a uctio o SPE ad DCD value. It ca be obeved that a ad b vaiace aitai withi a all age ad alot cloe to each othe, with a wot-cae dieece o aoud Fig. 8 how that the ea value o a ad b ae zeo o uicietly all SPE ad DCD value. Howeve, o geate value o SPE ad DCD, the ea value ted to deviate lagely o zeo, diatiyig citeia (1). Thi, i act, explai why o o-all SPE ad DCD value, the haoic pu level caot be pedicted accuately with the appoxiatio odel o [16]. ote that the oality b

E z ( ) exp z h hz p Z z I z K K K S e (1 K) I KI (19) () 1 whee h i the agitude o the vecto (µ a, µ b), i.e., h a (1) b ad K i the Rice acto which i deied a K h.

7 6 Fig. 8. MC iulatio egadig the vaiace, ad the ea o the adjacet haoic Fouie coeiciet ( = 1) a a uctio o oalized SPE ad DCD, uig oalized delay SD o.%. coditio o a ad b i (18) ca be veiied uig gaphical tet [16]. Theeoe, the haoic pu agitude S ae odeled a Ricea ado vaiable, with the ollowig PDF ad ea expeio [19]. E z ( ) exp z h hz p Z z I z K K K S e (1 K) I KI (19) () 1 whee h i the agitude o the vecto (µ a, µ b), i.e., h a (1) b ad K i the Rice acto which i deied a K h. () Alo, I (x) ad I 1(x) ae the odiied Beel uctio o the it kid with ode zeo ad oe, epectively, ad deied a 1 x co I ( x) e d (3) 1 x co I1 ( x) e co( ) d. (4) B. Deteiig Model Paaete Ate idetiyig the haoic pu agitude i ECDLL ytheize a Ricea ado vaiable, the ea ad PDF o S i (19) ad (), eed to be deteied by calculatig the value o h ad σ. Fidig the it ad ecod oet o (1) ad (13), the ea ad vaiace o a ad b ae deteied [16] a E a a E b b A A ) ( 1 c ( 1) (5) ) ( 1 c ( 1) (6) va a vab A ( ) T e 1 ( 1) i (7) i 4 1 i1 i1 The value o h ca be oud by ubtitutio o the ueical value o (5) ad (6) ito (1). ow, kowig the Ricea ado vaiable S, the atio ado vaiable SCR deied i (9) hould be deteied. A dicued i [16], it ca be how that the ado vaiable C which epeet the caie agitude, ca be appoxiated by it ea value E[C], ad hece, (9) i ipliied to SCR = S /E[C]. Thi iplie that the haoic Fouie coeiciet o S, i.e., a ad b, ae divided by a cotat to o the Fouie coeiciet o SCR a a ~ (, ), b ~ (, ) (8) a whee o lieaity, E C, E C, E C (9) a a b b Fo all delay SD value, E[C] i ipliied [16] to b k T it T i e pe e EC T (3) pe i( T T ) pe Theeoe, it i cocluded that SCR i alo a Ricea ado vaiable with a PDF ad ea deied i cloed-o a z ( ) exp z h h z p z I z (31) Z E K K SCR e (1 K) I KI whee e K (3) 1 a b h K h h E C (33) h K (34) VI. VALIDATIO OF THE PREDICTIVE MODEL Thi ectio evaluate the accuacy ad obute o the popoed pedictio ethod o pu chaacteizatio o ECDLL-baed ytheize, ove wide-age value o the yte o-idealitie. I ode to do o, the pedicted ea

7 Fig. 9. MC iulatio o the aalytical odel (9) veu the popoed pedictive odel (3) o ea SCR value a a uctio o oalized SPE ad DCD, uig oalized delay SD o %: the adjacet, ad the alteate haoic. Fig. 1.

MC iulatio o the aalytical odel (9) veu the popoed pedictive odel o ea SCR value a a uctio o oalized delay SD.

Futheoe, the accuacy o the popoed odel i veiied though MC iulatio o the SCR o thee dieet tet cae, uig a taito-level ECDLL-baed ytheize odel which i deiged i a tadad 65- CMOS techology. A.

8 7 Fig. 9. MC iulatio o the aalytical odel (9) veu the popoed pedictive odel (3) o ea SCR value a a uctio o oalized SPE ad DCD, uig oalized delay SD o %: the adjacet, ad the alteate haoic. Fig. 1. MC iulatio o the aalytical odel (9) veu the popoed pedictive odel (3) o ea SCR value a a uctio o oalized SPE ad DCD, uig oalized delay SD o.%: the adjacet, ad the alteate haoic. Fig. 11. MC iulatio o the aalytical odel (9) veu the popoed pedictive odel o ea SCR value a a uctio o oalized delay SD. SCR uig the popoed odel i copaed with that o attaied o the MC iulatio o the aalytical odel (9). Futheoe, the accuacy o the popoed odel i veiied though MC iulatio o the SCR o thee dieet tet cae, uig a taito-level ECDLL-baed ytheize odel which i deiged i a tadad 65- CMOS techology. A. Behavioal Validatio The ea SCR o the ytheize a a uctio o SPE ad DCD i illutated i Fig. 9 ad 1, uig a oalized delay SD o % ad.%, epectively. Fig. 9 ad 1 deotate the haoic pu level at = c e, while Fig. 9 ad 1 illutate the pu level at = c e. The olid plae epeet the MC iulatio eult o the aalytical odel o (9), wheea the olid lie with ake depict the pedicted ea SCR povided by (3). It ca be veiied o Fig. 9 ad 1 that the pedicted eult cloely ollow that o the MC iulatio. So a to veiy the accuacy o the popoed odel agait wide-age delay SD value, the ea SCR i plotted i Fig. 11 with epect to oalized delay SD which i wept o.1% to 5%. It ca be ee that the pedictio eult cloely atche that o the MC iulatio with a eo o db o σ/µ =.1% to 1%, 1 db at σ/µ = %, ad db at σ/µ = 3% (SCR ea -15 dbc). ote that to ipove the pedictio accuacy o vey lage delay SD value, highe ode Taylo eie ca be eployed to bette appoxiate ie ad coie uctio i (7) ad (8), ad hece, calculate the oe exact odel paaete, i.e., the ea ad vaiace o a ad b i (5), (6), ad (7). evethele, lage delay SD value ae i act avoided due to the tiget equieet o the output pu level i the cotext o equecy ythei o wiele applicatio. Copaig the eult i Fig. 9, 1, ad 11 with thoe i Fig. 4, 5, ad 6, epectively, eveal the achieved ipoveet i the pedictio obute ad iplie that the popoed odel

9 V p ca accuately chaacteize the puiou peoace o ECDLL o both the eve ad odd haoic ode, ove wide-age value o SPE, DCD, ad delay SD. B. Taito-Level Validatio Tet Poit = (T pe, T dcd ) e = Duy D 1 D D 5 Duy 4 MHz V Ф 1 Ф V-I 1 V-I out = 5 4 MHz Ф 5 V-I 5 Fig. 1. Scheatic o the iulated ECDLL ytheize i ope-loop egie. I the peviou pat, it wa veiied that the popoed pedictive odel cloely atche the behavioal odel o the ECDLL-baed ytheize o SCR etiatio ove wide-age value o the o-idealitie. I thi pat, the validity ad accuacy o the popoed odel i ivetigated by copaig the pedicted PDF o the cloed-o expeio (31), with MC iulatio hitoga o the taito-level odel o the ytheize, deiged i a tadad 65- CMOS poce. ote that due to the lage iulatio tie which i ivolved i MC iulatio o the taito-level deig, it i ot aodable to iulate the SCR o wide-age value o SPE ad DCD. A a coequece, thee dieet pai o (T pe, T dcd) ae itead elected o thi expeiet. Alo, ote that the epoted SCR value i thi pat coepod to the laget adjacet ad alteate haoic, i.e., ax(scr 1, SCR +1) o the adjacet, ad ax(scr, SCR +) o the alteate haoic. The iulated cheatic o the ECDLL ytheize i how i Fig. 1, whee 5 phae-hited output o the VCDL ae cobied uig 5 ideal tage o voltage-tocuet (V-I) covete to geeate the caie at c = 1 GHz. ote that i pactical ipleetatio [8], [1], a LC-tak load ca be ued to ehace the ECDLL output ipedace ad alo uppe the pu level depedig o it Q acto [16]. So a to educe the iulatio tie, the ytheize i iulated i a ope-loop egie. The eect o iatch betwee up ad dow igal i PD/CP i odeled by aually itoducig T pe i thi ope-loop cheatic. Due to the ope-loop opeatio, the actual SPE ay lightly deviate o it deigated value o each MC aple. I ode to obtai SCR o each MC aple, taiet iulatio ae peoed o the tetbech o Fig. 1 o duatio o 16.6, cotaiig 5 cycle o the eeece clock. Dicete Fouie tao (DFT) uctio i the applied to the ytheized output to calculate the coepodig agitude o the caie ad haoic pu. Siulatio ae peoed uig Cadece Specte while acceleated paallel iulato (APS) i eabled. Taiet oie optio o the iulato i ot eabled to peed up the MC iulatio. Howeve, ice the oie will eult i ado jitte o the DLL output phae which i ot idetical o cycle to cycle, it doe ot poduce a ixed-patte peiodicity. Theeoe, it will give ie to the phae oie athe tha the pu agitude. The eployed toleace optio o the iulato ae eltol = 1-6, vabtol = 1 V, ad iabtol = 1 A. Futheoe, the iulatio ae caied out o a igle.8-ghz poceo coe, with 3.7 GB o eoy. Coideig the utilized iguatio, the total iulatio tie egadig 1 4 MC TABLE I PREDICTIO MODEL PARAMETERS AD THEIR RELATIOS WITH TECHOLOGY, TRASISTOR-LEVEL, AD SYSTEM PARAMETERS Pedictio odel paaete σ /µ, σ /µ V p = 356V i V = 845V Taito-level ad techology paaete σi, σvth, VTH, WL, VDD, V, Vp, Aβ, AVTH aple i aoud 38 K (3.8 /aple). O the othe had, the pedictio ae caied out baed o cloed-o expeio whee o iulatio i ivolved. I ode to plot the popoed SCR PDF o (31) o a give haoic, Table I uaize how the pedictio odel paaete ae elated to the yte, taito-level, ad techology paaete. A how i Fig. 13, a cuet-taved delay tage with a output ivete bue i utilized ad caeully deiged to povide a ea delay o µ = µ µ 1 p. Eployig the iatch equatio o MOS device [17], the value o the oalized tage-delay SD o a cuet-taved delay tage o Fig. 13 i deived [13] a I VTH (35) I VDD VTH whee σ I ad σ VTH ae the cuet ad voltage-thehold SD, A I AV TH (36) I WL ( V V ) WL CS V DD=1. V 7.6/.8 V TH=-311V 15/.3 15/.3 V TH=-356V out 5/.3 5/.3 V TH=358V 5/.8 V TH=9V Fig. 13. Delay tage. Biaig coepod to the cae o zeo SPE. GS AV TH B Syte paaete TH CS Relatio (35) (37) λ, κc, κ, α, β Tdcd, Tpe,,, Te (15) (17) µa, µb, σ (5) (7) h, K (33), (34) 8 (37) VTH WL Alo, WL CS ad WL B ae the aea o the cuet-taved ad bue taito, ad A β ad A VTH ae the techologydepedet cotat. With the taito izig ad voltage biaig how i Fig. 13, ad the techology cotat o the taget tadad 65- CMOS poce, the delay SD value o σ /µ.7% ad σ /µ.9% ae obtaied. So a to obeve the accuacy o the pedictive odel whe the delay iatch doiate SPE ad DCD value, a SPE-DCD pai o (, ) i elected a the it tet cae. It ca be peceived o the SCR ditibutio i Fig. 14, that both the PDF o the popoed pedictive odel (olid lie with ake) give by (31), ad the appoxiatio odel o [16] (dahed lie) cloely atch the hitoga o the taito-level MC iulatio (ba chat), o eithe o the haoic. It ca alo be veiied that o thi tet cae whee the delay SD abob SPE ad DCD value, the ea SCR o the adjacet haoic, how i Fig. 14, i lage tha that o the alteate

9 Fig. 14. Pedicted PDF veu taito-level MC hitoga o SCR with (Tpe, Tdcd) = (, ): the laget adjacet, ad the laget alteate pu. Fig. 15.

Pedicted PDF veu taito-level MC hitoga o SCR with (Tpe, Tdcd) = (1p, 9.3p): the laget adjacet, ad the laget alteate pu. haoic plotted i Fig. 14.

6 V ad V p = 347.3 V i Fig. 13. Moeove, the value o DCD i iitially et to T dcd = 1 p by chagig the pulewidth o the quae wave iput clock ouce i the cheatic tetbech o Fig. 1. The eective DCD value howeve, i about 9.

It ca be ee that the SCR o the alteate haoic doiate that o the adjacet haoic by 4 db.

both haoic. A the lat expeiet ad to evaluate the accuacy o the odel whe the delay iatch i abobed by elatively lage SPE ad DCD value, a tet pai o (1p, 9.3p) i eployed.

10 9 Fig. 14. Pedicted PDF veu taito-level MC hitoga o SCR with (Tpe, Tdcd) = (, ): the laget adjacet, ad the laget alteate pu. Fig. 15. Pedicted PDF veu taito-level MC hitoga o SCR with (Tpe, Tdcd) = (5p, 9.3p): the laget adjacet, ad the laget alteate pu. Fig. 16. Pedicted PDF veu taito-level MC hitoga o SCR with (Tpe, Tdcd) = (1p, 9.3p): the laget adjacet, ad the laget alteate pu. haoic plotted i Fig. 14. The ecod tet i peoed uig the o-ideality pai (5p, 9.3p). ote that the equied T pe = 5 p i itoduced to both the iig ad allig-edge delay, by odiyig the bia voltage to V = V ad V p = V i Fig. 13. Moeove, the value o DCD i iitially et to T dcd = 1 p by chagig the pulewidth o the quae wave iput clock ouce i the cheatic tetbech o Fig. 1. The eective DCD value howeve, i about 9.3 p, accodig to the taiet iulatio o the waveo. A iila SPE-DCD pai ha bee utilized a the iput to the PDF expeio o the pedictive odel ad the copaio eult ae depicted i Fig. 15. It ca be ee that the SCR o the alteate haoic doiate that o the adjacet haoic by 4 db. It ca alo be peceived that the odel o [16] exhibit a pedictio eo o db ad 1 db, o the adjacet ad alteate haoic pu, epectively, while the popoed odel pedict the ea SCR accuately o both haoic. A the lat expeiet ad to evaluate the accuacy o the odel whe the delay iatch i abobed by elatively lage SPE ad DCD value, a tet pai o (1p, 9.3p) i eployed. To povide the equied T pe = 1 p, the bia voltage o the cuet-taved delay eleet ae chaged to V = V ad V p = V. It ca be oticed o Fig. 16 that i thi cae, the PDF o the popoed odel ca ollow the hitoga o the taito-level MC iulatio o both the adjacet ad alteate haoic pu, while the pedictio eo o [16] i agiied to 6 db ad 18 db. VII. COCLUSIO Evaluatio o puiou peoace i ECDLL-baed

1 equecy ytheize dead exhautive tatitical iulatio uig MC ethod which igiicatly low dow the iteative deig pocedue o uch ytheize.

The ipotat chaacteitic o the popoed odel i that it pedictio accuacy i idepedet o the deig paaete ad the yte o-idealitie.

The accuacy o the odel ha bee ivetigated though MC iulatio o the behavioal odel o the ytheize, agait wide-age value o SPE, DCD, ad tage-delay SD.

11 1 equecy ytheize dead exhautive tatitical iulatio uig MC ethod which igiicatly low dow the iteative deig pocedue o uch ytheize. Baed o the deived cloed-o expeio o the PDF ad ea o the pu agitude, thi pape itoduce a geeic pedictive odel o chaacteizig the puiou peoace o ECDLLbaed ytheize. The ipotat chaacteitic o the popoed odel i that it pedictio accuacy i idepedet o the deig paaete ad the yte o-idealitie. Hece, the odel i copaable to MC ethod i te o accuacy ad obute, wheea it alleviate the eed o exhautive tatitical iulatio. The accuacy o the odel ha bee ivetigated though MC iulatio o the behavioal odel o the ytheize, agait wide-age value o SPE, DCD, ad tage-delay SD. Moeove, the validity o the odel ha bee uthe ipected by peoig MC iulatio o a taito-level odel o the ytheize which i deiged i a tadad 65- CMOS poce. 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Alvadpou, A DLL-baed ijectio-locked equecy ytheize o WiMedia UWB, i Poc. IEEE It. Sypoiu Cicuit Syt., May 1, pp [1] T. C. Lee ad K. J. Hiao, The deig ad aalyi o a DLL-baed equecy ytheize o UWB applicatio, IEEE J. Solid State Cicuit, vol. 41, o. 6, pp , Ju. 6. [13] O. Caha et al., Aalyi o the pu chaacteitic o edge-cobiig DLL-baed equecy ultiplie, IEEE Ta. Cicuit Syt. II: Exp. Bie, vol. 56, o., pp , Feb. 9. [14]. Kha, M. Hoai, K.L.E. Law, A low powe equecy ytheize o 6-GHz wiele peoal aea etwok, IEEE Ta. Cicuit Syt. II: Exp. Bie, vol.58, o.1, pp. 6 66, Oct. 11. [15] H. J. g et al., A DLL-uppoted, low phae oie actioal- PLL with a widebad VCO ad a highly liea equecy ap geeato o FMCW ada, IEEE Ta. Cicuit Syt. I: Reg. Pape, vol. 6, o. 1, pp , Dec. 13. [16] A. Ojai, B. Megazadeh, ad A. Alvadpou, Modelig ad aalyi o haoic pu i DLL-baed equecy ytheize, IEEE Ta. Cicuit Syt. I: Reg. Pape, vol. PP, o. 99, pp. 1 1, Ju. 14. [17] M. J. M. Pelgo, A. C. J. Duiaije, ad A. P. G. Welbe, Matchig popetie o MOS taito, IEEE J. Solid-State Cicuit, vol. 4, o. 1, pp , Oct [18] T. P. Gia,. Tukka, ad E. Machad, Deity o the atio o two oal ado vaiable ad applicatio, Cou. Stat., Theoy Method, vol. 35, o. 7 9, pp , Sep. 6. [19] J.G. Poaki, ad M. Salehi, Digital Couicatio, 5 d Editio, McGaw Hill, 8. Ai Ojai (S 1) eceived the M.Sc. degee i electical egieeig o Liköpig Uiveity, Liköpig, Swede, i 8. He i cuetly wokig towad the Ph.D. degee at Liköpig Uiveity. Betwee 8 ad 9, he wa with Eico AB, Lud, Swede, whee he woked o clock geeatio ad ditibutio o Eico obile plato. Hi eeach iteet iclude phaelocked yte ad RF ytheize. Behzad Megazadeh (S M 9) eceived the B.Sc. degee i electical egieeig o Shai Uiveity o Techology, Teha, Ia, i, ad the M.Sc. ad Ph.D. degee i electical egieeig o Liköpig Uiveity, Liköpig, Swede, i 4 ad 8, epectively. He i cuetly a Aitat Poeo at the Depatet o Electical Egieeig, Liköpig Uiveity. Hi eeach iteet iclude lowpowe clockig techique, clock geeato ad equecy ytheize, ad high-data-ate wiele couicatio yte. D. Megazadeh wa the ecipiet o the 5th IEEE Midwet Sypoiu o Cicuit ad Syte Bet Studet Pape Awad i 7. Atila Alvadpou (M 99 SM 4) eceived the M.S. ad Ph.D. degee o Liköpig Uiveity, Swede, i 1995 ad 1999, epectively. Fo 1999 to 3, he wa a eio eeach cietit with Cicuit Reeach Lab, Itel Copoatio. I 3, he joied the depatet o Electical Egieeig, Liköpig Uiveity, a a Poeo o VLSI deig. Sice 4, he i the head o Electoic Device diviio. Hi eeach iteet iclude vaiou iue i deig o itegated cicuit ad yte i advaced aocale techologie, with a pecial ocu o eiciet data covete, wiele taceive ot-ed, ochip clock geeato ad ytheize, eo iteace electoic, lowpowe/high-peoace digital cicuit ad eoie, ad chip deig techique. He ha publihed oe tha 1 pape i iteatioal joual ad eece, ad hold 4 U.S. patet. Po. Alvadpou i a eio ebe o IEEE, ad ha eved o ay techical poga coittee o IEEE ad othe iteatioal eece, icludig the IEEE Solid-State Cicuit Coeece (ISSCC), ad Euopea Solid-State Cicuit Coeece (ESSCIRC). He ha alo eved a guet edito o IEEE JOURAL OF SOLID-STATE CIRCUITS.

rad / sec min rev 60sec. 2* rad / sec s

rad / sec min rev 60sec. 2* rad / sec s EE 559, Exa 2, Spig 26, D. McCalley, 75 iute allowed. Cloed Book, Cloed Note, Calculato Peitted, No Couicatio Device. (6 pt) Coide a.5 MW, 69 v, 5 Hz, 75 p DFG wid eegy yt. he paaete o the geeato ae give